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From: Yash Shah <yash.shah@sifive.com>
To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org
Cc: bp@suse.de, anup@brainfault.org, Jonathan.Cameron@huawei.com,
	wsa@kernel.org, sam@ravnborg.org, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org,
	sagar.kadam@sifive.com, sachin.ghadi@sifive.com,
	Yash Shah <yash.shah@sifive.com>
Subject: [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC
Date: Thu, 10 Dec 2020 15:58:01 +0530	[thread overview]
Message-ID: <1607596083-81480-1-git-send-email-yash.shah@sifive.com> (raw)

Add support for additional interrupt present in SiFive FU740 chip.

Changes:
v3:
- Rename the subject line of dt-binding patch
- Add the additional interrupt "DirFail" as the last entry so as to keep
  the order of all previous index same.

v2:
- Changes as per Rob Herring's request on v1

Yash Shah (2):
  dt-bindings: riscv: Update l2 cache DT documentation to add support
    for SiFive FU740
  RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive
    FU740

 .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
 drivers/soc/sifive/sifive_l2_cache.c               | 27 +++++++++++++++--
 2 files changed, 54 insertions(+), 7 deletions(-)

-- 
2.7.4


             reply	other threads:[~2020-12-10 10:29 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-10 10:28 Yash Shah [this message]
2020-12-10 10:28 ` [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
2020-12-11  1:55   ` Palmer Dabbelt
2020-12-11  3:46   ` Rob Herring
2020-12-10 10:28 ` [PATCH v3 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support " Yash Shah
2021-01-08  1:36 ` [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Palmer Dabbelt

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