From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
<dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
Yongqiang Niu <yongqiang.niu@mediatek.com>
Subject: [PATCH v2, 17/17] arm64: dts: mt8192: add display node
Date: Sat, 12 Dec 2020 12:11:57 +0800 [thread overview]
Message-ID: <1607746317-4696-18-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1607746317-4696-1-git-send-email-yongqiang.niu@mediatek.com>
add display node
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 130 +++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 7c0c233..da681b0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -17,6 +17,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl_2l2 = &ovl_2l2;
+ rdma4 = &rdma4;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -614,9 +619,134 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8192-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
};
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8192-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_CONFIG>,
+ <&mmsys CLK_MM_26MHZ>,
+ <&mmsys CLK_MM_DISP_MUTEX0>;
+ mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+ };
+
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+ // <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ };
+
+ ovl_2l0: ovl@14006000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+ // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,rdma_fifo_size = <5120>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8192-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+ };
+
+ ccorr0: ccorr@1400a000 {
+ compatible = "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
+ };
+
+ aal0: aal@1400b000 {
+ compatible = "mediatek,mt8192-disp-aal";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+ };
+
+ gamma0: gamma@1400c000 {
+ compatible = "mediatek,mt8192-disp-gamma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ };
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ //iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ };
+
+ dither0: dither@1400e000 {
+ compatible = "mediatek,mt8192-disp-dither";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ };
+
+ ovl_2l2: ovl@14014000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+ //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+ // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
+ };
+
+ rdma4: rdma@14015000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+ //iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+ mediatek,rdma_fifo_size = <2048>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8192-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
1.8.1.1.dirty
prev parent reply other threads:[~2020-12-12 4:15 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-12 4:11 [PATCH v2, 00/17] drm/mediatek: add support for mediatek SOC MT8192 Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 01/17] dt-bindings: mediatek: add description for postmask Yongqiang Niu
2020-12-15 14:49 ` Chun-Kuang Hu
2020-12-23 1:16 ` Yongqiang Niu
2020-12-15 16:20 ` Rob Herring
2020-12-12 4:11 ` [PATCH v2, 02/17] dt-bindings: mediatek: add CLK_MM_DISP_CONFIG control description for mt8192 display Yongqiang Niu
2020-12-16 15:17 ` Chun-Kuang Hu
2020-12-23 1:19 ` Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 03/17] dt-bindings: mediatek: add " Yongqiang Niu
2020-12-13 15:58 ` Chun-Kuang Hu
2020-12-15 16:23 ` Rob Herring
2020-12-12 4:11 ` [PATCH v2, 04/17] drm/mediatek: add component OVL_2L2 Yongqiang Niu
2020-12-13 1:15 ` Chun-Kuang Hu
2020-12-23 1:21 ` Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 05/17] drm/mediatek: add component POSTMASK Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 06/17] drm/mediatek: add component RDMA4 Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 07/17] drm/mediatek: add disp config and mm 26mhz clock into mutex device Yongqiang Niu
2020-12-15 13:37 ` Nicolas Boichat
2020-12-23 1:23 ` Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 08/17] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 09/17] drm/mediatek: check if fb is null Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 10/17] drm/mediatek: fix aal size config Yongqiang Niu
2020-12-16 15:10 ` Chun-Kuang Hu
2020-12-23 1:36 ` Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 11/17] drm/mediatek: fix dither " Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 12/17] drm/mediatek: fix gamma " Yongqiang Niu
2020-12-14 23:40 ` Chun-Kuang Hu
2020-12-23 1:37 ` Yongqiang Niu
2020-12-23 15:48 ` Chun-Kuang Hu
2020-12-12 4:11 ` [PATCH v2, 13/17] drm/mediatek: fix ccorr " Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 14/17] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register Yongqiang Niu
2020-12-15 13:42 ` Nicolas Boichat
2020-12-23 1:41 ` Yongqiang Niu
2020-12-12 4:11 ` [PATCH v2, 15/17] soc: mediatek: mmsys: add mt8192 mmsys support Yongqiang Niu
2020-12-13 16:02 ` Chun-Kuang Hu
2020-12-14 0:39 ` Yongqiang Niu
2020-12-15 14:44 ` Chun-Kuang Hu
2020-12-12 4:11 ` [PATCH v2, 16/17] drm/mediatek: add support for mediatek SOC MT8192 Yongqiang Niu
2020-12-12 4:11 ` Yongqiang Niu [this message]
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