[PATCH 06/11] dts: bindings: Document device tree bindings for ETE

[PATCH 06/11] dts: bindings: Document device tree bindings for ETE

[Anshuman Khandual]

From: Suzuki K Poulose <suzuki.poulose@arm.com>

Document the device tree bindings for Embedded Trace Extensions.
ETE can be connected to legacy coresight components and thus
could optionally contain a connection graph as described by
the CoreSight bindings.

Cc: devicetree@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 Documentation/devicetree/bindings/arm/ete.txt | 41 +++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/ete.txt

diff --git a/Documentation/devicetree/bindings/arm/ete.txt b/Documentation/devicetree/bindings/arm/ete.txt
new file mode 100644
index 0000000..b52b507
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ete.txt
@@ -0,0 +1,41 @@
+Arm Embedded Trace Extensions
+
+Arm Embedded Trace Extensions (ETE) is a per CPU trace component that
+allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
+architecture and has extended support for future architecture changes.
+The trace generated by the ETE could be stored via legacy CoreSight
+components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
+Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
+legacy CoreSight components, a node must be listed per instance, along
+with any optional connection graph as per the coresight bindings.
+See bindings/arm/coresight.txt.
+
+** ETE Required properties:
+
+- compatible : should be one of:
+	"arm,embedded-trace-extensions"
+
+- cpu : the CPU phandle this ETE belongs to.
+
+** Optional properties:
+- CoreSight connection graph, see bindings/arm/coresight.txt.
+
+** Example:
+
+ete_0 {
+	compatible = "arm,embedded-trace-extension";
+	cpu = <&cpu_0>;
+};
+
+ete_1 {
+	compatible = "arm,embedded-trace-extension";
+	cpu = <&cpu_1>;
+
+	out-ports {	/* legacy CoreSight connection */
+		port {
+			ete1_out_port: endpoint@0 {
+				remote-endpoint = <&funnel_in_port0>;
+			};
+		};
+	};
+};
-- 
2.7.4

[PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE

[Anshuman Khandual]

This patch documents the device tree binding in use for Arm TRBE.

Cc: devicetree@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V1:

- TRBE DT entry has been renamed as 'arm, trace-buffer-extension'

 Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt

diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt
new file mode 100644
index 0000000..001945d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/trbe.txt
@@ -0,0 +1,20 @@
+* Trace Buffer Extension (TRBE)
+
+Trace Buffer Extension (TRBE) is used for collecting trace data generated
+from a corresponding trace unit (ETE) using an in memory trace buffer.
+
+** TRBE Required properties:
+
+- compatible : should be one of:
+	       "arm,trace-buffer-extension"
+
+- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
+	       TRBE is only supported on a subset of the CPUs, please consult
+	       the arm,gic-v3 binding for details on describing a PPI partition.
+
+** Example:
+
+trbe {
+	compatible = "arm,trace-buffer-extension";
+	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+};
-- 
2.7.4

Re: [PATCH 06/11] dts: bindings: Document device tree bindings for ETE

[Rob Herring]

On Wed, Dec 23, 2020 at 03:33:38PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> Document the device tree bindings for Embedded Trace Extensions.
> ETE can be connected to legacy coresight components and thus
> could optionally contain a connection graph as described by
> the CoreSight bindings.
> 
> Cc: devicetree@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  Documentation/devicetree/bindings/arm/ete.txt | 41 +++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/ete.txt

Bindings are in schema format now, please convert this.

> 
> diff --git a/Documentation/devicetree/bindings/arm/ete.txt b/Documentation/devicetree/bindings/arm/ete.txt
> new file mode 100644
> index 0000000..b52b507
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ete.txt
> @@ -0,0 +1,41 @@
> +Arm Embedded Trace Extensions
> +
> +Arm Embedded Trace Extensions (ETE) is a per CPU trace component that
> +allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
> +architecture and has extended support for future architecture changes.
> +The trace generated by the ETE could be stored via legacy CoreSight
> +components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
> +Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
> +legacy CoreSight components, a node must be listed per instance, along
> +with any optional connection graph as per the coresight bindings.
> +See bindings/arm/coresight.txt.
> +
> +** ETE Required properties:
> +
> +- compatible : should be one of:
> +	"arm,embedded-trace-extensions"
> +
> +- cpu : the CPU phandle this ETE belongs to.

If this is 1:1 with CPUs, then perhaps it should be a child node of the 
CPU nodes.

> +
> +** Optional properties:
> +- CoreSight connection graph, see bindings/arm/coresight.txt.
> +
> +** Example:
> +
> +ete_0 {
> +	compatible = "arm,embedded-trace-extension";
> +	cpu = <&cpu_0>;
> +};
> +
> +ete_1 {
> +	compatible = "arm,embedded-trace-extension";
> +	cpu = <&cpu_1>;
> +
> +	out-ports {	/* legacy CoreSight connection */
> +		port {
> +			ete1_out_port: endpoint@0 {
> +				remote-endpoint = <&funnel_in_port0>;
> +			};
> +		};
> +	};
> +};
> -- 
> 2.7.4
> 

Re: [PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE

[Rob Herring]

On Wed, Dec 23, 2020 at 03:33:43PM +0530, Anshuman Khandual wrote:
> This patch documents the device tree binding in use for Arm TRBE.
> 
> Cc: devicetree@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V1:
> 
> - TRBE DT entry has been renamed as 'arm, trace-buffer-extension'
> 
>  Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt
> new file mode 100644
> index 0000000..001945d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/trbe.txt
> @@ -0,0 +1,20 @@
> +* Trace Buffer Extension (TRBE)
> +
> +Trace Buffer Extension (TRBE) is used for collecting trace data generated
> +from a corresponding trace unit (ETE) using an in memory trace buffer.
> +
> +** TRBE Required properties:
> +
> +- compatible : should be one of:
> +	       "arm,trace-buffer-extension"
> +
> +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
> +	       TRBE is only supported on a subset of the CPUs, please consult
> +	       the arm,gic-v3 binding for details on describing a PPI partition.
> +
> +** Example:
> +
> +trbe {
> +	compatible = "arm,trace-buffer-extension";
> +	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;

If only an interrupt, then could just be part of ETE? If not, how is 
this hardware block accessed? An interrupt alone is not enough unless 
there's some architected way to access.

Rob

Re: [PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE

[Anshuman Khandual]

On 1/3/21 10:35 PM, Rob Herring wrote:
> On Wed, Dec 23, 2020 at 03:33:43PM +0530, Anshuman Khandual wrote:
>> This patch documents the device tree binding in use for Arm TRBE.
>>
>> Cc: devicetree@vger.kernel.org
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> Changes in V1:
>>
>> - TRBE DT entry has been renamed as 'arm, trace-buffer-extension'
>>
>>  Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++
>>  1 file changed, 20 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt
>> new file mode 100644
>> index 0000000..001945d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/trbe.txt
>> @@ -0,0 +1,20 @@
>> +* Trace Buffer Extension (TRBE)
>> +
>> +Trace Buffer Extension (TRBE) is used for collecting trace data generated
>> +from a corresponding trace unit (ETE) using an in memory trace buffer.
>> +
>> +** TRBE Required properties:
>> +
>> +- compatible : should be one of:
>> +	       "arm,trace-buffer-extension"
>> +
>> +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
>> +	       TRBE is only supported on a subset of the CPUs, please consult
>> +	       the arm,gic-v3 binding for details on describing a PPI partition.
>> +
>> +** Example:
>> +
>> +trbe {
>> +	compatible = "arm,trace-buffer-extension";
>> +	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
> 
> If only an interrupt, then could just be part of ETE? If not, how is 
> this hardware block accessed? An interrupt alone is not enough unless 
> there's some architected way to access.

TRBE hardware block is accessed via respective new system registers but the
PPI number where the IRQ will be triggered for various buffer events, would
depend on the platform as defined in the SBSA.

TRBE would need a ETE to work but the reverse is not true. ETE might just
be present without a corresponding TRBE and can work with traditional sinks.
Hence just wondering whether it would be prudent to add the TRBE interrupt
number as part of the ETE DT specification.

Re: [PATCH 06/11] dts: bindings: Document device tree bindings for ETE

[Suzuki K Poulose]

Hi Rob,

On 1/3/21 5:02 PM, Rob Herring wrote:
> On Wed, Dec 23, 2020 at 03:33:38PM +0530, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> Document the device tree bindings for Embedded Trace Extensions.
>> ETE can be connected to legacy coresight components and thus
>> could optionally contain a connection graph as described by
>> the CoreSight bindings.
>>
>> Cc: devicetree@vger.kernel.org
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   Documentation/devicetree/bindings/arm/ete.txt | 41 +++++++++++++++++++++++++++
>>   1 file changed, 41 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/ete.txt
> 
> Bindings are in schema format now, please convert this.
> 

Sure, will do that.

>>
>> diff --git a/Documentation/devicetree/bindings/arm/ete.txt b/Documentation/devicetree/bindings/arm/ete.txt
>> new file mode 100644
>> index 0000000..b52b507
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/ete.txt
>> @@ -0,0 +1,41 @@
>> +Arm Embedded Trace Extensions
>> +
>> +Arm Embedded Trace Extensions (ETE) is a per CPU trace component that
>> +allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
>> +architecture and has extended support for future architecture changes.
>> +The trace generated by the ETE could be stored via legacy CoreSight
>> +components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
>> +Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
>> +legacy CoreSight components, a node must be listed per instance, along
>> +with any optional connection graph as per the coresight bindings.
>> +See bindings/arm/coresight.txt.
>> +
>> +** ETE Required properties:
>> +
>> +- compatible : should be one of:
>> +	"arm,embedded-trace-extensions"
>> +
>> +- cpu : the CPU phandle this ETE belongs to.
> 
> If this is 1:1 with CPUs, then perhaps it should be a child node of the
> CPU nodes.

Yes, it is 1:1 with the CPUs. I have tried to keep this aligned with that of
"coresight-etm4x". The same driver handles both. The only reason why this
was separated from the "coresight.txt" is to describe the new configurations
possible (read, TRBE).

That said, I am happy to move this under the CPU, if Mathieu is happy with
the diversion.

Thanks for the review.

Suzuki

Re: [PATCH 06/11] dts: bindings: Document device tree bindings for ETE

[Mathieu Poirier]

On Mon, Jan 04, 2021 at 02:42:08PM +0000, Suzuki K Poulose wrote:
> Hi Rob,
> 
> On 1/3/21 5:02 PM, Rob Herring wrote:
> > On Wed, Dec 23, 2020 at 03:33:38PM +0530, Anshuman Khandual wrote:
> > > From: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > 
> > > Document the device tree bindings for Embedded Trace Extensions.
> > > ETE can be connected to legacy coresight components and thus
> > > could optionally contain a connection graph as described by
> > > the CoreSight bindings.
> > > 
> > > Cc: devicetree@vger.kernel.org
> > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > > Cc: Mike Leach <mike.leach@linaro.org>
> > > Cc: Rob Herring <robh@kernel.org>
> > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > ---
> > >   Documentation/devicetree/bindings/arm/ete.txt | 41 +++++++++++++++++++++++++++
> > >   1 file changed, 41 insertions(+)
> > >   create mode 100644 Documentation/devicetree/bindings/arm/ete.txt
> > 
> > Bindings are in schema format now, please convert this.
> > 
> 
> Sure, will do that.
> 
> > > 
> > > diff --git a/Documentation/devicetree/bindings/arm/ete.txt b/Documentation/devicetree/bindings/arm/ete.txt
> > > new file mode 100644
> > > index 0000000..b52b507
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/arm/ete.txt
> > > @@ -0,0 +1,41 @@
> > > +Arm Embedded Trace Extensions
> > > +
> > > +Arm Embedded Trace Extensions (ETE) is a per CPU trace component that
> > > +allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
> > > +architecture and has extended support for future architecture changes.
> > > +The trace generated by the ETE could be stored via legacy CoreSight
> > > +components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
> > > +Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
> > > +legacy CoreSight components, a node must be listed per instance, along
> > > +with any optional connection graph as per the coresight bindings.
> > > +See bindings/arm/coresight.txt.
> > > +
> > > +** ETE Required properties:
> > > +
> > > +- compatible : should be one of:
> > > +	"arm,embedded-trace-extensions"
> > > +
> > > +- cpu : the CPU phandle this ETE belongs to.
> > 
> > If this is 1:1 with CPUs, then perhaps it should be a child node of the
> > CPU nodes.
> 
> Yes, it is 1:1 with the CPUs. I have tried to keep this aligned with that of
> "coresight-etm4x". The same driver handles both. The only reason why this
> was separated from the "coresight.txt" is to describe the new configurations
> possible (read, TRBE).

Would it be possible to keep the CPU handle rather than moving things under the
CPU nodes?  ETMv3.x and ETMv4.x are using a handle and as Suzuki points out ETE
and ETMv4.x are sharing the same driver.  Proceeding differently for the ETE
would be terribly confusing.

> 
> That said, I am happy to move this under the CPU, if Mathieu is happy with
> the diversion.
> 
> Thanks for the review.
> 
> Suzuki

Re: [PATCH 06/11] dts: bindings: Document device tree bindings for ETE

[Rob Herring]

On Mon, Jan 4, 2021 at 11:15 AM Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Mon, Jan 04, 2021 at 02:42:08PM +0000, Suzuki K Poulose wrote:
> > Hi Rob,
> >
> > On 1/3/21 5:02 PM, Rob Herring wrote:
> > > On Wed, Dec 23, 2020 at 03:33:38PM +0530, Anshuman Khandual wrote:
> > > > From: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > >
> > > > Document the device tree bindings for Embedded Trace Extensions.
> > > > ETE can be connected to legacy coresight components and thus
> > > > could optionally contain a connection graph as described by
> > > > the CoreSight bindings.
> > > >
> > > > Cc: devicetree@vger.kernel.org
> > > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > > > Cc: Mike Leach <mike.leach@linaro.org>
> > > > Cc: Rob Herring <robh@kernel.org>
> > > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > > ---
> > > >   Documentation/devicetree/bindings/arm/ete.txt | 41 +++++++++++++++++++++++++++
> > > >   1 file changed, 41 insertions(+)
> > > >   create mode 100644 Documentation/devicetree/bindings/arm/ete.txt
> > >
> > > Bindings are in schema format now, please convert this.
> > >
> >
> > Sure, will do that.
> >
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/arm/ete.txt b/Documentation/devicetree/bindings/arm/ete.txt
> > > > new file mode 100644
> > > > index 0000000..b52b507
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/arm/ete.txt
> > > > @@ -0,0 +1,41 @@
> > > > +Arm Embedded Trace Extensions
> > > > +
> > > > +Arm Embedded Trace Extensions (ETE) is a per CPU trace component that
> > > > +allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
> > > > +architecture and has extended support for future architecture changes.
> > > > +The trace generated by the ETE could be stored via legacy CoreSight
> > > > +components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
> > > > +Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
> > > > +legacy CoreSight components, a node must be listed per instance, along
> > > > +with any optional connection graph as per the coresight bindings.
> > > > +See bindings/arm/coresight.txt.
> > > > +
> > > > +** ETE Required properties:
> > > > +
> > > > +- compatible : should be one of:
> > > > + "arm,embedded-trace-extensions"
> > > > +
> > > > +- cpu : the CPU phandle this ETE belongs to.
> > >
> > > If this is 1:1 with CPUs, then perhaps it should be a child node of the
> > > CPU nodes.
> >
> > Yes, it is 1:1 with the CPUs. I have tried to keep this aligned with that of
> > "coresight-etm4x". The same driver handles both. The only reason why this
> > was separated from the "coresight.txt" is to describe the new configurations
> > possible (read, TRBE).
>
> Would it be possible to keep the CPU handle rather than moving things under the
> CPU nodes?  ETMv3.x and ETMv4.x are using a handle and as Suzuki points out ETE
> and ETMv4.x are sharing the same driver.  Proceeding differently for the ETE
> would be terribly confusing.

Yeah, no problem.

Rob

Re: [PATCH 11/11] dts: bindings: Document device tree binding for Arm TRBE

[Suzuki K Poulose]

On 1/4/21 3:44 AM, Anshuman Khandual wrote:
> 
> On 1/3/21 10:35 PM, Rob Herring wrote:
>> On Wed, Dec 23, 2020 at 03:33:43PM +0530, Anshuman Khandual wrote:
>>> This patch documents the device tree binding in use for Arm TRBE.
>>>
>>> Cc: devicetree@vger.kernel.org
>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> Cc: Mike Leach <mike.leach@linaro.org>
>>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>> ---
>>> Changes in V1:
>>>
>>> - TRBE DT entry has been renamed as 'arm, trace-buffer-extension'
>>>
>>>   Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++
>>>   1 file changed, 20 insertions(+)
>>>   create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt
>>> new file mode 100644
>>> index 0000000..001945d
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/trbe.txt
>>> @@ -0,0 +1,20 @@
>>> +* Trace Buffer Extension (TRBE)
>>> +
>>> +Trace Buffer Extension (TRBE) is used for collecting trace data generated
>>> +from a corresponding trace unit (ETE) using an in memory trace buffer.
>>> +
>>> +** TRBE Required properties:
>>> +
>>> +- compatible : should be one of:
>>> +	       "arm,trace-buffer-extension"
>>> +
>>> +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
>>> +	       TRBE is only supported on a subset of the CPUs, please consult
>>> +	       the arm,gic-v3 binding for details on describing a PPI partition.
>>> +
>>> +** Example:
>>> +
>>> +trbe {
>>> +	compatible = "arm,trace-buffer-extension";
>>> +	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
>>
>> If only an interrupt, then could just be part of ETE? If not, how is
>> this hardware block accessed? An interrupt alone is not enough unless
>> there's some architected way to access.
> 
> TRBE hardware block is accessed via respective new system registers but the
> PPI number where the IRQ will be triggered for various buffer events, would
> depend on the platform as defined in the SBSA.

That is correct. TRBE is accessed via CPU system registers. The IRQ is specifically
for the TRBE unit to handle buffer overflow situations and other errors in the
buffer handling. Please include this information in the description section of
the bindings.

Also, it may be worth switching this to yaml format.

Suzuki