* [PATCH v1 2/5] dt-bindings: usb: dwc3: add description for rk3328
2021-02-01 19:41 [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
@ 2021-02-01 19:41 ` Johan Jonker
2021-02-01 19:41 ` [PATCH v1 3/5] usb: dwc3: of-simple: add compatible " Johan Jonker
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Johan Jonker @ 2021-02-01 19:41 UTC (permalink / raw)
To: heiko
Cc: robh+dt, gregkh, balbi, linux-usb, devicetree, linux-rockchip,
linux-arm-kernel, linux-kernel
Add description for "rockchip,rk3328-dwc3".
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
index 681086fa6..f4de1b2ee 100644
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -12,9 +12,11 @@ maintainers:
properties:
compatible:
enum:
+ - rockchip,rk3328-dwc3
- rockchip,rk3399-dwc3
clocks:
+ minItems: 3
items:
- description:
Controller reference clock, must to be 24 MHz
@@ -31,6 +33,7 @@ properties:
Controller grf clock
clock-names:
+ minItems: 3
items:
- const: ref_clk
- const: suspend_clk
--
2.11.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v1 3/5] usb: dwc3: of-simple: add compatible for rk3328
2021-02-01 19:41 [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
2021-02-01 19:41 ` [PATCH v1 2/5] dt-bindings: usb: dwc3: add description for rk3328 Johan Jonker
@ 2021-02-01 19:41 ` Johan Jonker
2021-02-01 19:41 ` [PATCH v1 4/5] arm64: dts: rockchip: add rk3328 dwc3 usb controller node Johan Jonker
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Johan Jonker @ 2021-02-01 19:41 UTC (permalink / raw)
To: heiko
Cc: robh+dt, gregkh, balbi, linux-usb, devicetree, linux-rockchip,
linux-arm-kernel, linux-kernel
From: Cameron Nemo <cnemo@tutanota.com>
Add a compatible to be hooked into by the Rockchip rk3328 device tree.
The rk3399 compatible cannot be reused because the rk3328 SoCs may
require a specialized driver in the future and old device trees must
remain compatible with newer kernels.
Signed-off-by: Cameron Nemo <cnemo@tutanota.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index e62ecd22b..93bc34328 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -171,6 +171,7 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
};
static const struct of_device_id of_dwc3_simple_match[] = {
+ { .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "xlnx,zynqmp-dwc3" },
{ .compatible = "cavium,octeon-7130-usb-uctl" },
--
2.11.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v1 4/5] arm64: dts: rockchip: add rk3328 dwc3 usb controller node
2021-02-01 19:41 [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
2021-02-01 19:41 ` [PATCH v1 2/5] dt-bindings: usb: dwc3: add description for rk3328 Johan Jonker
2021-02-01 19:41 ` [PATCH v1 3/5] usb: dwc3: of-simple: add compatible " Johan Jonker
@ 2021-02-01 19:41 ` Johan Jonker
2021-02-01 19:41 ` [PATCH v1 5/5] dts64: rockchip: enable dwc3 usb for A95X Z2 Johan Jonker
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Johan Jonker @ 2021-02-01 19:41 UTC (permalink / raw)
To: heiko
Cc: robh+dt, gregkh, balbi, linux-usb, devicetree, linux-rockchip,
linux-arm-kernel, linux-kernel
From: Cameron Nemo <cnemo@tutanota.com>
RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Cameron Nemo <cnemo@tutanota.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 17709faf6..2bb666d35 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -987,6 +987,33 @@
status = "disabled";
};
+ usbdrd3: usb@ff600000 {
+ compatible = "rockchip,rk3328-dwc3";
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+ <&cru ACLK_USB3OTG>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3: usb@ff600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff600000 0x0 0x100000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+ };
+
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.11.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v1 5/5] dts64: rockchip: enable dwc3 usb for A95X Z2
2021-02-01 19:41 [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
` (2 preceding siblings ...)
2021-02-01 19:41 ` [PATCH v1 4/5] arm64: dts: rockchip: add rk3328 dwc3 usb controller node Johan Jonker
@ 2021-02-01 19:41 ` Johan Jonker
2021-02-01 20:46 ` [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
2021-02-02 17:44 ` Rob Herring
5 siblings, 0 replies; 8+ messages in thread
From: Johan Jonker @ 2021-02-01 19:41 UTC (permalink / raw)
To: heiko
Cc: robh+dt, gregkh, balbi, linux-usb, devicetree, linux-rockchip,
linux-arm-kernel, linux-kernel
Enable dwc3 usb for A95X Z2.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
index 30c73ef25..b26c653c6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
@@ -357,6 +357,15 @@
status = "okay";
};
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
--
2.11.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
2021-02-01 19:41 [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
` (3 preceding siblings ...)
2021-02-01 19:41 ` [PATCH v1 5/5] dts64: rockchip: enable dwc3 usb for A95X Z2 Johan Jonker
@ 2021-02-01 20:46 ` Johan Jonker
2021-02-02 20:06 ` Rob Herring
2021-02-02 17:44 ` Rob Herring
5 siblings, 1 reply; 8+ messages in thread
From: Johan Jonker @ 2021-02-01 20:46 UTC (permalink / raw)
To: heiko
Cc: robh+dt, gregkh, balbi, linux-usb, devicetree, linux-rockchip,
linux-arm-kernel, linux-kernel
Hi Rob,
See questions below.
Kind regards,
Johan Jonker
On 2/1/21 8:41 PM, Johan Jonker wrote:
> In the past Rockchip dwc3 usb nodes were manually checked.
> With the conversion of snps,dwc3.yaml as common document
> we now can convert rockchip,dwc3.txt to yaml as well.
>
> Added properties for rk3399 are:
> resets
> reset-names
>
> Generic properties that are now also filtered:
> "#address-cells"
> "#size-cells"
> ranges
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 -----------
> .../devicetree/bindings/usb/rockchip,dwc3.yaml | 107 +++++++++++++++++++++
> 2 files changed, 107 insertions(+), 56 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> deleted file mode 100644
> index 945204932..000000000
> --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -Rockchip SuperSpeed DWC3 USB SoC controller
> -
> -Required properties:
> -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
> -- clocks: A list of phandle + clock-specifier pairs for the
> - clocks listed in clock-names
> -- clock-names: Should contain the following:
> - "ref_clk" Controller reference clk, have to be 24 MHz
> - "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
> - "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
> - operation and >= 30MHz for HS operation
> - "grf_clk" Controller grf clk
> -
> -Required child node:
> -A child node must exist to represent the core DWC3 IP block. The name of
> -the node is not important. The content of the node is defined in dwc3.txt.
> -
> -Phy documentation is provided in the following places:
> -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
> -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
> -
> -Example device nodes:
> -
> - usbdrd3_0: usb@fe800000 {
> - compatible = "rockchip,rk3399-dwc3";
> - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
> - clock-names = "ref_clk", "suspend_clk",
> - "bus_clk", "grf_clk";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - usbdrd_dwc3_0: dwc3@fe800000 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0xfe800000 0x0 0x100000>;
> - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> - dr_mode = "otg";
> - };
> - };
> -
> - usbdrd3_1: usb@fe900000 {
> - compatible = "rockchip,rk3399-dwc3";
> - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
> - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
> - clock-names = "ref_clk", "suspend_clk",
> - "bus_clk", "grf_clk";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - usbdrd_dwc3_1: dwc3@fe900000 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0xfe900000 0x0 0x100000>;
> - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> - dr_mode = "otg";
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> new file mode 100644
> index 000000000..681086fa6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip SuperSpeed DWC3 USB SoC controller
> +
> +maintainers:
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3399-dwc3
> +
> + clocks:
> + items:
> + - description:
> + Controller reference clock, must to be 24 MHz
> + - description:
> + Controller suspend clock, must to be 24 MHz or 32 KHz
> + - description:
> + Master/Core clock, must to be >= 62.5 MHz for SS
> + operation and >= 30MHz for HS operation
> + - description:
> + Controller aclk_usb3_rksoc_axi_perf clock
> + - description:
> + Controller aclk_usb3 clock
> + - description:
> + Controller grf clock
> +
> + clock-names:
> + items:
> + - const: ref_clk
> + - const: suspend_clk
> + - const: bus_clk
> + - const: aclk_usb3_rksoc_axi_perf
> + - const: aclk_usb3
This was not in the original document, but is needed to compile.
> + - const: grf_clk
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + const: usb3-otg
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + ranges: true
> +
> +patternProperties:
> + "^usb@[a-f0-9]+$":
> + type: object
> +
> + $ref: "snps,dwc3.yaml"
> +
> + description:
> + A child node must exist to represent the core DWC3 IP block.
> + The content of the node is defined in snps,dwc3.yaml.
> +
> + Phy documentation is provided in the following places.
> +
> + USB2.0 PHY
> + Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
> +
> + Type-C PHY
> + Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> +
> + unevaluatedProperties: false
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - "#address-cells"
> + - "#size-cells"
> + - ranges
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rk3399-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + usbdrd3_0: usb@fe800000 {
The rk3399 has 2 dwc3 usb nodes. When we remove @fe800000 and @fe900000
in the rk3399.dtsi it complains about 2 identical usb root nodenames.
For this example to pass change to:
usbdrd3_0: usb ??
What to do with it in the dtsi??
> + compatible = "rockchip,rk3399-dwc3";
> + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
> + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
> + clock-names = "ref_clk", "suspend_clk",
> + "bus_clk", "aclk_usb3_rksoc_axi_perf",
> + "aclk_usb3", "grf_clk";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Ranges generates notifications. Could you advise if that is needed in
this dwc3 usb context and rk3399.dtsi or should it be removed?
> + usbdrd_dwc3_0: usb@fe800000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0xfe800000 0x0 0x100000>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "otg";
> + };
> + };
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
2021-02-01 20:46 ` [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
@ 2021-02-02 20:06 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2021-02-02 20:06 UTC (permalink / raw)
To: Johan Jonker
Cc: heiko@sntech.de, Greg Kroah-Hartman, Felipe Balbi, Linux USB List,
devicetree, open list:ARM/Rockchip SoC..., linux-arm-kernel,
linux-kernel@vger.kernel.org
On Mon, Feb 1, 2021 at 2:46 PM Johan Jonker <jbx6244@gmail.com> wrote:
>
> Hi Rob,
>
> See questions below.
>
> Kind regards,
>
> Johan Jonker
>
> On 2/1/21 8:41 PM, Johan Jonker wrote:
> > In the past Rockchip dwc3 usb nodes were manually checked.
> > With the conversion of snps,dwc3.yaml as common document
> > we now can convert rockchip,dwc3.txt to yaml as well.
> >
> > Added properties for rk3399 are:
> > resets
> > reset-names
> >
> > Generic properties that are now also filtered:
> > "#address-cells"
> > "#size-cells"
> > ranges
> >
> > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > ---
> > .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 -----------
> > .../devicetree/bindings/usb/rockchip,dwc3.yaml | 107 +++++++++++++++++++++
> > 2 files changed, 107 insertions(+), 56 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> > create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> > deleted file mode 100644
> > index 945204932..000000000
> > --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> > +++ /dev/null
> > @@ -1,56 +0,0 @@
> > -Rockchip SuperSpeed DWC3 USB SoC controller
> > -
> > -Required properties:
> > -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
> > -- clocks: A list of phandle + clock-specifier pairs for the
> > - clocks listed in clock-names
> > -- clock-names: Should contain the following:
> > - "ref_clk" Controller reference clk, have to be 24 MHz
> > - "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
> > - "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
> > - operation and >= 30MHz for HS operation
> > - "grf_clk" Controller grf clk
> > -
> > -Required child node:
> > -A child node must exist to represent the core DWC3 IP block. The name of
> > -the node is not important. The content of the node is defined in dwc3.txt.
> > -
> > -Phy documentation is provided in the following places:
> > -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
> > -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
> > -
> > -Example device nodes:
> > -
> > - usbdrd3_0: usb@fe800000 {
> > - compatible = "rockchip,rk3399-dwc3";
> > - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> > - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
> > - clock-names = "ref_clk", "suspend_clk",
> > - "bus_clk", "grf_clk";
> > - #address-cells = <2>;
> > - #size-cells = <2>;
> > - ranges;
> > - usbdrd_dwc3_0: dwc3@fe800000 {
> > - compatible = "snps,dwc3";
> > - reg = <0x0 0xfe800000 0x0 0x100000>;
> > - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > - dr_mode = "otg";
> > - };
> > - };
> > -
> > - usbdrd3_1: usb@fe900000 {
> > - compatible = "rockchip,rk3399-dwc3";
> > - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
> > - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
> > - clock-names = "ref_clk", "suspend_clk",
> > - "bus_clk", "grf_clk";
> > - #address-cells = <2>;
> > - #size-cells = <2>;
> > - ranges;
> > - usbdrd_dwc3_1: dwc3@fe900000 {
> > - compatible = "snps,dwc3";
> > - reg = <0x0 0xfe900000 0x0 0x100000>;
> > - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> > - dr_mode = "otg";
> > - };
> > - };
> > diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> > new file mode 100644
> > index 000000000..681086fa6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> > @@ -0,0 +1,107 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Rockchip SuperSpeed DWC3 USB SoC controller
> > +
> > +maintainers:
> > + - Heiko Stuebner <heiko@sntech.de>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - rockchip,rk3399-dwc3
> > +
> > + clocks:
> > + items:
> > + - description:
> > + Controller reference clock, must to be 24 MHz
> > + - description:
> > + Controller suspend clock, must to be 24 MHz or 32 KHz
> > + - description:
> > + Master/Core clock, must to be >= 62.5 MHz for SS
> > + operation and >= 30MHz for HS operation
> > + - description:
> > + Controller aclk_usb3_rksoc_axi_perf clock
> > + - description:
> > + Controller aclk_usb3 clock
> > + - description:
> > + Controller grf clock
> > +
> > + clock-names:
> > + items:
> > + - const: ref_clk
> > + - const: suspend_clk
> > + - const: bus_clk
>
> > + - const: aclk_usb3_rksoc_axi_perf
> > + - const: aclk_usb3
>
> This was not in the original document, but is needed to compile.
Okay, fine to add it. That's common.
> > + - const: grf_clk
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + reset-names:
> > + const: usb3-otg
> > +
> > + "#address-cells":
> > + const: 2
> > +
> > + "#size-cells":
> > + const: 2
> > +
> > + ranges: true
> > +
> > +patternProperties:
> > + "^usb@[a-f0-9]+$":
> > + type: object
> > +
> > + $ref: "snps,dwc3.yaml"
> > +
> > + description:
> > + A child node must exist to represent the core DWC3 IP block.
> > + The content of the node is defined in snps,dwc3.yaml.
> > +
> > + Phy documentation is provided in the following places.
> > +
> > + USB2.0 PHY
> > + Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
> > +
> > + Type-C PHY
> > + Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> > +
> > + unevaluatedProperties: false
> > +
> > +additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - clocks
> > + - clock-names
> > + - "#address-cells"
> > + - "#size-cells"
> > + - ranges
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/rk3399-cru.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> > + usbdrd3_0: usb@fe800000 {
>
> The rk3399 has 2 dwc3 usb nodes. When we remove @fe800000 and @fe900000
> in the rk3399.dtsi it complains about 2 identical usb root nodenames.
> For this example to pass change to:
>
> usbdrd3_0: usb ??
>
> What to do with it in the dtsi??
The correct thing is really that there shouldn't have been 2 nodes in
the first place. I think the first DWC3 user had some wrapper
registers where separate nodes kind of make sense. But just for
clocks, not really needed.
> > + compatible = "rockchip,rk3399-dwc3";
> > + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> > + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
> > + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
> > + clock-names = "ref_clk", "suspend_clk",
> > + "bus_clk", "aclk_usb3_rksoc_axi_perf",
> > + "aclk_usb3", "grf_clk";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> > + ranges;
>
> Ranges generates notifications. Could you advise if that is needed in
> this dwc3 usb context and rk3399.dtsi or should it be removed?
A non-empty ranges will solve all your problems:
ranges = <0 0xfe800000 0 0xfe800000 0 0x100000>;
>
> > + usbdrd_dwc3_0: usb@fe800000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x0 0xfe800000 0x0 0x100000>;
> > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > + dr_mode = "otg";
> > + };
> > + };
> >
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
2021-02-01 19:41 [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
` (4 preceding siblings ...)
2021-02-01 20:46 ` [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
@ 2021-02-02 17:44 ` Rob Herring
5 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2021-02-02 17:44 UTC (permalink / raw)
To: Johan Jonker
Cc: heiko, linux-usb, robh+dt, devicetree, balbi, linux-arm-kernel,
linux-kernel, linux-rockchip, gregkh
On Mon, 01 Feb 2021 20:41:01 +0100, Johan Jonker wrote:
> In the past Rockchip dwc3 usb nodes were manually checked.
> With the conversion of snps,dwc3.yaml as common document
> we now can convert rockchip,dwc3.txt to yaml as well.
>
> Added properties for rk3399 are:
> resets
> reset-names
>
> Generic properties that are now also filtered:
> "#address-cells"
> "#size-cells"
> ranges
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 -----------
> .../devicetree/bindings/usb/rockchip,dwc3.yaml | 107 +++++++++++++++++++++
> 2 files changed, 107 insertions(+), 56 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Unknown file referenced: [Errno 2] No such file or directory: '/usr/local/lib/python3.8/dist-packages/dtschema/schemas/usb/snps,dwc3.yaml'
xargs: dt-doc-validate: exited with status 255; aborting
Documentation/devicetree/bindings/usb/rockchip,dwc3.example.dts:31.11-18: Warning (ranges_format): /example-0/usb@fe800000:ranges: empty "ranges" property but its #address-cells (2) differs from /example-0 (1)
Documentation/devicetree/bindings/usb/rockchip,dwc3.example.dts:31.11-18: Warning (ranges_format): /example-0/usb@fe800000:ranges: empty "ranges" property but its #size-cells (2) differs from /example-0 (1)
Documentation/devicetree/bindings/usb/rockchip,dwc3.example.dts:21.33-38.11: Warning (unit_address_vs_reg): /example-0/usb@fe800000: node has a unit name, but no reg or ranges property
make[1]: *** Deleting file 'Documentation/devicetree/bindings/usb/rockchip,dwc3.example.dt.yaml'
Unknown file referenced: [Errno 2] No such file or directory: '/usr/local/lib/python3.8/dist-packages/dtschema/schemas/usb/snps,dwc3.yaml'
make[1]: *** [scripts/Makefile.lib:344: Documentation/devicetree/bindings/usb/rockchip,dwc3.example.dt.yaml] Error 255
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1370: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1434297
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 8+ messages in thread