From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E48AEC433E6 for ; Fri, 19 Feb 2021 09:55:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96BDA64E92 for ; Fri, 19 Feb 2021 09:55:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230228AbhBSJzn (ORCPT ); Fri, 19 Feb 2021 04:55:43 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:49710 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229927AbhBSJzG (ORCPT ); Fri, 19 Feb 2021 04:55:06 -0500 X-UUID: 6f5b02960cb84ea4be1ce4d10cba6458-20210219 X-UUID: 6f5b02960cb84ea4be1ce4d10cba6458-20210219 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1410267829; Fri, 19 Feb 2021 17:54:17 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 19 Feb 2021 17:54:16 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 19 Feb 2021 17:54:15 +0800 From: Yongqiang Niu To: CK Hu , Matthias Brugger CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , , , , , , , Hsin-Yi Wang , Chun-Kuang Hu , Yongqiang Niu Subject: [PATCH v1] drm/mediatek: move page flip handle into cmdq cb Date: Fri, 19 Feb 2021 17:54:12 +0800 Message-ID: <1613728452-24871-2-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1613728452-24871-1-git-send-email-yongqiang.niu@mediatek.com> References: <1613728452-24871-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org move page flip handle into cmdq cb irq callback will before cmdq flush ddp register into hardware, that will cause the display frame page flip event before it realy display out time Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index bdd37ea..bece327 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -72,6 +72,13 @@ struct mtk_crtc_state { unsigned int pending_vrefresh; }; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +struct mtk_cmdq_cb_data { + struct cmdq_pkt *cmdq_handle; + struct mtk_drm_crtc *mtk_crtc; +}; +#endif + static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) { return container_of(c, struct mtk_drm_crtc, base); @@ -96,7 +103,6 @@ static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) { - drm_crtc_handle_vblank(&mtk_crtc->base); if (mtk_crtc->pending_needs_vblank) { mtk_drm_crtc_finish_page_flip(mtk_crtc); mtk_crtc->pending_needs_vblank = false; @@ -241,7 +247,19 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, #if IS_REACHABLE(CONFIG_MTK_CMDQ) static void ddp_cmdq_cb(struct cmdq_cb_data data) { - cmdq_pkt_destroy(data.data); + struct mtk_cmdq_cb_data *cb_data = data.data; + + if (cb_data) { + struct mtk_drm_crtc *mtk_crtc = cb_data->mtk_crtc; + + if (mtk_crtc) + mtk_drm_finish_page_flip(mtk_crtc); + + if (cb_data->cmdq_handle) + cmdq_pkt_destroy(cb_data->cmdq_handle); + + kfree(cb_data); + } } #endif @@ -481,13 +499,20 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) } #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (mtk_crtc->cmdq_client) { + struct mtk_cmdq_cb_data *cb_data; + mbox_flush(mtk_crtc->cmdq_client->chan, 2000); cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); mtk_crtc_ddp_config(crtc, cmdq_handle); cmdq_pkt_finalize(cmdq_handle); - cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); + + cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL); + cb_data->cmdq_handle = cmdq_handle; + cb_data->mtk_crtc = mtk_crtc; + + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cb_data); } #endif mutex_unlock(&mtk_crtc->hw_lock); @@ -674,7 +699,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) #endif mtk_crtc_ddp_config(crtc, NULL); - mtk_drm_finish_page_flip(mtk_crtc); + drm_crtc_handle_vblank(&mtk_crtc->base); } static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, -- 1.8.1.1.dirty