From: Mason Zhang <mason.zhang@mediatek.com>
To: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <hanks.chen@mediatek.com>,
<wsd_upstream@mediatek.com>
Subject: Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
Date: Mon, 1 Mar 2021 10:01:55 +0800 [thread overview]
Message-ID: <1614564115.1578.8.camel@mbjsdccf07> (raw)
In-Reply-To: <20210226105918.3057-1-Mason.Zhang@mediatek.com>
On Fri, 2021-02-26 at 18:59 +0800, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
next prev parent reply other threads:[~2021-03-01 2:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-26 10:59 [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node Mason Zhang
2021-03-01 2:01 ` Mason Zhang [this message]
2021-03-22 11:28 ` Mason Zhang
2021-03-29 15:50 ` Matthias Brugger
2021-04-07 8:49 ` Mason Zhang
2021-04-07 11:17 ` Matthias Brugger
2021-04-09 2:27 ` Mason Zhang
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