From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7D81C43611 for ; Wed, 7 Apr 2021 03:29:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B82C613D5 for ; Wed, 7 Apr 2021 03:29:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348373AbhDGD32 (ORCPT ); Tue, 6 Apr 2021 23:29:28 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:38989 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1348370AbhDGD3N (ORCPT ); Tue, 6 Apr 2021 23:29:13 -0400 X-UUID: 4a6fb3b086a5419c9a48f0741c839147-20210407 X-UUID: 4a6fb3b086a5419c9a48f0741c839147-20210407 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 415551506; Wed, 07 Apr 2021 11:29:00 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Apr 2021 11:28:58 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 7 Apr 2021 11:28:58 +0800 From: Flora Fu To: Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Liam Girdwood , Mark Brown CC: Flora Fu , Pi-Cheng Chen , Chiawen Lee , Chun-Jie Chen , , , , , Subject: [PATCH 8/8] arm64: dts: mt8192: Add APU power domain node Date: Wed, 7 Apr 2021 11:28:06 +0800 Message-ID: <1617766086-5502-9-git-send-email-flora.fu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1617766086-5502-1-git-send-email-flora.fu@mediatek.com> References: <1617766086-5502-1-git-send-email-flora.fu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add APU power domain node to MT8192. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 29 +++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts index 1769f3a9b510..9e89efb3dc8a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts @@ -65,3 +65,10 @@ &mt6359_vrf12_ldo_reg { regulator-always-on; }; + +&apuspm { + vsram-supply = <&mt6359_vsram_md_ldo_reg>; + power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP { + domain-supply = <&mt6359_vproc1_buck_reg>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index b1467ccbe5aa..546c058ef560 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -1033,6 +1034,34 @@ #clock-cells = <1>; }; + apuspm: power-domain@190f0000 { + compatible = "mediatek,mt8192-apu-pm", "syscon"; + reg = <0 0x190f0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,scpsys = <&scpsys>; + mediatek,apu_conn = <&apu_conn>; + mediatek,apu_vcore = <&apu_vcore>; + + power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP { + reg = ; + #power-domain-cells = <0>; + clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>; + clock-names = "clk_top_conn", + "clk_top_ipu_if", + "clk_off", + "clk_on_default"; + assigned-clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>; + }; + }; + larb13: larb@1a001000 { compatible = "mediatek,mt8192-smi-larb"; reg = <0 0x1a001000 0 0x1000>; -- 2.18.0