From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
To: <vkoul@kernel.org>, <robh+dt@kernel.org>, <michal.simek@xilinx.com>
Cc: <dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <git@xilinx.com>,
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Subject: [RFC v2 PATCH 4/7] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
Date: Fri, 9 Apr 2021 23:26:02 +0530 [thread overview]
Message-ID: <1617990965-35337-5-git-send-email-radhey.shyam.pandey@xilinx.com> (raw)
In-Reply-To: <1617990965-35337-1-git-send-email-radhey.shyam.pandey@xilinx.com>
Increase AXI DMA transaction segments count to ensure that even in
high load we always get a free segment in prepare descriptor for a
DMA_SLAVE transaction.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
---
Changes for v2:
- None
---
drivers/dma/xilinx/xilinx_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 14dcfc473e52..890bf46b36e5 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -178,7 +178,7 @@
#define XILINX_DMA_BD_SOP BIT(27)
#define XILINX_DMA_BD_EOP BIT(26)
#define XILINX_DMA_COALESCE_MAX 255
-#define XILINX_DMA_NUM_DESCS 255
+#define XILINX_DMA_NUM_DESCS 512
#define XILINX_DMA_NUM_APP_WORDS 5
/* AXI CDMA Specific Registers/Offsets */
--
2.7.4
next prev parent reply other threads:[~2021-04-09 17:57 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 17:55 [RFC v2 PATCH 0/7] Xilinx DMA enhancements and optimization Radhey Shyam Pandey
2021-04-09 17:55 ` [RFC v2 PATCH 1/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected property Radhey Shyam Pandey
2021-04-12 18:25 ` Rob Herring
2021-04-09 17:56 ` [RFC v2 PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Radhey Shyam Pandey
2021-04-12 18:25 ` Rob Herring
2021-04-09 17:56 ` [RFC v2 PATCH 3/7] dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client Radhey Shyam Pandey
2021-04-09 17:56 ` Radhey Shyam Pandey [this message]
2021-04-09 17:56 ` [RFC v2 PATCH 5/7] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Radhey Shyam Pandey
2021-04-15 7:08 ` Lars-Peter Clausen
2021-06-11 16:16 ` Radhey Shyam Pandey
2021-04-15 7:26 ` Lars-Peter Clausen
2021-06-11 18:58 ` Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 6/7] dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase Radhey Shyam Pandey
2021-04-15 7:10 ` Lars-Peter Clausen
2021-06-11 18:30 ` Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 7/7] dmaengine: xilinx_dma: Program interrupt delay timeout Radhey Shyam Pandey
2021-04-15 7:33 ` Lars-Peter Clausen
2021-06-11 19:33 ` Radhey Shyam Pandey
2021-04-15 7:06 ` [RFC v2 PATCH 0/7] Xilinx DMA enhancements and optimization Lars-Peter Clausen
2021-06-11 16:13 ` Radhey Shyam Pandey
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