Re: [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs

[Kewei Xu <kewei.xu@mediatek.com>]

On Tue, 2021-06-08 at 16:01 +0200, Matthias Brugger wrote:
> 
> On 08/06/2021 05:16, Kewei Xu wrote:
> > From: "Kewei.Xu" <kewei.xu@mediatek.com>
> > 
> > When a timeout error occurs in i2c transter, it is usually related
> > to the i2c/dma IP hardware configuration. Therefore, the purpose of
> > this patch is to dump the key register values of i2c/dma when a
> > timeout occurs in i2c for debugging.
> > 
> > Signed-off-by: Kewei.Xu <kewei.xu@mediatek.com>
> > ---
> >  drivers/i2c/busses/i2c-mt65xx.c | 97 ++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 95 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index 5ddfa4e..e65a41e 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -125,6 +125,7 @@ enum I2C_REGS_OFFSET {
> >  	OFFSET_HS,
> >  	OFFSET_SOFTRESET,
> >  	OFFSET_DCM_EN,
> > +	OFFSET_MULTI_DMA,
> >  	OFFSET_PATH_DIR,
> >  	OFFSET_DEBUGSTAT,
> >  	OFFSET_DEBUGCTRL,
> > @@ -192,8 +193,9 @@ enum I2C_REGS_OFFSET {
> >  	[OFFSET_TRANSFER_LEN_AUX] = 0x44,
> >  	[OFFSET_CLOCK_DIV] = 0x48,
> >  	[OFFSET_SOFTRESET] = 0x50,
> > +	[OFFSET_MULTI_DMA] = 0x84,
> >  	[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
> > -	[OFFSET_DEBUGSTAT] = 0xe0,
> > +	[OFFSET_DEBUGSTAT] = 0xe4,
> 
> Is this offset only for mt8192 or also for mt8183?
> In any case that should go in as another patch. Either a fix or a new
> mt_i2c_regs_v3[]
> 
> Regards,
  Matthias

Hi Matthias,

This offset value is suitable for the IC of mt_i2c_regs_v2 hardware
design similar to mt8192/8195, not for 8183.

The reason for the modification here is that the previous
offset information is incorrect, OFFSET_DEBUGSTAT = 0XE4 is
the correct value.

Regards,
Kewei