Re: [PATCH 2/3] riscv: Implement Zicbom-based cache management operations

Randy Dunlap
2022-06-10T03:22:39Z

On 6/9/22 17:43, Heiko Stuebner wrote:
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 32ffef9f6e5b..384d0c15f2b6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -376,6 +376,21 @@ config RISCV_ISA_SVPBMT
>
> If you don't know what to do here, say Y.
>
> +config RISCV_ISA_ZICBOM
> + bool "Zicbom extension support for non-coherent dma operation"
> + select ARCH_HAS_DMA_PREP_COHERENT
> + select ARCH_HAS_SYNC_DMA_FOR_DEVICE
> + select ARCH_HAS_SYNC_DMA_FOR_CPU
> + select ARCH_HAS_SETUP_DMA_OPS
> + select DMA_DIRECT_REMAP
> + select RISCV_ALTERNATIVE

Since RISCV_ALTERNATIVE depends on !XIP_KERNEL and since 'select' does not
follow any dependency chains, this config also needs to depend on
!XIP_KERNEL.

> + default y
> + help
> + Adds support to dynamically detect the presence of the ZICBOM extension
> + (Cache Block Management Operations) and enable its usage.
> +
> + If you don't know what to do here, say Y.

--
~Randy