* [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 [not found] <1624015734-16778-1-git-send-email-okukatla@codeaurora.org> @ 2021-06-18 11:28 ` Odelu Kukatla 2021-07-08 23:22 ` Stephen Boyd 2021-06-18 11:28 ` [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla 1 sibling, 1 reply; 6+ messages in thread From: Odelu Kukatla @ 2021-06-18 11:28 UTC (permalink / raw) To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Georgi Djakov, Rob Herring, Sibi Sankar, linux-arm-msm, linux-pm, devicetree, linux-kernel Cc: sboyd, seansw, elder, linux-arm-msm-owner, Odelu Kukatla Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 ++++++++- include/dt-bindings/interconnect/qcom,osm-l3.h | 10 +++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index d6a95c3..9f67c8e 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -18,12 +18,19 @@ properties: compatible: enum: - qcom,sc7180-osm-l3 + - qcom,sc7280-epss-l3 - qcom,sdm845-osm-l3 - qcom,sm8150-osm-l3 - qcom,sm8250-epss-l3 reg: - maxItems: 1 + minItems: 1 + maxItems: 4 + items: + - description: OSM clock domain-0 base address and size + - description: OSM clock domain-1 base address and size + - description: OSM clock domain-2 base address and size + - description: OSM clock domain-3 base address and size clocks: items: diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h index 61ef649..99534a5 100644 --- a/include/dt-bindings/interconnect/qcom,osm-l3.h +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved. */ #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H @@ -11,5 +11,13 @@ #define MASTER_EPSS_L3_APPS 0 #define SLAVE_EPSS_L3_SHARED 1 +#define SLAVE_EPSS_L3_CPU0 2 +#define SLAVE_EPSS_L3_CPU1 3 +#define SLAVE_EPSS_L3_CPU2 4 +#define SLAVE_EPSS_L3_CPU3 5 +#define SLAVE_EPSS_L3_CPU4 6 +#define SLAVE_EPSS_L3_CPU5 7 +#define SLAVE_EPSS_L3_CPU6 8 +#define SLAVE_EPSS_L3_CPU7 9 #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 2021-06-18 11:28 ` [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla @ 2021-07-08 23:22 ` Stephen Boyd 2021-08-09 16:31 ` okukatla 0 siblings, 1 reply; 6+ messages in thread From: Stephen Boyd @ 2021-07-08 23:22 UTC (permalink / raw) To: Andy Gross, Georgi Djakov, Odelu Kukatla, Rob Herring, Sibi Sankar, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, linux-pm Cc: seansw, elder, linux-arm-msm-owner Quoting Odelu Kukatla (2021-06-18 04:28:52) > Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 ++++++++- > include/dt-bindings/interconnect/qcom,osm-l3.h | 10 +++++++++- > 2 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > index d6a95c3..9f67c8e 100644 > --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > @@ -18,12 +18,19 @@ properties: > compatible: > enum: > - qcom,sc7180-osm-l3 > + - qcom,sc7280-epss-l3 > - qcom,sdm845-osm-l3 > - qcom,sm8150-osm-l3 > - qcom,sm8250-epss-l3 > > reg: > - maxItems: 1 > + minItems: 1 > + maxItems: 4 Can we base this on the compatible string so that only sc7280-epss-l3 requires 4 items? and then the others require 1 reg property? > + items: > + - description: OSM clock domain-0 base address and size > + - description: OSM clock domain-1 base address and size > + - description: OSM clock domain-2 base address and size > + - description: OSM clock domain-3 base address and size > > clocks: > items: ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 2021-07-08 23:22 ` Stephen Boyd @ 2021-08-09 16:31 ` okukatla 0 siblings, 0 replies; 6+ messages in thread From: okukatla @ 2021-08-09 16:31 UTC (permalink / raw) To: Stephen Boyd Cc: Andy Gross, Georgi Djakov, Rob Herring, Sibi Sankar, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, linux-pm, seansw, elder, linux-arm-msm-owner Thanks Stephen for the reviews! On 2021-07-09 04:52, Stephen Boyd wrote: > Quoting Odelu Kukatla (2021-06-18 04:28:52) >> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 >> SoCs. >> >> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> --- >> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 >> ++++++++- >> include/dt-bindings/interconnect/qcom,osm-l3.h | 10 >> +++++++++- >> 2 files changed, 17 insertions(+), 2 deletions(-) >> >> diff --git >> a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> index d6a95c3..9f67c8e 100644 >> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> @@ -18,12 +18,19 @@ properties: >> compatible: >> enum: >> - qcom,sc7180-osm-l3 >> + - qcom,sc7280-epss-l3 >> - qcom,sdm845-osm-l3 >> - qcom,sm8150-osm-l3 >> - qcom,sm8250-epss-l3 >> >> reg: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 4 > > Can we base this on the compatible string so that only sc7280-epss-l3 > requires 4 items? and then the others require 1 reg property? > Done, Addressing this in new revision. >> + items: >> + - description: OSM clock domain-0 base address and size >> + - description: OSM clock domain-1 base address and size >> + - description: OSM clock domain-2 base address and size >> + - description: OSM clock domain-3 base address and size >> >> clocks: >> items: ^ permalink raw reply [flat|nested] 6+ messages in thread
* [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider [not found] <1624015734-16778-1-git-send-email-okukatla@codeaurora.org> 2021-06-18 11:28 ` [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla @ 2021-06-18 11:28 ` Odelu Kukatla 2021-07-08 23:04 ` Stephen Boyd 1 sibling, 1 reply; 6+ messages in thread From: Odelu Kukatla @ 2021-06-18 11:28 UTC (permalink / raw) To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel Cc: sboyd, seansw, elder, linux-pm, linux-arm-msm-owner, Odelu Kukatla Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 38a7f55..7690d7e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1153,6 +1153,15 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>, + <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + clk_virt: interconnect { compatible = "qcom,sc7280-clk-virt"; #interconnect-cells = <2>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-06-18 11:28 ` [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla @ 2021-07-08 23:04 ` Stephen Boyd 2021-08-09 16:47 ` okukatla 0 siblings, 1 reply; 6+ messages in thread From: Stephen Boyd @ 2021-07-08 23:04 UTC (permalink / raw) To: Andy Gross, Odelu Kukatla, Rob Herring, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel Cc: seansw, elder, linux-pm, linux-arm-msm-owner Quoting Odelu Kukatla (2021-06-18 04:28:54) > Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 38a7f55..7690d7e 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1153,6 +1153,15 @@ > }; > }; > > + epss_l3: interconnect@18590000 { > + compatible = "qcom,sc7280-epss-l3"; > + reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>, > + <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; > + clock-names = "xo", "alternate"; > + #interconnect-cells = <1>; > + }; Is this inside the soc node? Because it should be but then the next node is called 'interconnect' and has no address so that is probably outside the soc node. Please put nodes with a reg property like this into the soc node. > + > clk_virt: interconnect { > compatible = "qcom,sc7280-clk-virt"; > #interconnect-cells = <2>; ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-07-08 23:04 ` Stephen Boyd @ 2021-08-09 16:47 ` okukatla 0 siblings, 0 replies; 6+ messages in thread From: okukatla @ 2021-08-09 16:47 UTC (permalink / raw) To: Stephen Boyd Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, seansw, elder, linux-pm, linux-arm-msm-owner On 2021-07-09 04:34, Stephen Boyd wrote: > Quoting Odelu Kukatla (2021-06-18 04:28:54) >> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >> SoCs. >> >> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 38a7f55..7690d7e 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1153,6 +1153,15 @@ >> }; >> }; >> >> + epss_l3: interconnect@18590000 { >> + compatible = "qcom,sc7280-epss-l3"; >> + reg = <0 0x18590000 0 1000>, <0 0x18591000 0 >> 0x100>, >> + <0 0x18592000 0 0x100>, <0 0x18593000 >> 0 0x100>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc >> GCC_GPLL0>; >> + clock-names = "xo", "alternate"; >> + #interconnect-cells = <1>; >> + }; > > Is this inside the soc node? Because it should be but then the next > node > is called 'interconnect' and has no address so that is probably outside > the soc node. Please put nodes with a reg property like this into the > soc node. > no, will move this into soc node in v5. >> + >> clk_virt: interconnect { >> compatible = "qcom,sc7280-clk-virt"; >> #interconnect-cells = <2>; ^ permalink raw reply [flat|nested] 6+ messages in thread
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2021-06-18 11:28 ` [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-07-08 23:22 ` Stephen Boyd
2021-08-09 16:31 ` okukatla
2021-06-18 11:28 ` [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-07-08 23:04 ` Stephen Boyd
2021-08-09 16:47 ` okukatla
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