[PATCH v2 0/3] Misc Ingenic patches.

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* [PATCH v2 0/3] Misc Ingenic patches.
@ 2021-06-22 15:55 周琰杰 (Zhou Yanjie)
  2021-06-22 15:55 ` [PATCH v2 1/3] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-22 15:55 UTC (permalink / raw)
  To: tsbogend, paul, robh+dt
  Cc: linux-mips, devicetree, linux-kernel, dongsheng.qiu, aric.pzqi,
	rick.tyliu, sihui.liu, jun.jiang, sernia.zhou

Some misc patches that don't really have any relation
between themselves.

周琰杰 (Zhou Yanjie) (3):
  MIPS: X1830: Respect cell count of common properties.
  MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
  MIPS: CI20: Add second percpu timer for SMP.

 arch/mips/boot/dts/ingenic/ci20.dts   | 21 +++++++++++----------
 arch/mips/boot/dts/ingenic/x1000.dtsi |  7 +++++++
 arch/mips/boot/dts/ingenic/x1830.dtsi | 16 +++++++++++-----
 3 files changed, 29 insertions(+), 15 deletions(-)

-- 
2.7.4


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v2 1/3] MIPS: X1830: Respect cell count of common properties.
  2021-06-22 15:55 [PATCH v2 0/3] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
@ 2021-06-22 15:55 ` 周琰杰 (Zhou Yanjie)
  2021-06-22 15:55 ` [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
  2021-06-22 15:55 ` [PATCH v2 3/3] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
  2 siblings, 0 replies; 6+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-22 15:55 UTC (permalink / raw)
  To: tsbogend, paul, robh+dt
  Cc: linux-mips, devicetree, linux-kernel, dongsheng.qiu, aric.pzqi,
	rick.tyliu, sihui.liu, jun.jiang, sernia.zhou

If N fields of X cells should be provided, then that's what the
devicetree should represent, instead of having one single field of
(N * X) cells.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    v1->v2:
    No change.

 arch/mips/boot/dts/ingenic/x1830.dtsi | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index b21c930..59ca3a8 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -97,9 +97,9 @@
 
 		#clock-cells = <1>;
 
-		clocks = <&cgu X1830_CLK_RTCLK
-			  &cgu X1830_CLK_EXCLK
-			  &cgu X1830_CLK_PCLK>;
+		clocks = <&cgu X1830_CLK_RTCLK>,
+			 <&cgu X1830_CLK_EXCLK>,
+			 <&cgu X1830_CLK_PCLK>;
 		clock-names = "rtc", "ext", "pclk";
 
 		interrupt-controller;
@@ -274,8 +274,7 @@
 
 	pdma: dma-controller@13420000 {
 		compatible = "ingenic,x1830-dma";
-		reg = <0x13420000 0x400
-			   0x13421000 0x40>;
+		reg = <0x13420000 0x400>, <0x13421000 0x40>;
 		#dma-cells = <2>;
 
 		interrupt-parent = <&intc>;
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
  2021-06-22 15:55 [PATCH v2 0/3] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
  2021-06-22 15:55 ` [PATCH v2 1/3] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
@ 2021-06-22 15:55 ` 周琰杰 (Zhou Yanjie)
  2021-06-23 18:34   ` Paul Cercueil
  2021-06-22 15:55 ` [PATCH v2 3/3] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
  2 siblings, 1 reply; 6+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-22 15:55 UTC (permalink / raw)
  To: tsbogend, paul, robh+dt
  Cc: linux-mips, devicetree, linux-kernel, dongsheng.qiu, aric.pzqi,
	rick.tyliu, sihui.liu, jun.jiang, sernia.zhou

Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    v1->v2:
    No change.

 arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
 arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++
 2 files changed, 14 insertions(+)

diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index aac9ded..dec7909 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -80,6 +80,11 @@
 
 			status = "disabled";
 		};
+
+		mac_phy_ctrl: mac-phy-ctrl@e8 {
+			compatible = "syscon";
+			reg = <0xe8 0x4>;
+		};
 	};
 
 	ost: timer@12000000 {
@@ -347,6 +352,8 @@
 		clocks = <&cgu X1000_CLK_MAC>;
 		clock-names = "stmmaceth";
 
+		mode-reg = <&mac_phy_ctrl>;
+
 		status = "disabled";
 
 		mdio: mdio {
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index 59ca3a8..215257f 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -73,6 +73,11 @@
 
 			status = "disabled";
 		};
+
+		mac_phy_ctrl: mac-phy-ctrl@e8 {
+			compatible = "syscon";
+			reg = <0xe8 0x4>;
+		};
 	};
 
 	ost: timer@12000000 {
@@ -336,6 +341,8 @@
 		clocks = <&cgu X1830_CLK_MAC>;
 		clock-names = "stmmaceth";
 
+		mode-reg = <&mac_phy_ctrl>;
+
 		status = "disabled";
 
 		mdio: mdio {
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
  2021-06-22 15:55 ` [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2021-06-23 18:34   ` Paul Cercueil
  2021-06-24  4:10     ` 周琰杰
  0 siblings, 1 reply; 6+ messages in thread
From: Paul Cercueil @ 2021-06-23 18:34 UTC (permalink / raw)
  To: 周琰杰
  Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
	dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
	sernia.zhou

Hi Zhou,

Le mar., juin 22 2021 at 23:55:37 +0800, 周琰杰 (Zhou Yanjie) 
<zhouyanjie@wanyeetech.com> a écrit :
> Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic.
> 
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> Acked-by: Paul Cercueil <paul@crapouillou.net>
> ---
> 
> Notes:
>     v1->v2:
>     No change.
> 
>  arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
>  arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi 
> b/arch/mips/boot/dts/ingenic/x1000.dtsi
> index aac9ded..dec7909 100644
> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -80,6 +80,11 @@
> 
>  			status = "disabled";
>  		};
> +
> +		mac_phy_ctrl: mac-phy-ctrl@e8 {
> +			compatible = "syscon";
> +			reg = <0xe8 0x4>;
> +		};

I acked this patch already, but you do need to update the CGU binding 
documentation as well.

-Paul

>  	};
> 
>  	ost: timer@12000000 {
> @@ -347,6 +352,8 @@
>  		clocks = <&cgu X1000_CLK_MAC>;
>  		clock-names = "stmmaceth";
> 
> +		mode-reg = <&mac_phy_ctrl>;
> +
>  		status = "disabled";
> 
>  		mdio: mdio {
> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi 
> b/arch/mips/boot/dts/ingenic/x1830.dtsi
> index 59ca3a8..215257f 100644
> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> @@ -73,6 +73,11 @@
> 
>  			status = "disabled";
>  		};
> +
> +		mac_phy_ctrl: mac-phy-ctrl@e8 {
> +			compatible = "syscon";
> +			reg = <0xe8 0x4>;
> +		};
>  	};
> 
>  	ost: timer@12000000 {
> @@ -336,6 +341,8 @@
>  		clocks = <&cgu X1830_CLK_MAC>;
>  		clock-names = "stmmaceth";
> 
> +		mode-reg = <&mac_phy_ctrl>;
> +
>  		status = "disabled";
> 
>  		mdio: mdio {
> --
> 2.7.4
> 



^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
  2021-06-23 18:34   ` Paul Cercueil
@ 2021-06-24  4:10     ` 周琰杰
  0 siblings, 0 replies; 6+ messages in thread
From: 周琰杰 @ 2021-06-24  4:10 UTC (permalink / raw)
  To: Paul Cercueil
  Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
	dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
	sernia.zhou

Hi Paul,

于 Wed, 23 Jun 2021 19:34:15 +0100
Paul Cercueil <paul@crapouillou.net> 写道:

> Hi Zhou,
> 
> Le mar., juin 22 2021 at 23:55:37 +0800, 周琰杰 (Zhou Yanjie) 
> <zhouyanjie@wanyeetech.com> a écrit :
> > Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic.
> > 
> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> > Acked-by: Paul Cercueil <paul@crapouillou.net>
> > ---
> > 
> > Notes:
> >     v1->v2:
> >     No change.
> > 
> >  arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
> >  arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++
> >  2 files changed, 14 insertions(+)
> > 
> > diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi 
> > b/arch/mips/boot/dts/ingenic/x1000.dtsi
> > index aac9ded..dec7909 100644
> > --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> > +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> > @@ -80,6 +80,11 @@
> > 
> >  			status = "disabled";
> >  		};
> > +
> > +		mac_phy_ctrl: mac-phy-ctrl@e8 {
> > +			compatible = "syscon";
> > +			reg = <0xe8 0x4>;
> > +		};  
> 
> I acked this patch already, but you do need to update the CGU binding 
> documentation as well.

Sure, I will send v3.

> 
> -Paul
> 
> >  	};
> > 
> >  	ost: timer@12000000 {
> > @@ -347,6 +352,8 @@
> >  		clocks = <&cgu X1000_CLK_MAC>;
> >  		clock-names = "stmmaceth";
> > 
> > +		mode-reg = <&mac_phy_ctrl>;
> > +
> >  		status = "disabled";
> > 
> >  		mdio: mdio {
> > diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi 
> > b/arch/mips/boot/dts/ingenic/x1830.dtsi
> > index 59ca3a8..215257f 100644
> > --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> > +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> > @@ -73,6 +73,11 @@
> > 
> >  			status = "disabled";
> >  		};
> > +
> > +		mac_phy_ctrl: mac-phy-ctrl@e8 {
> > +			compatible = "syscon";
> > +			reg = <0xe8 0x4>;
> > +		};
> >  	};
> > 
> >  	ost: timer@12000000 {
> > @@ -336,6 +341,8 @@
> >  		clocks = <&cgu X1830_CLK_MAC>;
> >  		clock-names = "stmmaceth";
> > 
> > +		mode-reg = <&mac_phy_ctrl>;
> > +
> >  		status = "disabled";
> > 
> >  		mdio: mdio {
> > --
> > 2.7.4
> >   
> 


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v2 3/3] MIPS: CI20: Add second percpu timer for SMP.
  2021-06-22 15:55 [PATCH v2 0/3] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
  2021-06-22 15:55 ` [PATCH v2 1/3] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
  2021-06-22 15:55 ` [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2021-06-22 15:55 ` 周琰杰 (Zhou Yanjie)
  2 siblings, 0 replies; 6+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-22 15:55 UTC (permalink / raw)
  To: tsbogend, paul, robh+dt
  Cc: linux-mips, devicetree, linux-kernel, dongsheng.qiu, aric.pzqi,
	rick.tyliu, sihui.liu, jun.jiang, sernia.zhou

1.Add a new TCU channel as the percpu timer of core1, this is to
  prepare for the subsequent SMP support. The newly added channel
  will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
  order in jz4780.dtsi file.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---

Notes:
    v1->v2:
    New patch.

 arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 8877c62..70005cc 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -118,6 +118,17 @@
 	assigned-clock-rates = <48000000>;
 };
 
+&tcu {
+	/*
+	 * 750 kHz for the system timers and 3 MHz for the clocksources,
+	 * use channel #0 and #1 for the per cpu system timers, and use
+	 * channel #2 for the clocksource.
+	 */
+	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+					  <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
+	assigned-clock-rates = <750000>, <750000>, <3000000>, <3000000>;
+};
+
 &mmc0 {
 	status = "okay";
 
@@ -522,13 +533,3 @@
 		bias-disable;
 	};
 };
-
-&tcu {
-	/*
-	 * 750 kHz for the system timer and 3 MHz for the clocksource,
-	 * use channel #0 for the system timer, #1 for the clocksource.
-	 */
-	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
-					  <&tcu TCU_CLK_OST>;
-	assigned-clock-rates = <750000>, <3000000>, <3000000>;
-};
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-06-24  4:11 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-06-22 15:55 [PATCH v2 0/3] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
2021-06-22 15:55 ` [PATCH v2 1/3] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
2021-06-22 15:55 ` [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-06-23 18:34   ` Paul Cercueil
2021-06-24  4:10     ` 周琰杰
2021-06-22 15:55 ` [PATCH v2 3/3] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie)

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