From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org,
plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz,
tiwai@suse.com, srinivas.kandagatla@linaro.org,
rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org,
alsa-devel@alsa-project.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, swboyd@chromium.org,
judyhsiao@chromium.org
Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>,
Venkata Prasad Potturu <potturu@codeaurora.org>
Subject: [PATCH 6/7] ASoC: codecs: lpass-tx-macro: Change bulk voting to individual clock voting
Date: Mon, 20 Sep 2021 13:05:30 +0530 [thread overview]
Message-ID: <1632123331-2425-7-git-send-email-srivasam@codeaurora.org> (raw)
In-Reply-To: <1632123331-2425-1-git-send-email-srivasam@codeaurora.org>
Change bulk clock frequency voting to individual voting.
Fixes: c39667ddcfc5 (ASoC: codecs: lpass-tx-macro: add support for lpass tx macro)
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
---
sound/soc/codecs/lpass-tx-macro.c | 67 +++++++++++++++++++++++++++------------
1 file changed, 47 insertions(+), 20 deletions(-)
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c
index e65b592..78e5e0b 100644
--- a/sound/soc/codecs/lpass-tx-macro.c
+++ b/sound/soc/codecs/lpass-tx-macro.c
@@ -6,6 +6,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
@@ -258,7 +259,11 @@ struct tx_macro {
unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
unsigned long active_decimator[TX_MACRO_MAX_DAIS];
struct regmap *regmap;
- struct clk_bulk_data clks[TX_NUM_CLKS_MAX];
+ struct clk *mclk;
+ struct clk *npl;
+ struct clk *macro;
+ struct clk *dcodec;
+ struct clk *fsgen;
struct clk_hw hw;
bool dec_active[NUM_DECIMATORS];
bool reset_swr;
@@ -1695,7 +1700,9 @@ static int swclk_gate_enable(struct clk_hw *hw)
{
struct tx_macro *tx = to_tx_macro(hw);
struct regmap *regmap = tx->regmap;
-
+ pm_runtime_get_sync(tx->dev);
+ clk_set_rate(tx->npl, 2 * MCLK_FREQ);
+ clk_prepare_enable(tx->npl);
tx_macro_mclk_enable(tx, true);
if (tx->reset_swr)
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
@@ -1722,6 +1729,7 @@ static void swclk_gate_disable(struct clk_hw *hw)
CDC_TX_SWR_CLK_EN_MASK, 0x0);
tx_macro_mclk_enable(tx, false);
+ clk_disable_unprepare(tx->npl);
}
static int swclk_gate_is_enabled(struct clk_hw *hw)
@@ -1759,7 +1767,7 @@ static struct clk *tx_macro_register_mclk_output(struct tx_macro *tx)
struct clk_init_data init;
int ret;
- parent_clk_name = __clk_get_name(tx->clks[2].clk);
+ parent_clk_name = __clk_get_name(tx->mclk);
init.name = clk_name;
init.ops = &swclk_gate_ops;
@@ -1799,17 +1807,25 @@ static int tx_macro_probe(struct platform_device *pdev)
if (!tx)
return -ENOMEM;
- tx->clks[0].id = "macro";
- tx->clks[1].id = "dcodec";
- tx->clks[2].id = "mclk";
- tx->clks[3].id = "npl";
- tx->clks[4].id = "fsgen";
+ tx->mclk = devm_clk_get(dev, "mclk");
+ if (IS_ERR(tx->mclk))
+ return PTR_ERR(tx->mclk);
- ret = devm_clk_bulk_get(dev, TX_NUM_CLKS_MAX, tx->clks);
- if (ret) {
- dev_err(dev, "Error getting RX Clocks (%d)\n", ret);
- return ret;
- }
+ tx->npl = devm_clk_get(dev, "npl");
+ if (IS_ERR(tx->npl))
+ return PTR_ERR(tx->npl);
+
+ tx->macro = devm_clk_get_optional(dev, "macro");
+ if (IS_ERR(tx->macro))
+ return PTR_ERR(tx->macro);
+
+ tx->dcodec = devm_clk_get_optional(dev, "dcodec");
+ if (IS_ERR(tx->dcodec))
+ return PTR_ERR(tx->dcodec);
+
+ tx->fsgen = devm_clk_get(dev, "fsgen");
+ if (IS_ERR(tx->fsgen))
+ return PTR_ERR(tx->fsgen);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -1823,12 +1839,15 @@ static int tx_macro_probe(struct platform_device *pdev)
tx->dev = dev;
/* set MCLK and NPL rates */
- clk_set_rate(tx->clks[2].clk, MCLK_FREQ);
- clk_set_rate(tx->clks[3].clk, 2 * MCLK_FREQ);
+ clk_set_rate(tx->mclk, MCLK_FREQ);
+ clk_set_rate(tx->npl, 2 * MCLK_FREQ);
- ret = clk_bulk_prepare_enable(TX_NUM_CLKS_MAX, tx->clks);
- if (ret)
- return ret;
+ clk_prepare_enable(tx->macro);
+ clk_prepare_enable(tx->dcodec);
+
+ clk_prepare_enable(tx->mclk);
+ clk_prepare_enable(tx->npl);
+ clk_prepare_enable(tx->fsgen);
tx_macro_register_mclk_output(tx);
@@ -1839,7 +1858,11 @@ static int tx_macro_probe(struct platform_device *pdev)
goto err;
return ret;
err:
- clk_bulk_disable_unprepare(TX_NUM_CLKS_MAX, tx->clks);
+ clk_disable_unprepare(tx->mclk);
+ clk_disable_unprepare(tx->npl);
+ clk_disable_unprepare(tx->macro);
+ clk_disable_unprepare(tx->dcodec);
+ clk_disable_unprepare(tx->fsgen);
return ret;
}
@@ -1850,7 +1873,11 @@ static int tx_macro_remove(struct platform_device *pdev)
of_clk_del_provider(pdev->dev.of_node);
- clk_bulk_disable_unprepare(TX_NUM_CLKS_MAX, tx->clks);
+ clk_disable_unprepare(tx->mclk);
+ clk_disable_unprepare(tx->npl);
+ clk_disable_unprepare(tx->macro);
+ clk_disable_unprepare(tx->dcodec);
+ clk_disable_unprepare(tx->fsgen);
return 0;
}
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2021-09-20 7:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 7:35 [PATCH 0/7] Update Lpass digital codec macro drivers Srinivasa Rao Mandadapu
2021-09-20 7:35 ` [PATCH 1/7] ASoC: qcom: Add compatible names in va,wsa,rx,tx codec drivers for sc7280 Srinivasa Rao Mandadapu
2021-09-20 18:17 ` Stephen Boyd
2021-09-21 8:42 ` Srinivasa Rao Mandadapu
2021-09-20 7:35 ` [PATCH 2/7] ASoC: qcom: dt-bindings: Add compatible names for lpass sc7280 digital codecs Srinivasa Rao Mandadapu
2021-09-20 13:24 ` Srinivas Kandagatla
2021-09-21 6:59 ` Srinivasa Rao Mandadapu
2021-09-20 7:35 ` [PATCH 3/7] ASoC: codecs: tx-macro: Change mic control registers to volatile Srinivasa Rao Mandadapu
2021-09-20 13:24 ` Srinivas Kandagatla
2021-09-21 7:30 ` Srinivasa Rao Mandadapu
2021-09-21 8:48 ` Srinivas Kandagatla
2021-09-21 13:02 ` Srinivasa Rao Mandadapu
2021-09-20 7:35 ` [PATCH 4/7] ASoC: codecs: lpass-va-macro: Change bulk voting to individual clock voting Srinivasa Rao Mandadapu
2021-09-20 13:25 ` Srinivas Kandagatla
2021-09-21 8:14 ` Srinivasa Rao Mandadapu
2021-09-21 8:50 ` Srinivas Kandagatla
2021-09-21 12:25 ` Srinivasa Rao Mandadapu
2021-09-20 7:35 ` [PATCH 5/7] ASoC: codecs: lpass-rx-macro: " Srinivasa Rao Mandadapu
2021-09-20 7:35 ` Srinivasa Rao Mandadapu [this message]
2021-09-20 7:35 ` [PATCH 7/7] ASoC: codecs: lpass-va-macro: set mclk clock rate correctly Srinivasa Rao Mandadapu
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