From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE4F8C433F5 for ; Tue, 26 Oct 2021 12:20:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C392C60F70 for ; Tue, 26 Oct 2021 12:20:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235894AbhJZMWj (ORCPT ); Tue, 26 Oct 2021 08:22:39 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:61124 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232386AbhJZMWi (ORCPT ); Tue, 26 Oct 2021 08:22:38 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1635250815; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=tYto2LoVENLzeNtQFzqzVBgMkcTo1jqLc7m9bcYCLBY=; b=dqSVUnnbmXIQPdKX2jO6yd7PSgm2x7bjWQ3FVZ+JZSNDaZfGFKwSJqYvrfi9mMVylKmK3l01 xeOJBHTd7DG2yYGB6dpDOziH9WK/f2lwNFyCK60rCKe/ZFr1ZpSgoy/ZiTVOt99iYylQpcxC K8h1oKSveLlqqJoVUIAITIf2jhI= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 6177f2628e67b5f04eb1a490 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 26 Oct 2021 12:19:46 GMT Sender: srivasam=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id CAA3AC4338F; Tue, 26 Oct 2021 12:19:45 +0000 (UTC) Received: from hu-srivasam-hyd.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: srivasam) by smtp.codeaurora.org (Postfix) with ESMTPSA id 36143C43618; Tue, 26 Oct 2021 12:19:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 36143C43618 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org From: Srinivasa Rao Mandadapu To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz, tiwai@suse.com, srinivas.kandagatla@linaro.org, rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, judyhsiao@chromium.org Cc: Srinivasa Rao Mandadapu , Venkata Prasad Potturu Subject: [PATCH v4 1/3] ASoC: qcom: soundwire: Disable soundwire rxtx cgcr hardware control Date: Tue, 26 Oct 2021 17:49:22 +0530 Message-Id: <1635250764-13994-2-git-send-email-srivasam@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1635250764-13994-1-git-send-email-srivasam@codeaurora.org> References: <1635250764-13994-1-git-send-email-srivasam@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update soundwire master rxtx cgcr register field to make clock gating control as software controllable. It is required for soundwire v1.6.0 and above for RX and TX path to work. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- drivers/soundwire/qcom.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 0ef79d6..2492190 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -109,6 +109,7 @@ #define SWR_MAX_CMD_ID 14 #define MAX_FIFO_RD_RETRY 3 #define SWR_OVERFLOW_RETRY_COUNT 30 +#define SWR_RXTX_CGCR_HW_CTL_MASK ~BIT(1) struct qcom_swrm_port_config { u8 si; @@ -127,6 +128,7 @@ struct qcom_swrm_ctrl { struct device *dev; struct regmap *regmap; void __iomem *mmio; + char __iomem *audio_csr_mmio; struct completion broadcast; struct completion enumeration; struct work_struct slave_work; @@ -610,6 +612,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); + if (ctrl->audio_csr_mmio) { + val = ioread32(ctrl->audio_csr_mmio); + val &= SWR_RXTX_CGCR_HW_CTL_MASK; + iowrite32(val, ctrl->audio_csr_mmio); + } + ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); /* Enable Auto enumeration */ @@ -1201,6 +1209,7 @@ static int qcom_swrm_probe(struct platform_device *pdev) const struct qcom_swrm_data *data; int ret; u32 val; + int swrm_hctl_reg; ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); if (!ctrl) @@ -1251,6 +1260,11 @@ static int qcom_swrm_probe(struct platform_device *pdev) ctrl->bus.port_ops = &qcom_swrm_port_ops; ctrl->bus.compute_params = &qcom_swrm_compute_params; + if (!of_property_read_u32(dev->of_node, "qcom,swrm-hctl-reg", &swrm_hctl_reg)) { + ctrl->audio_csr_mmio = devm_ioremap(&pdev->dev, swrm_hctl_reg, 0x4); + if (!ctrl->audio_csr_mmio) + return -ENODEV; + } ret = qcom_swrm_get_port_config(ctrl); if (ret) goto err_clk; -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.