* [PATCH v2 0/3] Add pin control support for lpass sc7280
@ 2021-10-27 13:41 Srinivasa Rao Mandadapu
2021-10-27 13:41 ` [PATCH v2 1/3] pinctrl: qcom: Update lpass variant independent functions as generic Srinivasa Rao Mandadapu
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-10-27 13:41 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao
Cc: Srinivasa Rao Mandadapu
This patch series is to make lpass varient independent pin control
functions common and to add lpass sc7280 pincontrol support.
It also includes dt-bindings for lpass sc7280 lpi compatible.
Changes Since V1:
-- Make lpi pinctrl variant data structure as constant
-- Add appropriate commit message
-- Change signedoff by sequence.
Srinivasa Rao Mandadapu (3):
pinctrl: qcom: Update lpass variant independent functions as generic
dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl compatible
pinctrl: qcom: Add SC7280 lpass pin configuration
.../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +-
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 56 ++++++++++++++++++----
2 files changed, 51 insertions(+), 9 deletions(-)
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 1/3] pinctrl: qcom: Update lpass variant independent functions as generic 2021-10-27 13:41 [PATCH v2 0/3] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu @ 2021-10-27 13:41 ` Srinivasa Rao Mandadapu 2021-11-03 11:22 ` Srinivas Kandagatla 2021-10-27 13:41 ` [PATCH v2 2/3] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl compatible Srinivasa Rao Mandadapu 2021-10-27 13:41 ` [PATCH v2 3/3] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu 2 siblings, 1 reply; 9+ messages in thread From: Srinivasa Rao Mandadapu @ 2021-10-27 13:41 UTC (permalink / raw) To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai, bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd, judyhsiao Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu Update pin control variable names to make common for all lpass varients. Update bulk clock voting to optional voting as ADSP bypass platform doesn't need macro and decodec clocks, these are maintained as power domains and operated from lpass audio core cc. Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 2f19ab4..0bd0c16 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -107,7 +107,7 @@ struct lpi_pinctrl { }; /* sm8250 variant specific data */ -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { +static const struct pinctrl_pin_desc lpass_lpi_pins[] = { PINCTRL_PIN(0, "gpio0"), PINCTRL_PIN(1, "gpio1"), PINCTRL_PIN(2, "gpio2"), @@ -124,7 +124,7 @@ static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { PINCTRL_PIN(13, "gpio13"), }; -enum sm8250_lpi_functions { +enum lpass_lpi_functions { LPI_MUX_dmic1_clk, LPI_MUX_dmic1_data, LPI_MUX_dmic2_clk, @@ -203,7 +203,7 @@ static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), }; -static const struct lpi_function sm8250_functions[] = { +static const struct lpi_function lpass_functions[] = { LPI_FUNCTION(dmic1_clk), LPI_FUNCTION(dmic1_data), LPI_FUNCTION(dmic2_clk), @@ -228,12 +228,12 @@ static const struct lpi_function sm8250_functions[] = { }; static struct lpi_pinctrl_variant_data sm8250_lpi_data = { - .pins = sm8250_lpi_pins, - .npins = ARRAY_SIZE(sm8250_lpi_pins), + .pins = lpass_lpi_pins, + .npins = ARRAY_SIZE(lpass_lpi_pins), .groups = sm8250_groups, .ngroups = ARRAY_SIZE(sm8250_groups), - .functions = sm8250_functions, - .nfunctions = ARRAY_SIZE(sm8250_functions), + .functions = lpass_functions, + .nfunctions = ARRAY_SIZE(lpass_functions), }; static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, @@ -615,7 +615,7 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), "Slew resource not provided\n"); - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) return dev_err_probe(dev, ret, "Can't get clocks\n"); -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] pinctrl: qcom: Update lpass variant independent functions as generic 2021-10-27 13:41 ` [PATCH v2 1/3] pinctrl: qcom: Update lpass variant independent functions as generic Srinivasa Rao Mandadapu @ 2021-11-03 11:22 ` Srinivas Kandagatla 2021-11-19 6:36 ` Srinivasa Rao Mandadapu 0 siblings, 1 reply; 9+ messages in thread From: Srinivas Kandagatla @ 2021-11-03 11:22 UTC (permalink / raw) To: Srinivasa Rao Mandadapu, agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai, bgoswami, perex, tiwai, rohitkr, linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd, judyhsiao Cc: Venkata Prasad Potturu Hi Srinivasa, Thanks for the patches, I think you forgot to add correct mailing list for this drivers. Please consider using scripts/get_maintainer.pl to help you with this list. On 27/10/2021 14:41, Srinivasa Rao Mandadapu wrote: > Update pin control variable names to make common for all lpass varients. > Update bulk clock voting to optional voting as ADSP bypass platform doesn't > need macro and decodec clocks, these are maintained as power domains and > operated from lpass audio core cc. How are you going to ensure that the powerdomains are switched on when setting up the pinctrl configuration. Should we not take a reference to the power-domain in this driver? --srini > > Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> > Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> > Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> > --- > drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > index 2f19ab4..0bd0c16 100644 > --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > @@ -107,7 +107,7 @@ struct lpi_pinctrl { > }; > > /* sm8250 variant specific data */ > -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { > +static const struct pinctrl_pin_desc lpass_lpi_pins[] = { > PINCTRL_PIN(0, "gpio0"), > PINCTRL_PIN(1, "gpio1"), > PINCTRL_PIN(2, "gpio2"), > @@ -124,7 +124,7 @@ static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { > PINCTRL_PIN(13, "gpio13"), > }; > > -enum sm8250_lpi_functions { > +enum lpass_lpi_functions { > LPI_MUX_dmic1_clk, > LPI_MUX_dmic1_data, > LPI_MUX_dmic2_clk, > @@ -203,7 +203,7 @@ static const struct lpi_pingroup sm8250_groups[] = { > LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), > }; > > -static const struct lpi_function sm8250_functions[] = { > +static const struct lpi_function lpass_functions[] = { > LPI_FUNCTION(dmic1_clk), > LPI_FUNCTION(dmic1_data), > LPI_FUNCTION(dmic2_clk), > @@ -228,12 +228,12 @@ static const struct lpi_function sm8250_functions[] = { > }; > > static struct lpi_pinctrl_variant_data sm8250_lpi_data = { > - .pins = sm8250_lpi_pins, > - .npins = ARRAY_SIZE(sm8250_lpi_pins), > + .pins = lpass_lpi_pins, > + .npins = ARRAY_SIZE(lpass_lpi_pins), > .groups = sm8250_groups, > .ngroups = ARRAY_SIZE(sm8250_groups), > - .functions = sm8250_functions, > - .nfunctions = ARRAY_SIZE(sm8250_functions), > + .functions = lpass_functions, > + .nfunctions = ARRAY_SIZE(lpass_functions), > }; > > static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, > @@ -615,7 +615,7 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) > return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), > "Slew resource not provided\n"); > > - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); > + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); > if (ret) > return dev_err_probe(dev, ret, "Can't get clocks\n"); > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] pinctrl: qcom: Update lpass variant independent functions as generic 2021-11-03 11:22 ` Srinivas Kandagatla @ 2021-11-19 6:36 ` Srinivasa Rao Mandadapu 0 siblings, 0 replies; 9+ messages in thread From: Srinivasa Rao Mandadapu @ 2021-11-19 6:36 UTC (permalink / raw) To: Srinivas Kandagatla, agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai, bgoswami, perex, tiwai, rohitkr, linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd, judyhsiao Cc: Venkata Prasad Potturu On 11/3/2021 4:52 PM, Srinivas Kandagatla wrote: Thanks for your time Srini!!! > Hi Srinivasa, > Thanks for the patches, I think you forgot to add correct mailing list > for this drivers. > > Please consider using scripts/get_maintainer.pl to help you with this > list. > > On 27/10/2021 14:41, Srinivasa Rao Mandadapu wrote: >> Update pin control variable names to make common for all lpass varients. >> Update bulk clock voting to optional voting as ADSP bypass platform >> doesn't >> need macro and decodec clocks, these are maintained as power domains and >> operated from lpass audio core cc. > > How are you going to ensure that the powerdomains are switched on when > setting up the pinctrl configuration. > > Should we not take a reference to the power-domain in this driver? The required power domains are getting enabled in core-boot level. So no need of reference in this driver. And still if power domain need to referenced, we can do it from device tree itself. > > > --srini >> >> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> >> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> >> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> >> --- >> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 16 ++++++++-------- >> 1 file changed, 8 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> index 2f19ab4..0bd0c16 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> @@ -107,7 +107,7 @@ struct lpi_pinctrl { >> }; >> /* sm8250 variant specific data */ >> -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { >> +static const struct pinctrl_pin_desc lpass_lpi_pins[] = { >> PINCTRL_PIN(0, "gpio0"), >> PINCTRL_PIN(1, "gpio1"), >> PINCTRL_PIN(2, "gpio2"), >> @@ -124,7 +124,7 @@ static const struct pinctrl_pin_desc >> sm8250_lpi_pins[] = { >> PINCTRL_PIN(13, "gpio13"), >> }; >> -enum sm8250_lpi_functions { >> +enum lpass_lpi_functions { >> LPI_MUX_dmic1_clk, >> LPI_MUX_dmic1_data, >> LPI_MUX_dmic2_clk, >> @@ -203,7 +203,7 @@ static const struct lpi_pingroup sm8250_groups[] = { >> LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), >> }; >> -static const struct lpi_function sm8250_functions[] = { >> +static const struct lpi_function lpass_functions[] = { >> LPI_FUNCTION(dmic1_clk), >> LPI_FUNCTION(dmic1_data), >> LPI_FUNCTION(dmic2_clk), >> @@ -228,12 +228,12 @@ static const struct lpi_function >> sm8250_functions[] = { >> }; >> static struct lpi_pinctrl_variant_data sm8250_lpi_data = { >> - .pins = sm8250_lpi_pins, >> - .npins = ARRAY_SIZE(sm8250_lpi_pins), >> + .pins = lpass_lpi_pins, >> + .npins = ARRAY_SIZE(lpass_lpi_pins), >> .groups = sm8250_groups, >> .ngroups = ARRAY_SIZE(sm8250_groups), >> - .functions = sm8250_functions, >> - .nfunctions = ARRAY_SIZE(sm8250_functions), >> + .functions = lpass_functions, >> + .nfunctions = ARRAY_SIZE(lpass_functions), >> }; >> static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int >> pin, >> @@ -615,7 +615,7 @@ static int lpi_pinctrl_probe(struct >> platform_device *pdev) >> return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), >> "Slew resource not provided\n"); >> - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); >> + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, >> pctrl->clks); >> if (ret) >> return dev_err_probe(dev, ret, "Can't get clocks\n"); >> -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl compatible 2021-10-27 13:41 [PATCH v2 0/3] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu 2021-10-27 13:41 ` [PATCH v2 1/3] pinctrl: qcom: Update lpass variant independent functions as generic Srinivasa Rao Mandadapu @ 2021-10-27 13:41 ` Srinivasa Rao Mandadapu 2021-11-01 21:37 ` Rob Herring 2021-10-27 13:41 ` [PATCH v2 3/3] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu 2 siblings, 1 reply; 9+ messages in thread From: Srinivasa Rao Mandadapu @ 2021-10-27 13:41 UTC (permalink / raw) To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai, bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd, judyhsiao Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu Add device tree binding compatible name for Qualcomm SC7280 LPASS LPI pinctrl driver. Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> --- Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml index e47ebf9..578b283 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -16,7 +16,9 @@ description: | properties: compatible: - const: qcom,sm8250-lpass-lpi-pinctrl + enum: + - qcom,sc7280-lpass-lpi-pinctrl + - qcom,sm8250-lpass-lpi-pinctrl reg: minItems: 2 -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl compatible 2021-10-27 13:41 ` [PATCH v2 2/3] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl compatible Srinivasa Rao Mandadapu @ 2021-11-01 21:37 ` Rob Herring 0 siblings, 0 replies; 9+ messages in thread From: Rob Herring @ 2021-11-01 21:37 UTC (permalink / raw) To: Srinivasa Rao Mandadapu Cc: srinivas.kandagatla, linux-arm-msm, linux-kernel, judyhsiao, bjorn.andersson, agross, perex, bgoswami, devicetree, swboyd, rohitkr, broonie, lgirdwood, Venkata Prasad Potturu, plai, alsa-devel, tiwai, robh+dt On Wed, 27 Oct 2021 19:11:36 +0530, Srinivasa Rao Mandadapu wrote: > Add device tree binding compatible name for Qualcomm SC7280 LPASS LPI pinctrl driver. > > Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> > Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> > Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> > --- > Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] pinctrl: qcom: Add SC7280 lpass pin configuration 2021-10-27 13:41 [PATCH v2 0/3] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu 2021-10-27 13:41 ` [PATCH v2 1/3] pinctrl: qcom: Update lpass variant independent functions as generic Srinivasa Rao Mandadapu 2021-10-27 13:41 ` [PATCH v2 2/3] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl compatible Srinivasa Rao Mandadapu @ 2021-10-27 13:41 ` Srinivasa Rao Mandadapu 2021-11-03 11:22 ` Srinivas Kandagatla 2 siblings, 1 reply; 9+ messages in thread From: Srinivasa Rao Mandadapu @ 2021-10-27 13:41 UTC (permalink / raw) To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai, bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd, judyhsiao Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu Update pin control support for SC7280 LPASS LPI. Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 0bd0c16..17a05a6 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -122,6 +122,7 @@ static const struct pinctrl_pin_desc lpass_lpi_pins[] = { PINCTRL_PIN(11, "gpio11"), PINCTRL_PIN(12, "gpio12"), PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), }; enum lpass_lpi_functions { @@ -136,6 +137,7 @@ enum lpass_lpi_functions { LPI_MUX_i2s1_ws, LPI_MUX_i2s2_clk, LPI_MUX_i2s2_data, + LPI_MUX_sc7280_i2s2_data, LPI_MUX_i2s2_ws, LPI_MUX_qua_mi2s_data, LPI_MUX_qua_mi2s_sclk, @@ -144,6 +146,7 @@ enum lpass_lpi_functions { LPI_MUX_swr_rx_data, LPI_MUX_swr_tx_clk, LPI_MUX_swr_tx_data, + LPI_MUX_sc7280_swr_tx_data, LPI_MUX_wsa_swr_clk, LPI_MUX_wsa_swr_data, LPI_MUX_gpio, @@ -164,8 +167,11 @@ static const unsigned int gpio10_pins[] = { 10 }; static const unsigned int gpio11_pins[] = { 11 }; static const unsigned int gpio12_pins[] = { 12 }; static const unsigned int gpio13_pins[] = { 13 }; +static const unsigned int gpio14_pins[] = { 14 }; + static const char * const swr_tx_clk_groups[] = { "gpio0" }; static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; +static const char * const sc7280_swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; static const char * const swr_rx_clk_groups[] = { "gpio3" }; static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; static const char * const dmic1_clk_groups[] = { "gpio6" }; @@ -185,6 +191,7 @@ static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; static const char * const wsa_swr_clk_groups[] = { "gpio10" }; static const char * const wsa_swr_data_groups[] = { "gpio11" }; static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; +static const char * const sc7280_i2s2_data_groups[] = { "gpio12", "gpio13" }; static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), @@ -203,6 +210,24 @@ static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), }; +static const struct lpi_pingroup sc7280_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _), + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, sc7280_i2s2_data, _, _), + LPI_PINGROUP(13, NO_SLEW, dmic3_data, sc7280_i2s2_data, _, _), + LPI_PINGROUP(14, 6, sc7280_swr_tx_data, _, _, _), +}; + static const struct lpi_function lpass_functions[] = { LPI_FUNCTION(dmic1_clk), LPI_FUNCTION(dmic1_data), @@ -215,6 +240,7 @@ static const struct lpi_function lpass_functions[] = { LPI_FUNCTION(i2s1_ws), LPI_FUNCTION(i2s2_clk), LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(sc7280_i2s2_data), LPI_FUNCTION(i2s2_ws), LPI_FUNCTION(qua_mi2s_data), LPI_FUNCTION(qua_mi2s_sclk), @@ -223,6 +249,7 @@ static const struct lpi_function lpass_functions[] = { LPI_FUNCTION(swr_rx_data), LPI_FUNCTION(swr_tx_clk), LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(sc7280_swr_tx_data), LPI_FUNCTION(wsa_swr_clk), LPI_FUNCTION(wsa_swr_data), }; @@ -236,6 +263,15 @@ static struct lpi_pinctrl_variant_data sm8250_lpi_data = { .nfunctions = ARRAY_SIZE(lpass_functions), }; +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { + .pins = lpass_lpi_pins, + .npins = ARRAY_SIZE(lpass_lpi_pins), + .groups = sc7280_groups, + .ngroups = ARRAY_SIZE(sc7280_groups), + .functions = lpass_functions, + .nfunctions = ARRAY_SIZE(lpass_functions), +}; + static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { @@ -677,6 +713,10 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { .compatible = "qcom,sm8250-lpass-lpi-pinctrl", .data = &sm8250_lpi_data, }, + { + .compatible = "qcom,sc7280-lpass-lpi-pinctrl", + .data = &sc7280_lpi_data, + }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 3/3] pinctrl: qcom: Add SC7280 lpass pin configuration 2021-10-27 13:41 ` [PATCH v2 3/3] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu @ 2021-11-03 11:22 ` Srinivas Kandagatla 2021-11-08 10:01 ` Srinivasa Rao Mandadapu 0 siblings, 1 reply; 9+ messages in thread From: Srinivas Kandagatla @ 2021-11-03 11:22 UTC (permalink / raw) To: Srinivasa Rao Mandadapu, agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai, bgoswami, perex, tiwai, rohitkr, linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd, judyhsiao Cc: Venkata Prasad Potturu Thanks Srinivasa for the patches. On 27/10/2021 14:41, Srinivasa Rao Mandadapu wrote: > Update pin control support for SC7280 LPASS LPI. > > Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> > Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> > Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> > --- > drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 40 ++++++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > index 0bd0c16..17a05a6 100644 > --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > @@ -122,6 +122,7 @@ static const struct pinctrl_pin_desc lpass_lpi_pins[] = { > PINCTRL_PIN(11, "gpio11"), > PINCTRL_PIN(12, "gpio12"), > PINCTRL_PIN(13, "gpio13"), > + PINCTRL_PIN(14, "gpio14"), I see your point in first patch making these names more generic, but this is not really going to work, as the above line just added new pin for sm8250 even though it really only has 0-13 pins. I think it would be more clear if you could just make a dedicated structures for sc7280. Simillar comments apply for other changes too. Other than that the patch looks good to me. --srini > }; > > enum lpass_lpi_functions { > @@ -136,6 +137,7 @@ enum lpass_lpi_functions { > LPI_MUX_i2s1_ws, > LPI_MUX_i2s2_clk, > LPI_MUX_i2s2_data, > + LPI_MUX_sc7280_i2s2_data, > LPI_MUX_i2s2_ws, > LPI_MUX_qua_mi2s_data, > LPI_MUX_qua_mi2s_sclk, > @@ -144,6 +146,7 @@ enum lpass_lpi_functions { > LPI_MUX_swr_rx_data, > LPI_MUX_swr_tx_clk, > LPI_MUX_swr_tx_data, > + LPI_MUX_sc7280_swr_tx_data, > LPI_MUX_wsa_swr_clk, > LPI_MUX_wsa_swr_data, > LPI_MUX_gpio, > @@ -164,8 +167,11 @@ static const unsigned int gpio10_pins[] = { 10 }; > static const unsigned int gpio11_pins[] = { 11 }; > static const unsigned int gpio12_pins[] = { 12 }; > static const unsigned int gpio13_pins[] = { 13 }; > +static const unsigned int gpio14_pins[] = { 14 }; > + > static const char * const swr_tx_clk_groups[] = { "gpio0" }; > static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; > +static const char * const sc7280_swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; > static const char * const swr_rx_clk_groups[] = { "gpio3" }; > static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; > static const char * const dmic1_clk_groups[] = { "gpio6" }; > @@ -185,6 +191,7 @@ static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; > static const char * const wsa_swr_clk_groups[] = { "gpio10" }; > static const char * const wsa_swr_data_groups[] = { "gpio11" }; > static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; > +static const char * const sc7280_i2s2_data_groups[] = { "gpio12", "gpio13" }; > > static const struct lpi_pingroup sm8250_groups[] = { > LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), > @@ -203,6 +210,24 @@ static const struct lpi_pingroup sm8250_groups[] = { > LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), > }; > > +static const struct lpi_pingroup sc7280_groups[] = { > + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), > + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), > + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), > + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), > + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), > + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _), > + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _), > + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _), > + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _), > + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _), > + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), > + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), > + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, sc7280_i2s2_data, _, _), > + LPI_PINGROUP(13, NO_SLEW, dmic3_data, sc7280_i2s2_data, _, _), > + LPI_PINGROUP(14, 6, sc7280_swr_tx_data, _, _, _), > +}; > + > static const struct lpi_function lpass_functions[] = { > LPI_FUNCTION(dmic1_clk), > LPI_FUNCTION(dmic1_data), > @@ -215,6 +240,7 @@ static const struct lpi_function lpass_functions[] = { > LPI_FUNCTION(i2s1_ws), > LPI_FUNCTION(i2s2_clk), > LPI_FUNCTION(i2s2_data), > + LPI_FUNCTION(sc7280_i2s2_data), > LPI_FUNCTION(i2s2_ws), > LPI_FUNCTION(qua_mi2s_data), > LPI_FUNCTION(qua_mi2s_sclk), > @@ -223,6 +249,7 @@ static const struct lpi_function lpass_functions[] = { > LPI_FUNCTION(swr_rx_data), > LPI_FUNCTION(swr_tx_clk), > LPI_FUNCTION(swr_tx_data), > + LPI_FUNCTION(sc7280_swr_tx_data), > LPI_FUNCTION(wsa_swr_clk), > LPI_FUNCTION(wsa_swr_data), > }; > @@ -236,6 +263,15 @@ static struct lpi_pinctrl_variant_data sm8250_lpi_data = { > .nfunctions = ARRAY_SIZE(lpass_functions), > }; > > +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { > + .pins = lpass_lpi_pins, > + .npins = ARRAY_SIZE(lpass_lpi_pins), > + .groups = sc7280_groups, > + .ngroups = ARRAY_SIZE(sc7280_groups), > + .functions = lpass_functions, > + .nfunctions = ARRAY_SIZE(lpass_functions), > +}; > + > static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, > unsigned int addr) > { > @@ -677,6 +713,10 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { > .compatible = "qcom,sm8250-lpass-lpi-pinctrl", > .data = &sm8250_lpi_data, > }, > + { > + .compatible = "qcom,sc7280-lpass-lpi-pinctrl", > + .data = &sc7280_lpi_data, > + }, > { } > }; > MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 3/3] pinctrl: qcom: Add SC7280 lpass pin configuration 2021-11-03 11:22 ` Srinivas Kandagatla @ 2021-11-08 10:01 ` Srinivasa Rao Mandadapu 0 siblings, 0 replies; 9+ messages in thread From: Srinivasa Rao Mandadapu @ 2021-11-08 10:01 UTC (permalink / raw) To: Srinivas Kandagatla, agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai, bgoswami, perex, tiwai, rohitkr, linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd, judyhsiao Cc: Venkata Prasad Potturu On 11/3/2021 4:52 PM, Srinivas Kandagatla wrote: Thanks Srini for your TIme!!! > Thanks Srinivasa for the patches. > > On 27/10/2021 14:41, Srinivasa Rao Mandadapu wrote: >> Update pin control support for SC7280 LPASS LPI. >> >> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> >> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> >> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> >> --- >> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 40 >> ++++++++++++++++++++++++++++++++ >> 1 file changed, 40 insertions(+) >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> index 0bd0c16..17a05a6 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> @@ -122,6 +122,7 @@ static const struct pinctrl_pin_desc >> lpass_lpi_pins[] = { >> PINCTRL_PIN(11, "gpio11"), >> PINCTRL_PIN(12, "gpio12"), >> PINCTRL_PIN(13, "gpio13"), >> + PINCTRL_PIN(14, "gpio14"), > > I see your point in first patch making these names more generic, but > this is not really going to work, as the above line just added new pin > for sm8250 even though it really only has 0-13 pins. > > I think it would be more clear if you could just make a dedicated > structures for sc7280. Simillar comments apply for other changes too. > > Other than that the patch looks good to me. > > --srini Okay. agree to your point. As lpass_lpi_pins array is just declaration, and it will be used in functions, I thought it won't impact as functions are different for both architectures. With your feedback understood that it may not work existing archs. Will change accordingly and re-post it. > >> }; >> enum lpass_lpi_functions { >> @@ -136,6 +137,7 @@ enum lpass_lpi_functions { >> LPI_MUX_i2s1_ws, >> LPI_MUX_i2s2_clk, >> LPI_MUX_i2s2_data, >> + LPI_MUX_sc7280_i2s2_data, >> LPI_MUX_i2s2_ws, >> LPI_MUX_qua_mi2s_data, >> LPI_MUX_qua_mi2s_sclk, >> @@ -144,6 +146,7 @@ enum lpass_lpi_functions { >> LPI_MUX_swr_rx_data, >> LPI_MUX_swr_tx_clk, >> LPI_MUX_swr_tx_data, >> + LPI_MUX_sc7280_swr_tx_data, >> LPI_MUX_wsa_swr_clk, >> LPI_MUX_wsa_swr_data, >> LPI_MUX_gpio, >> @@ -164,8 +167,11 @@ static const unsigned int gpio10_pins[] = { 10 }; >> static const unsigned int gpio11_pins[] = { 11 }; >> static const unsigned int gpio12_pins[] = { 12 }; >> static const unsigned int gpio13_pins[] = { 13 }; >> +static const unsigned int gpio14_pins[] = { 14 }; >> + >> static const char * const swr_tx_clk_groups[] = { "gpio0" }; >> static const char * const swr_tx_data_groups[] = { "gpio1", >> "gpio2", "gpio5" }; >> +static const char * const sc7280_swr_tx_data_groups[] = { "gpio1", >> "gpio2", "gpio14" }; >> static const char * const swr_rx_clk_groups[] = { "gpio3" }; >> static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; >> static const char * const dmic1_clk_groups[] = { "gpio6" }; >> @@ -185,6 +191,7 @@ static const char * const i2s1_data_groups[] = { >> "gpio8", "gpio9" }; >> static const char * const wsa_swr_clk_groups[] = { "gpio10" }; >> static const char * const wsa_swr_data_groups[] = { "gpio11" }; >> static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; >> +static const char * const sc7280_i2s2_data_groups[] = { "gpio12", >> "gpio13" }; >> static const struct lpi_pingroup sm8250_groups[] = { >> LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), >> @@ -203,6 +210,24 @@ static const struct lpi_pingroup sm8250_groups[] >> = { >> LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), >> }; >> +static const struct lpi_pingroup sc7280_groups[] = { >> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), >> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), >> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), >> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), >> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), >> + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _), >> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _), >> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _), >> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _), >> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _), >> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), >> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), >> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, sc7280_i2s2_data, _, _), >> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, sc7280_i2s2_data, _, _), >> + LPI_PINGROUP(14, 6, sc7280_swr_tx_data, _, _, _), >> +}; >> + >> static const struct lpi_function lpass_functions[] = { >> LPI_FUNCTION(dmic1_clk), >> LPI_FUNCTION(dmic1_data), >> @@ -215,6 +240,7 @@ static const struct lpi_function >> lpass_functions[] = { >> LPI_FUNCTION(i2s1_ws), >> LPI_FUNCTION(i2s2_clk), >> LPI_FUNCTION(i2s2_data), >> + LPI_FUNCTION(sc7280_i2s2_data), >> LPI_FUNCTION(i2s2_ws), >> LPI_FUNCTION(qua_mi2s_data), >> LPI_FUNCTION(qua_mi2s_sclk), >> @@ -223,6 +249,7 @@ static const struct lpi_function >> lpass_functions[] = { >> LPI_FUNCTION(swr_rx_data), >> LPI_FUNCTION(swr_tx_clk), >> LPI_FUNCTION(swr_tx_data), >> + LPI_FUNCTION(sc7280_swr_tx_data), >> LPI_FUNCTION(wsa_swr_clk), >> LPI_FUNCTION(wsa_swr_data), >> }; >> @@ -236,6 +263,15 @@ static struct lpi_pinctrl_variant_data >> sm8250_lpi_data = { >> .nfunctions = ARRAY_SIZE(lpass_functions), >> }; >> +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { >> + .pins = lpass_lpi_pins, >> + .npins = ARRAY_SIZE(lpass_lpi_pins), >> + .groups = sc7280_groups, >> + .ngroups = ARRAY_SIZE(sc7280_groups), >> + .functions = lpass_functions, >> + .nfunctions = ARRAY_SIZE(lpass_functions), >> +}; >> + >> static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, >> unsigned int addr) >> { >> @@ -677,6 +713,10 @@ static const struct of_device_id >> lpi_pinctrl_of_match[] = { >> .compatible = "qcom,sm8250-lpass-lpi-pinctrl", >> .data = &sm8250_lpi_data, >> }, >> + { >> + .compatible = "qcom,sc7280-lpass-lpi-pinctrl", >> + .data = &sc7280_lpi_data, >> + }, >> { } >> }; >> MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); >> -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-11-19 6:36 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-10-27 13:41 [PATCH v2 0/3] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu 2021-10-27 13:41 ` [PATCH v2 1/3] pinctrl: qcom: Update lpass variant independent functions as generic Srinivasa Rao Mandadapu 2021-11-03 11:22 ` Srinivas Kandagatla 2021-11-19 6:36 ` Srinivasa Rao Mandadapu 2021-10-27 13:41 ` [PATCH v2 2/3] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl compatible Srinivasa Rao Mandadapu 2021-11-01 21:37 ` Rob Herring 2021-10-27 13:41 ` [PATCH v2 3/3] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu 2021-11-03 11:22 ` Srinivas Kandagatla 2021-11-08 10:01 ` Srinivasa Rao Mandadapu
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