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Thu, 13 Jan 2022 13:31:11 +0000 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH 3/6] dt-bindings: Add headers for Tegra234 I2C Date: Thu, 13 Jan 2022 19:00:20 +0530 Message-ID: <1642080623-15980-4-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642080623-15980-1-git-send-email-akhilrajeev@nvidia.com> References: <1642080623-15980-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 72283cc4-5b8d-445e-4426-08d9d698f9ae X-MS-TrafficTypeDiagnostic: BN8PR12MB4594:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1186; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: omCGQ5TxdsfxqAW69y4KqTyBrEPl2F62r7DwIm/LdMSJARe7IefipgyBp9rbhN+eZsb5DsAXaW3GKh84SwGMqZiic40eUwvMkactaCIhZO74YToshrC3Rz2g4cgkExF8pWscC4oTkw/BT4oT3dqfNUlncaN2JzhtDAbhQas2NwNaPPnhErV5n8HQY1XQ85jO+c7Gciu90vENm3hddLonoixHbdR6tCx3JJrW2i/ZegUhEjSoqrn1xKgtYM0uts0tlDxy5mrFE4FVKeTe/NwWJ8DMAIaX9jNWp3egGXxJuaNem8ap2sS00WMASu/c9Jb7h69mMZfQoIopGF6rFA9yueK+1vhU6nSciyzj9GQOLjmyS3mv/TJiA5OWoSCM0PIEeVGXmcpL1Jf6VeAHuQZ4cTcDZCVHq/6rolIlkRmQWVOwCgiwRLMSVwp5gS88FimRBeBEot4TV61u4xR76WCOBjFpaWRpMB2tcXgFeAwcmFjqtYhOx9MQXfby/HYiTYu0f+8HoR/XOFbgfRLXv+6VzdRcyqZfsx5u9TdRplvGBi5JBXPZH9MXOb/PXXrHrlWJlBRCjF8/O3aGseLnLi3COknGB1lL3LYwjDD8+PHVLLO/dGF5Dpm5h6s/0l6ij19aTwzIY/gRc/7c2RAjKcjFZCGtLUW0w5DMQdBtRDT5DA5gyV01uj7tX3SFayOXSWJy5L3UStEwb1hW5mPiCZ69wCyLwea7kyaGIfeQ70UiRuPRs3SJrwlWZG42FKrduI+b22RNoLBYjLBDgfhJiXwI/MS0OyzmMVER68IVTFdm5DZDamvPQIOM8lAoU1dUE8zS X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(40470700002)(36840700001)(46966006)(40460700001)(5660300002)(70206006)(2616005)(36756003)(426003)(86362001)(82310400004)(7696005)(36860700001)(6666004)(47076005)(2906002)(921005)(8676002)(107886003)(83380400001)(336012)(316002)(4326008)(70586007)(186003)(26005)(110136005)(508600001)(356005)(81166007)(8936002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2022 13:31:16.0237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72283cc4-5b8d-445e-4426-08d9d698f9ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB4594 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt-bindings header files for I2C controllers for Tegra234 Signed-off-by: Akhil R --- include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ 2 files changed, 27 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8d7e66e..5d05c19 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -30,5 +30,24 @@ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ +#define TEGRA234_CLK_I2C1 48U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA234_CLK_I2C2 49U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA234_CLK_I2C3 50U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA234_CLK_I2C4 51U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA234_CLK_I2C6 52U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA234_CLK_I2C7 53U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA234_CLK_I2C8 54U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA234_CLK_I2C9 55U + +/** @brief PLLP clk output */ +#define TEGRA234_CLK_PLLP_OUT0 102U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 50e13bc..e07e898 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -12,6 +12,14 @@ */ #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U +#define TEGRA234_RESET_I2C1 24U +#define TEGRA234_RESET_I2C2 29U +#define TEGRA234_RESET_I2C3 30U +#define TEGRA234_RESET_I2C4 31U +#define TEGRA234_RESET_I2C6 32U +#define TEGRA234_RESET_I2C7 33U +#define TEGRA234_RESET_I2C8 34U +#define TEGRA234_RESET_I2C9 35U /** @} */ -- 2.7.4