From: Ashish Mhetre <amhetre@nvidia.com>
To: <robh+dt@kernel.org>, <krzysztof.kozlowski@canonical.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<digetx@gmail.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>
Cc: <vdumpa@nvidia.com>, <Snikam@nvidia.com>, <amhetre@nvidia.com>
Subject: [Patch v4 1/4] arm64: tegra: Add memory controller channels
Date: Wed, 2 Mar 2022 14:13:26 +0530 [thread overview]
Message-ID: <1646210609-21943-2-git-send-email-amhetre@nvidia.com> (raw)
In-Reply-To: <1646210609-21943-1-git-send-email-amhetre@nvidia.com>
From tegra186 onwards, memory controller support multiple channels.
During the error interrupts from memory controller, corresponding
channels need to be accessed for logging error info and clearing the
interrupt.
So add address and size of these channels in device tree node of
tegra186, tegra194 and tegra234 memory controller.
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 ++++++-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 21 ++++++++++++++++++---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 21 ++++++++++++++++++---
3 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index e9b40f5..9c14404 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -521,7 +521,12 @@
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
- reg = <0x0 0x02c00000 0x0 0xb0000>;
+ reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
+ <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
+ <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
+ <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
+ <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
+ <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c28bf4d..e19c56c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -604,9 +604,24 @@
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra194-mc";
- reg = <0x02c00000 0x100000>,
- <0x02b80000 0x040000>,
- <0x01700000 0x100000>;
+ reg = <0x02c00000 0x10000>, /* MC-SID */
+ <0x02c10000 0x10000>, /* MC Broadcast*/
+ <0x02c20000 0x10000>, /* MC0 */
+ <0x02c30000 0x10000>, /* MC1 */
+ <0x02c40000 0x10000>, /* MC2 */
+ <0x02c50000 0x10000>, /* MC3 */
+ <0x02b80000 0x10000>, /* MC4 */
+ <0x02b90000 0x10000>, /* MC5 */
+ <0x02ba0000 0x10000>, /* MC6 */
+ <0x02bb0000 0x10000>, /* MC7 */
+ <0x01700000 0x10000>, /* MC8 */
+ <0x01710000 0x10000>, /* MC9 */
+ <0x01720000 0x10000>, /* MC10 */
+ <0x01730000 0x10000>, /* MC11 */
+ <0x01740000 0x10000>, /* MC12 */
+ <0x01750000 0x10000>, /* MC13 */
+ <0x01760000 0x10000>, /* MC14 */
+ <0x01770000 0x10000>; /* MC15 */
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index aaace60..6e33d2b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -507,9 +507,24 @@
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra234-mc";
- reg = <0x02c00000 0x100000>,
- <0x02b80000 0x040000>,
- <0x01700000 0x100000>;
+ reg = <0x02c00000 0x10000>, /* MC-SID */
+ <0x02c10000 0x10000>, /* MC Broadcast*/
+ <0x02c20000 0x10000>, /* MC0 */
+ <0x02c30000 0x10000>, /* MC1 */
+ <0x02c40000 0x10000>, /* MC2 */
+ <0x02c50000 0x10000>, /* MC3 */
+ <0x02b80000 0x10000>, /* MC4 */
+ <0x02b90000 0x10000>, /* MC5 */
+ <0x02ba0000 0x10000>, /* MC6 */
+ <0x02bb0000 0x10000>, /* MC7 */
+ <0x01700000 0x10000>, /* MC8 */
+ <0x01710000 0x10000>, /* MC9 */
+ <0x01720000 0x10000>, /* MC10 */
+ <0x01730000 0x10000>, /* MC11 */
+ <0x01740000 0x10000>, /* MC12 */
+ <0x01750000 0x10000>, /* MC13 */
+ <0x01760000 0x10000>, /* MC14 */
+ <0x01770000 0x10000>; /* MC15 */
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
status = "okay";
--
2.7.4
next prev parent reply other threads:[~2022-03-02 8:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-02 8:43 [Patch v4 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-03-02 8:43 ` Ashish Mhetre [this message]
2022-03-02 19:32 ` [Patch v4 1/4] arm64: tegra: Add memory controller channels Krzysztof Kozlowski
2022-03-02 8:43 ` [Patch v4 2/4] dt-bindings: memory: Update reg maxitems for tegra186 Ashish Mhetre
2022-03-02 17:51 ` Rob Herring
2022-03-02 19:31 ` Krzysztof Kozlowski
2022-03-02 8:43 ` [Patch v4 3/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-03-02 19:35 ` Krzysztof Kozlowski
2022-03-09 8:56 ` Jon Hunter
2022-03-02 8:43 ` [Patch v4 4/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-03-02 19:44 ` Krzysztof Kozlowski
2022-03-07 19:02 ` Ashish Mhetre
2022-03-03 12:31 ` Dan Carpenter
2022-03-03 13:03 ` Krzysztof Kozlowski
2022-03-07 19:47 ` Ashish Mhetre
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