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Thu, 14 Apr 2022 00:36:04 -0700 From: Kartik To: , , , , , , , , Subject: [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes Date: Thu, 14 Apr 2022 13:05:56 +0530 Message-ID: <1649921757-16919-3-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649921757-16919-1-git-send-email-kkartik@nvidia.com> References: <1649921757-16919-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3cbbeb57-269c-410e-13ed-08da1de97076 X-MS-TrafficTypeDiagnostic: MN2PR12MB3616:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: X06IYXbm1v9v8XmGS2bDZq2MX3gGjh8N7B7lTFaY4JsWNjMwROBb5FgY3yNyvu7q35+S0Mmiv7BLFxgOHfHs6plINMP36fZI4rwD7uzYzeLGq/i+AADGyLo0VyO5OH+L8njGUqGaQtWn1vc8iu27EtokHkrcUKA7iqVuBVupDffJJOAWkDhjOW3jxTVk0YyObolg2EXM3gzVjsHPLlF6oqsNTM0V/rbvaYktJJGy7LfgQtAQAh6ZnoHYwKTEEBkdJ9Nou5M0+uzUj3YUtExkPj30rOMSfi2hq02eD2bG1ulnn6kiMKAzmO5WFptw/Cqk5QiEgbgM2BRfyNQUNDVJoqpXX60kcgjdftucKjmwyO9H37mjyvTKUvcnT7TtY7bT9dNmUlTbLl54DCA4Y6xPPtnnZK2QwcfN+VtuXK90i4OXBrqHeM10CSu4Llg21TuxFtP5llWtMCeh30rL18JkVn8L3rjtBe7ULYjrm3F7Cbm2Wtq5UoPJfSc8dKLqGGGZ5MSbMEM8PMHFE7jwg4MPIOcCbtc84C7xdxdfV1kowQhP/ldD/SYwxAFVIRxOwS8TQcDN/iPP7MQCB/0mJZ0fEvRwKLjRpvGpURbSOc1L5mrz+ksP5WDhzQdUE8v5Dh2TgYaSbUp4bJR9dvvD+tuSXBkJ5CBQflnMaJnm5VS+F8sY3ZbMoXWekdNLkjIPVbT0vV2R2KfiIN19GHMu9Ttdgg== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(316002)(508600001)(2616005)(47076005)(110136005)(70586007)(86362001)(7696005)(6666004)(36756003)(336012)(426003)(26005)(8936002)(36860700001)(186003)(8676002)(70206006)(82310400005)(40460700003)(83380400001)(15650500001)(5660300002)(81166007)(2906002)(7049001)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 07:36:07.6624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cbbeb57-269c-410e-13ed-08da1de97076 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3616 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra234 supports sending/receiving 32-bit and 128-bit data over a shared mailbox. Based on the data size to be used, clients need to specify the type of shared mailbox in the device tree. Add a macro for 128-bit shared mailbox. Mailbox clients can use this macro as a flag in device tree to enable 128-bit data support for a shared mailbox. Signed-off-by: Kartik --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 +++++++++ include/dt-bindings/mailbox/tegra186-hsp.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index 9f7a7296b57f..a3e87516d637 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -26,6 +26,15 @@ description: | second cell is used to identify the mailbox that the client is going to use. + For shared mailboxes, the first cell composed of two fields: + - bits 15..8: + A bit mask of flags that further specifies the type of shared + mailbox to be used (based on the data size). If no flag is + specified then, 32-bit shared mailbox is used. + - bits 7..0: + Defines the type of the mailbox to be used. This field should be + TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes. + For doorbells, the second cell specifies the index of the doorbell to use. diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h index 3bdec7a84d35..b9ccae2aa9e2 100644 --- a/include/dt-bindings/mailbox/tegra186-hsp.h +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -15,6 +15,11 @@ #define TEGRA_HSP_MBOX_TYPE_SS 0x2 #define TEGRA_HSP_MBOX_TYPE_AS 0x3 +/* + * These define the types of shared mailbox supported based on data size. + */ +#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8) + /* * These defines represent the bit associated with the given master ID in the * doorbell registers. -- 2.17.1