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Thu, 14 Apr 2022 01:25:44 -0700 From: Kartik To: , , , , , , , , , , , , , , , , Subject: [PATCH 1/6] dt-bindings: timer: Add Tegra186 & Tegra234 Timer Date: Thu, 14 Apr 2022 13:55:33 +0530 Message-ID: <1649924738-17990-2-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> References: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9a5da73c-aa77-4628-2116-08da1df0627a X-MS-TrafficTypeDiagnostic: BYAPR12MB2647:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hyPvy4B4Qvo9ruAhjFiMqCXW+YrWXk+0ikgZbHU4w7/Cao+R0JbiBzywNoshAEFXXD4R8NZ8jiZA7JCLg8WcWbBTArLLxwMDva27OamsivlelK2bdOgZShj3TyT5te5hlcx9Cgikd8eFqJDpNQLtWYmgo4ovYNlkgMu72svIgLgDlnrcOqNJFWSKwpIgbKH2q33WOFwqN1XQK8cdfHaWSpVFbLRHFYSFbE4sGJ3aSWyvoF3L/qRy4gsdH30FUsTmhfczJ68MMkIQVYL40viC+Rxqi5YW0fbhOBOH9FQVuJFM9iFKkM+9adA5BEsHHLUyebZQR7CQkYdzonlaanWqOtTwbT83yDx+TmryTg8WxYwFZYx8OlI1p60huEuyQIkmaVUrmGik9sMr6A7SJIELjMrDO8G5LVD42xMywdtCBum/4LV3DQpmUIDCSEa437WMG+HSwDn7NHiRVxE92TEzYfBfWamGDSw078oekwSg8EwMxjZE50Ip9ljiefRlr45QwUnBL+TNc1Dl+/06V98HZghf3/DI+kE+zkGVceWAF45ZoYySFTkJFB4etpli3+m+rynDnkTSEOaxH4eVZMvBGvqeLucY9epwXYR9A124sJNykIqTpQh3+ZTihkgNY5FlcIo876z4617O5UVA54vCtuJxAxWIrpOm10Ms1eBSI6bs/+fd+12jk7BBN/vppsovTAoqlZwTfGKryxC+GJVZrmk/PfIduf88HBzA/+75L81S+5VGzWV9uGJBfyUe/iMrSjGrdxVu85pYNa4X4Fqfci+3r6gy65BgOD1bnCyINO+xjzBXNgpgDOwseNPylIuDV23yBkt+Wc490/+5xwlA5vAohhPdmGsynjixUtMNdvE= X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(83380400001)(336012)(26005)(47076005)(86362001)(5660300002)(356005)(82310400005)(8936002)(36756003)(6666004)(7696005)(36860700001)(2616005)(186003)(2906002)(40460700003)(70586007)(7049001)(921005)(316002)(426003)(110136005)(8676002)(70206006)(508600001)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 08:25:50.6155 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a5da73c-aa77-4628-2116-08da1df0627a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2647 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Tegra186 timer provides ten 29-bit timer counters and one 32-bit timestamp counter. The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit timestamp counter. Each NV timer selects its timing reference signal from the 1 MHz reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be programmed to generate one-shot, periodic, or watchdog interrupts. Signed-off-by: Kartik --- .../bindings/timer/nvidia,tegra186-timer.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml new file mode 100644 index 000000000000..7841a68d19f3 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra186 timer + +maintainers: + - Thierry Reding + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-timer + then: + properties: + interrupts: + # Either a single combined interrupt or up to 14 individual interrupts + minItems: 1 + maxItems: 10 + description: > + A list of 10 interrupts; one per each timer channels 0 through 9. + + - if: + properties: + compatible: + contains: + const: nvidia,tegra234-timer + then: + properties: + interrupts: + # Either a single combined interrupt or up to 16 individual interrupts + minItems: 1 + maxItems: 16 + description: > + A list of 16 interrupts; one per each timer channels 0 through 15. + +properties: + compatible: + oneOf: + - const: nvidia,tegra186-timer + description: > + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit + timestamp counter. Each NV timer selects its timing reference signal + from the 1 MHz reference generated by USEC, TSC or either clk_m or + OSC. Each TMR can be programmed to generate one-shot, periodic, or + watchdog interrupts. + - const: nvidia,tegra234-timer + description: > + The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit + timestamp counter. Each NV timer selects its timing reference signal + from the 1 MHz reference generated by USEC, TSC or either clk_m or + OSC. Each TMR can be programmed to generate one-shot, periodic, or + watchdog interrupts. + + reg: + maxItems: 1 + + interrupts: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + - | + #include + #include + + timer@2080000 { + compatible = "nvidia,tegra234-timer"; + reg = <0x02080000 0x00121000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; -- 2.17.1