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Mon, 18 Apr 2022 04:01:28 -0700 From: Kartik To: CC: , , , , , , , Subject: Re: [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes Date: Mon, 18 Apr 2022 16:31:12 +0530 Message-ID: <1650279672-11757-1-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 510521a6-49d0-40ea-6760-08da212acc2d X-MS-TrafficTypeDiagnostic: DM5PR12MB1931:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NlbwC2FCb3t63gY1LArqkIaKUKYAQx4IJhQuR1kL8SwrmfAg294BvAp2A7MjX4G7B1arvrhSTiPoGoLhbv7zoDjBgw/hLWPo0D+HvlGCnJBJu6+Uf9pw5TLtHzPc43ktbxoi2F427FaF8DKHFor98i61x0fkE37MfmFvUykB4RzE7UUjDlPUZAdcQlLhTqWnWjk2B0nVkTNz9+gOOoSy/vFLNq3+T7M4/TOIuwNcd4yxGJrZ2RQinJCujW4xTQB3hP8porgiIVrRgnrkLxSyVU6RL3iWgUdILRwh/yFe4jpDd1tWG6Doi8uNyZbza9Mq36ADjVDnxMijKMmK3dzFPyASszohhJhyBw5P8OoHQPMTNqjuUyD8Ne921sJ82oiIV0UYWNQtfWfxH1yE9xrWC3wbB2QO+WcHpM4BkA2yIPwdxkyvAO+Du3z7/FLopLz378+vKuCGvWx7HkhVSHYYsWISShUg6DPItQLyi6BSmmHkHKGCTYW771vVqzvwYdQ+NZavCMwbg+LA5WcLSykw1vz96gT+z5EzyzfuZ3kYOlVvbImnm7mC0T7iegULduPzJQnJJ3bzJUxlwMcmCZYYKM72vPl3bkSeG+PKpTBvx0ElCVBA4og/FFvDVoNL5M0SXInjAWYjHD7uiRd2Ok6sKoeqUEbyvVT+sEuVCtJc6lS11G9AffLdnnxODNKjsr4DP5QscLaEzLAFM2QF7SZvvg== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(53546011)(426003)(336012)(186003)(5660300002)(70586007)(508600001)(70206006)(47076005)(36756003)(54906003)(4326008)(15650500001)(8936002)(7696005)(6666004)(6916009)(8676002)(36860700001)(26005)(2906002)(83380400001)(316002)(86362001)(356005)(82310400005)(81166007)(40460700003)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2022 11:01:32.2498 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 510521a6-49d0-40ea-6760-08da212acc2d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1931 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 14/04/2022 13:53, Rob Herring wrote: >> Tegra234 supports sending/receiving 32-bit and 128-bit data over >> a shared mailbox. Based on the data size to be used, clients need >> to specify the type of shared mailbox in the device tree. >> >> Add a macro for 128-bit shared mailbox. Mailbox clients can use this >> macro as a flag in device tree to enable 128-bit data support for a >> shared mailbox. >> >> Signed-off-by: Kartik > >Need a full name here. This is my legal name as per the government ID's. > >> --- >> .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 +++++++++ >> include/dt-bindings/mailbox/tegra186-hsp.h | 5 +++++ >> 2 files changed, 14 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml >> index 9f7a7296b57f..a3e87516d637 100644 >> --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml >> +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml >> @@ -26,6 +26,15 @@ description: | >> second cell is used to identify the mailbox that the client is going >> to use. >> >> + For shared mailboxes, the first cell composed of two fields: >> + - bits 15..8: >> + A bit mask of flags that further specifies the type of shared >> + mailbox to be used (based on the data size). If no flag is >> + specified then, 32-bit shared mailbox is used. >> + - bits 7..0: >> + Defines the type of the mailbox to be used. This field should be >> + TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes. >> + >> For doorbells, the second cell specifies the index of the doorbell to >> use. >> >> diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h >> index 3bdec7a84d35..b9ccae2aa9e2 100644 >> --- a/include/dt-bindings/mailbox/tegra186-hsp.h >> +++ b/include/dt-bindings/mailbox/tegra186-hsp.h >> @@ -15,6 +15,11 @@ >> #define TEGRA_HSP_MBOX_TYPE_SS 0x2 >> #define TEGRA_HSP_MBOX_TYPE_AS 0x3 >> >> +/* >> + * These define the types of shared mailbox supported based on data size. >> + */ >> +#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8) >> + >> /* >> * These defines represent the bit associated with the given master ID in the >> * doorbell registers. >> -- >> 2.17.1 >> >>