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Wed, 20 Apr 2022 06:14:58 -0700 From: Kartik To: CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH 1/6] dt-bindings: timer: Add Tegra186 & Tegra234 Timer Date: Wed, 20 Apr 2022 18:44:57 +0530 Message-ID: <1650460497-26715-1-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 97cdfc88-0bf4-4e4f-be7a-08da22cfcb58 X-MS-TrafficTypeDiagnostic: SN6PR12MB4749:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LiuTF4KInAaLIzYomJCXAQS4ImHL/+TRxiKaRMbuixFYHK5buq+I0mLzhU9/qWqhrLYRb3y10bGgeDV/aDfDDYhq9NKK1oyyr+O6UVFiK0FxCoupYe6KpwFpaOAu1WDAG95RObhoCUpPu7nFQdF5KwpvCRt1QciPoMIXHnuyciiSCzCXTrgkb6AmNAjarsorcTSajL6RhzHoUaJ39jV7qMVB3GYh1iGwUGfj69g1G4UeIb394elJpEnznNuigapHFDhOoX5ieCqwxhaNFExxgb/C/8XK+THiTt7fY8C1hL4xUT3dCtcLDzlchLsaBvx1H4PO2WQeXj7P231yI8ZfIn+22kmvuGNllL8gd9sY0VdoUHKKiJjPV9V6+SwYCEdKEclsPow65E+FQPWdEyTXLwSiaEqY1g8D/829nvLN/qyqqu18uGpprCiZHPkqYOGuwajuO8ny4LoM88x28e9v5gUkfbTcbPo8UONWOlUVd7rPSxoeTl2VUSMxI6ErYvzSWouFxIyZlzsAOtWLt+C6eWMLhr+Bmy1nw4DhLmh6OvRY+Golsq8vQZhP53OgGSmaOplPeFhDWpetd4GlFNcWOrMDQwDIiXzKsPcL6qP8o4QGeDtRiq8RWpF0Vd8tZ+rXIrv8af0qGNB8HHblmr0Pew9BL0gquUsbPv8zyUaVx53TUVmMqE3IvWzTNYPqR1Dyl5TxIH8/kM23HgpzT4/QI5xqsEy1f6ZTPUziBzFcWO1SDVOXs1DKwDsb3jpXrGtwlCkQWw9IVlt7reYxTeZIkdUS9BJkSLnuOonUjhZSM7zHd14E6BsJO8RYEL7hM0XabT0hLhpmGHc56wLd6i/c5A== X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(36860700001)(8676002)(70586007)(86362001)(70206006)(83380400001)(40460700003)(8936002)(5660300002)(82310400005)(7696005)(186003)(4326008)(107886003)(426003)(81166007)(356005)(2906002)(2616005)(47076005)(508600001)(26005)(36756003)(6916009)(53546011)(336012)(54906003)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2022 13:15:09.0105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97cdfc88-0bf4-4e4f-be7a-08da22cfcb58 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB4749 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 14/04/2022 18:20, Rob Herring wrote: >> timestamp counter. The Tegra234 timer provides sixteen 29-bit timer >> counters and one 32-bit timestamp counter. Each NV timer selects its >> timing reference signal from the 1 MHz reference generated by USEC, >> TSC or either clk_m or OSC. Each TMR can be programmed to generate >> one-shot, periodic, or watchdog interrupts. >> >> Signed-off-by: Kartik > >Full name please. This is my legal name. > >> --- >> .../bindings/timer/nvidia,tegra186-timer.yaml | 116 ++++++++++++++++++ >> 1 file changed, 116 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml >> new file mode 100644 >> index 000000000000..7841a68d19f3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml >> @@ -0,0 +1,116 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: NVIDIA Tegra186 timer >> + >> +maintainers: >> + - Thierry Reding >> + >> +allOf: >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: nvidia,tegra186-timer >> + then: >> + properties: >> + interrupts: >> + # Either a single combined interrupt or up to 14 individual interrupts > >This can be part of 'description' I will include this in the description in v2. > >> + minItems: 1 >> + maxItems: 10 >> + description: > >> + A list of 10 interrupts; one per each timer channels 0 through 9. > >Is it 10 or 14? I'm confused. My bad, it is 10. > >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: nvidia,tegra234-timer >> + then: >> + properties: >> + interrupts: >> + # Either a single combined interrupt or up to 16 individual interrupts >> + minItems: 1 >> + maxItems: 16 >> + description: > >> + A list of 16 interrupts; one per each timer channels 0 through 15. >> + >> +properties: >> + compatible: >> + oneOf: >> + - const: nvidia,tegra186-timer >> + description: > >> + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit >> + timestamp counter. Each NV timer selects its timing reference signal >> + from the 1 MHz reference generated by USEC, TSC or either clk_m or >> + OSC. Each TMR can be programmed to generate one-shot, periodic, or >> + watchdog interrupts. >> + - const: nvidia,tegra234-timer >> + description: > >> + The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit >> + timestamp counter. Each NV timer selects its timing reference signal >> + from the 1 MHz reference generated by USEC, TSC or either clk_m or >> + OSC. Each TMR can be programmed to generate one-shot, periodic, or >> + watchdog interrupts. > >Move all this description to top-level description leaving out the exact >number of counters (as the schema defines that). > Do you mean it to be this way? title: NVIDIA Tegra186 timer maintainers: - Thierry Reding description: > The Tegra timer provides 29-bit timer counters and a 32-bit timestamp counter. Each NV timer selects its timing reference signal from the 1 MHz reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be programmed to generate one-shot, periodic, or watchdog interrupts. properties: compatible: oneOf: - const: nvidia,tegra186-timer description: > The Tegra186 timer provides ten 29-bit timer counters. - const: nvidia,tegra234-timer description: > The Tegra234 timer provides sixteen 29-bit timer counters. >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: true >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + >> + timer@3010000 { >> + compatible = "nvidia,tegra186-timer"; >> + reg = <0x03010000 0x000e0000>; >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + status = "disabled"; > >Drop status. > I will remove this in v2. >> + }; >> + >> + - | >> + #include >> + #include >> + >> + timer@2080000 { >> + compatible = "nvidia,tegra234-timer"; >> + reg = <0x02080000 0x00121000>; >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + status = "disabled"; >> + }; >> -- >> 2.17.1 >> >>