From: Vinod Polimera <quic_vpolimer@quicinc.com>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org, devicetree@vger.kernel.org
Cc: Vinod Polimera <quic_vpolimer@quicinc.com>,
linux-kernel@vger.kernel.org, robdclark@gmail.com,
dianders@chromium.org, swboyd@chromium.org,
quic_kalyant@quicinc.com, dmitry.baryshkov@linaro.org,
quic_khsieh@quicinc.com, quic_vproddut@quicinc.com,
quic_bjorande@quicinc.com, quic_aravindh@quicinc.com,
quic_abhinavk@quicinc.com, quic_sbillaka@quicinc.com
Subject: [PATCH v8 14/15] drm/msm/disp/dpu: reset the datapath after timing engine disable
Date: Wed, 12 Oct 2022 17:32:38 +0530 [thread overview]
Message-ID: <1665576159-3749-15-git-send-email-quic_vpolimer@quicinc.com> (raw)
In-Reply-To: <1665576159-3749-1-git-send-email-quic_vpolimer@quicinc.com>
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 5a0dc54..aeeb759 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -590,6 +590,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
}
}
+ dpu_encoder_helper_phys_cleanup(phys_enc);
phys_enc->enable_state = DPU_ENC_DISABLED;
}
--
2.7.4
next prev parent reply other threads:[~2022-10-12 12:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-12 12:02 [PATCH v8 00/15] Add PSR support for eDP Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 01/15] drm/msm/disp/dpu: clear dpu_assign_crtc and get crtc from connector state instead of dpu_enc Vinod Polimera
2022-10-24 15:22 ` Dmitry Baryshkov
2022-10-27 13:34 ` Vinod Polimera
2022-10-27 17:40 ` Dmitry Baryshkov
2022-11-01 11:16 ` Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 02/15] drm: add helper functions to retrieve old and new crtc Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 03/15] drm/msm/dp: use atomic callbacks for DP bridge ops Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 04/15] drm/msm/dp: Add basic PSR support for eDP Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 05/15] drm/msm/dp: use the eDP bridge ops to validate eDP modes Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 06/15] drm/msm/dp: disable self_refresh_aware after entering psr Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 07/15] drm/bridge: use atomic enable/disable callbacks for panel bridge Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 08/15] drm/bridge: add psr support for panel bridge callbacks Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 09/15] drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder functions Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 10/15] drm/msm/disp/dpu: check for crtc enable rather than crtc active to release shared resources Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 11/15] drm/msm/disp/dpu: add PSR support for eDP interface in dpu driver Vinod Polimera
2022-10-12 12:02 ` [PATCH v8 12/15] drm/msm/disp/dpu: get timing engine status from intf status register Vinod Polimera
2022-11-01 12:15 ` Marijn Suijten
2022-10-12 12:02 ` [PATCH v8 13/15] drm/msm/disp/dpu: wait for extra vsync till timing engine status is disabled Vinod Polimera
2022-10-12 12:02 ` Vinod Polimera [this message]
2022-10-12 12:02 ` [PATCH v8 15/15] drm/msm/disp/dpu: clear active interface in the datapath cleanup Vinod Polimera
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