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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id z6sm6384348ejd.35.2022.02.09.13.36.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Feb 2022 13:36:41 -0800 (PST) Message-ID: <167d6936-66a2-2953-702d-b269bc26fc7d@canonical.com> Date: Wed, 9 Feb 2022 22:36:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 4/5] arm64: dts: ti: Introduce base support for AM62x SoC Content-Language: en-US To: Vignesh Raghavendra , Nishanth Menon , Tero Kristo , Rob Herring , Santosh Shilimkar Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220208131827.1430086-1-vigneshr@ti.com> <20220208131827.1430086-5-vigneshr@ti.com> <3221dd42-7a14-7ac6-0b61-634a77a45753@canonical.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 09/02/2022 20:04, Vignesh Raghavendra wrote: > Hi Krzysztof, > > On 08/02/22 10:35 pm, Krzysztof Kozlowski wrote: > [...] >> >> (...) >> >>> diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi >>> new file mode 100644 >>> index 000000000000..f1a46be27c37 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi >>> @@ -0,0 +1,104 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Device Tree Source for AM62 SoC Family >>> + * >>> + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +/ { >>> + model = "Texas Instruments K3 AM625 SoC"; >>> + compatible = "ti,am625"; >> >> This is am625, but the file is am62. Why having the split? > > > Hierarchy is: > > am62.dtsi: > -> base SoC skeleton ie arch timers and interconnects which is common > across am62xx family of SoCs > -> includes am62-main.dtsi, am62-mcu.dtsi and am62-wakeup.dtsi > representing 3 domains and peripherals in each of these domain > -> describes all peripherals in the family (except CPU cluster) > > > am625.dtsi: > -> describes CPU cluster (Quad A53s). Since, am625 is a current superset > device with all peripherals, am625.dtsi includes am62.dtsi completing > SoC definition. > -> individual EVMs using this SoC will just need to include am625.dtsi > thus making things easier for Board and SOM Vendors. > > > In future: > am62{1-9}{1-9}.dtsi: > -> Includes am625.dtsi > -> Overrides top compatible: ti,am62{1-9}{1-9} > -> disables CPUs and peripherals not present (cutdowns of current SoC). > -> -> individual EVM dts files using this SoC will just need to include > am625.dtsi as starting point, thus making things easier for Board and > SOM Vendors. > > Top level compatible is set to "ti,am625.dtsi" which is first device in > family and superset. > > Hope this clears up? Will add this to commit msg > Hm, if I understand correctly: you might have later some future am6211.dtsi which includes am625.dtsi and in general is compatible with am625 but with disabled parts? It's as bit counter-intuitive - I expect compatible to be extended instead of overridden. But it looks also ok, if you build entire design around it. Best regards, Krzysztof