From: Arnd Bergmann <arnd@arndb.de>
To: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Gabriel FERNANDEZ <gabriel.fernandez@st.com>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Srinivas Kandagatla <srinivas.kandagatla@gmail.com>,
Maxime Coquelin <maxime.coquelin@st.com>,
Patrice Chotard <patrice.chotard@st.com>,
Russell King <linux@arm.linux.org.uk>,
Bjorn Helgaas <bhelgaas@google.com>,
Mohit Kumar <mohit.kumar@st.com>,
Jingoo Han <jg1.han@samsung.com>,
Grant Likely <grant.likely@linaro.org>,
Fabrice Gasnier <fabrice.gasnier@st.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
Thierry Reding <treding@nvidia.com>,
Minghuan Lian <Minghuan.Lian@freescale.com>,
Magnus Damm <damm@opensource.se>,
Will Deacon <will.deacon@arm.com>,
Tanmay
Subject: Re: [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller
Date: Mon, 19 Jan 2015 14:49:42 +0100 [thread overview]
Message-ID: <1682713.ac5OoTJoOr@wuerfel> (raw)
In-Reply-To: <CAG374jDmUyEX0_iu4wG8LjM6YGMjsB-3PjnyZy_0Se=nLcn16g@mail.gmail.com>
On Monday 19 January 2015 13:37:33 Gabriel Fernandez wrote:
> On 17 December 2014 at 23:14, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Wednesday 17 December 2014 11:34:44 Gabriel FERNANDEZ wrote:
> > > +/*
> > > + * On ARM platforms, we actually get a bus error returned when the PCIe
> > IP
> > > + * returns a UR or CRS instead of an OK.
> > > + */
> > > +static int st_pcie_abort_
> >
> > handler(unsigned long addr, unsigned int fsr,
> > > + struct pt_regs *regs)
> > > +{
> > > + return 0;
> > > +}
> >
> > You should check that it's actually PCI that caused the abort. Don't
> > just ignore a hard error condition.
> >
> > Usually there are registers in the PCI core that let you identify what
> > happened.
> >
>
>
> We return 0 because abort handler is not activated during boot.
>
Can you just remove the handler then? We should never have exception
handlers that unconditionally return 0.
> > > + * we must retry for up to a second before we decide the device is
> > > + * dead. If we are still dead then we assume there is nothing
> > there and
> > > + * return ~0
> > > + *
> > > + * The downside of this is that we incur a delay of 1s for every
> > pci
> > > + * express link that doesn't have a device connected.
> > > + */
> > > + if (((where & ~3) == 0) && devfn == 0 && (data == 0 || data ==
> > ~0)) {
> > > + if (retry_count++ < 1000) {
> > > + mdelay(1);
> > > + goto retry;
> > > + } else {
> > > + *val = ~0;
> > > + return PCIBIOS_DEVICE_NOT_FOUND;
> > > + }
> > > + }
> > > +
> > > + *val = data;
> > > + return ret;
> > > +}
> >
> > A busy-loop is extremely nasty. If this is only during the initial bus
> > scan, could you use an msleep instead?
> >
> > yes it's during the initial bus scan.
> But we can't use msleep because we are under raw_spin_lock_irqsave()
> see PCI_OP_READ() macro in drivers/pci/access.c
Ah, I see. Better use a loop with 'time_before()' and a much shorter
delay then. Even a single mdelay(1) with irqs disabled can be annoying,
so try to make the time as short as possible.
> > Also, it sounds like the error you get is actually the fault that you
> > are catching above. If this is correct, then use the fault handler to
> > communicate this to the probe function.
> >
>
> Same as above the handler is not activated during the boot and initial bus
> scan.
Maybe you could enable the handler during boot to catch this case, and
then disable it later?
> >
> > > +static void st_msi_init_one(struct pcie_port *pp)
> > > +{
> > > + struct st_pcie *pcie = to_st_pcie(pp);
> > > +
> > > + /*
> > > + * Set the magic address the hardware responds to. This has to be
> > in
> > > + * the range the PCI controller can write to.
> > > + */
> > > + dw_pcie_msi_init(pp);
> > > +
> > > + if ((virt_to_phys((void *)pp->msi_data) < pcie->lmi->start) ||
> > > + (virt_to_phys((void *)pp->msi_data) > pcie->lmi->end))
> > > + dev_err(pp->dev, "MSI addr miss-configured\n");
> > > +}
> >
> > Why do you call virt_to_phys() here? Isn't
> >
> > msi_data a physical address?
> >
> ?
>
>
> msi_data is a virtual address, it's obtained through a __get_free_pages()
> function in dw_pcie_msi_init() procedure.
I guess you need dma_map_single() then, or use dma_alloc_coherent instead
of __get_free_pages(). There is no guarantee that the page you allocate
there is actually visible to the PCI host at the same address that the CPU
uses, so you need to map from a CPU address to a DMA address that the PCI
host bridge uses.
Arnd
next prev parent reply other threads:[~2015-01-19 13:49 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-17 10:34 [PATCH 0/5] PCI: st: provide support for dw pcie Gabriel FERNANDEZ
2014-12-17 10:34 ` [PATCH 1/5] ARM: STi: Kconfig update for PCIe support Gabriel FERNANDEZ
2014-12-17 10:34 ` [PATCH 2/5] PCI: st: Add Device Tree bindings for sti pcie Gabriel FERNANDEZ
2014-12-17 22:01 ` Arnd Bergmann
2015-01-19 12:36 ` Gabriel Fernandez
2015-01-19 13:04 ` Gabriel Fernandez
2014-12-22 4:45 ` Pratyush Anand
2014-12-17 10:34 ` [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller Gabriel FERNANDEZ
2014-12-17 22:14 ` Arnd Bergmann
2015-01-19 12:37 ` Gabriel Fernandez
2015-01-19 13:49 ` Arnd Bergmann [this message]
2015-01-21 15:47 ` Gabriel Fernandez
[not found] ` <CAG374jCRByNZuuYxi5+-mKvV7p5-tCf2G+8mTYfzU4rRV4yfYQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-01-21 19:35 ` Arnd Bergmann
2015-01-21 19:59 ` Lucas Stach
2015-01-19 13:08 ` Gabriel Fernandez
[not found] ` <1418812486-12394-4-git-send-email-gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-12-18 6:03 ` Jingoo Han
2015-01-19 12:38 ` Gabriel Fernandez
[not found] ` <000f01d01a88$60405e50$20c11af0$%han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-01-19 13:06 ` Gabriel Fernandez
2014-12-22 5:12 ` Pratyush Anand
2015-01-12 18:43 ` Bjorn Helgaas
2015-01-21 15:32 ` Gabriel Fernandez
2014-12-17 10:34 ` [PATCH 4/5] PCI: designware: Add setup bus-related to pcie_host_ops Gabriel FERNANDEZ
2014-12-17 22:16 ` Arnd Bergmann
2014-12-18 4:58 ` Jingoo Han
2015-01-19 12:38 ` Gabriel Fernandez
2015-01-19 13:54 ` Arnd Bergmann
2015-01-19 15:46 ` Lorenzo Pieralisi
2015-01-19 13:09 ` Gabriel Fernandez
2014-12-17 10:34 ` [PATCH 5/5] PCI: st: disable IO support Gabriel FERNANDEZ
2014-12-17 14:01 ` One Thousand Gnomes
2015-01-21 15:49 ` Gabriel Fernandez
-- strict thread matches above, loose matches on Subject: below --
2015-04-10 7:38 [PATCH 0/5] PCI: st: provide support for dw pcie Gabriel FERNANDEZ
2015-04-10 7:38 ` [PATCH 3/5] PCI: st: Provide support for the sti PCIe controller Gabriel FERNANDEZ
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