* [PATCH v3 01/12] ARM: shmobile: r8a7792: add clock index macros
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
@ 2016-06-08 21:04 ` Sergei Shtylyov
[not found] ` <2256036.Aah0Fxjv7E-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-06-08 21:07 ` [PATCH v3 02/12] ARM: shmobile: r8a7792: add power domain " Sergei Shtylyov
` (7 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:04 UTC (permalink / raw)
To: linux-renesas-soc, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Add macros usable by the device tree sources to reference the R8A7792
clocks by index.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
Changes in version 2:
- removed the SDH, SD0, and SD1 clocks;
- added RCAN and ADSP clock indeces;
- fixed SYS-DMAC0/1 clock indeces.
include/dt-bindings/clock/r8a7792-clock.h | 103 ++++++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
Index: renesas/include/dt-bindings/clock/r8a7792-clock.h
===================================================================
--- /dev/null
+++ renesas/include/dt-bindings/clock/r8a7792-clock.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_H__
+
+/* CPG */
+#define R8A7792_CLK_MAIN 0
+#define R8A7792_CLK_PLL0 1
+#define R8A7792_CLK_PLL1 2
+#define R8A7792_CLK_PLL3 3
+#define R8A7792_CLK_LB 4
+#define R8A7792_CLK_QSPI 5
+#define R8A7792_CLK_Z 6
+#define R8A7792_CLK_RCAN 7
+#define R8A7792_CLK_ADSP 8
+
+/* MSTP0 */
+#define R8A7792_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7792_CLK_TMU1 11
+#define R8A7792_CLK_TMU3 21
+#define R8A7792_CLK_TMU2 22
+#define R8A7792_CLK_CMT0 24
+#define R8A7792_CLK_TMU0 25
+#define R8A7792_CLK_VSP1DU1 27
+#define R8A7792_CLK_VSP1DU0 28
+#define R8A7792_CLK_VSP1_SY 31
+
+/* MSTP2 */
+#define R8A7792_CLK_MSIOF1 8
+#define R8A7792_CLK_SYS_DMAC1 18
+#define R8A7792_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7792_CLK_TPU0 4
+#define R8A7792_CLK_SDHI0 14
+#define R8A7792_CLK_CMT1 29
+
+/* MSTP4 */
+#define R8A7792_CLK_IRQC 7
+
+/* MSTP5 */
+#define R8A7792_CLK_AUDIO_DMAC0 2
+#define R8A7792_CLK_THERMAL 22
+#define R8A7792_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7792_CLK_HSCIF1 16
+#define R8A7792_CLK_HSCIF0 17
+#define R8A7792_CLK_SCIF3 18
+#define R8A7792_CLK_SCIF2 19
+#define R8A7792_CLK_SCIF1 20
+#define R8A7792_CLK_SCIF0 21
+#define R8A7792_CLK_DU1 23
+#define R8A7792_CLK_DU0 24
+
+/* MSTP8 */
+#define R8A7792_CLK_VIN5 4
+#define R8A7792_CLK_VIN4 5
+#define R8A7792_CLK_VIN3 8
+#define R8A7792_CLK_VIN2 9
+#define R8A7792_CLK_VIN1 10
+#define R8A7792_CLK_VIN0 11
+#define R8A7792_CLK_ETHERAVB 12
+
+/* MSTP9 */
+#define R8A7792_CLK_GPIO7 4
+#define R8A7792_CLK_GPIO6 5
+#define R8A7792_CLK_GPIO5 7
+#define R8A7792_CLK_GPIO4 8
+#define R8A7792_CLK_GPIO3 9
+#define R8A7792_CLK_GPIO2 10
+#define R8A7792_CLK_GPIO1 11
+#define R8A7792_CLK_GPIO0 12
+#define R8A7792_CLK_GPIO11 13
+#define R8A7792_CLK_GPIO10 14
+#define R8A7792_CLK_CAN1 15
+#define R8A7792_CLK_CAN0 16
+#define R8A7792_CLK_QSPI_MOD 17
+#define R8A7792_CLK_GPIO9 19
+#define R8A7792_CLK_GPIO8 21
+#define R8A7792_CLK_I2C5 25
+#define R8A7792_CLK_IICDVFS 26
+#define R8A7792_CLK_I2C4 27
+#define R8A7792_CLK_I2C3 28
+#define R8A7792_CLK_I2C2 29
+#define R8A7792_CLK_I2C1 30
+#define R8A7792_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7792_CLK_SSI_ALL 5
+#define R8A7792_CLK_SSI4 11
+#define R8A7792_CLK_SSI3 12
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 02/12] ARM: shmobile: r8a7792: add power domain index macros
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
2016-06-08 21:04 ` [PATCH v3 01/12] ARM: shmobile: r8a7792: add clock index macros Sergei Shtylyov
@ 2016-06-08 21:07 ` Sergei Shtylyov
2016-06-08 21:17 ` [PATCH v3 06/12] ARM: dts: r8a7792: initial SoC device tree Sergei Shtylyov
` (6 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:07 UTC (permalink / raw)
To: linux-renesas-soc, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Add macros usable by the device tree sources to reference R8A7792 SYSC power
domains by index.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
include/dt-bindings/power/r8a7792-sysc.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
Index: renesas/include/dt-bindings/power/r8a7792-sysc.h
===================================================================
--- /dev/null
+++ renesas/include/dt-bindings/power/r8a7792-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7792_PD_CA15_CPU0 0
+#define R8A7792_PD_CA15_CPU1 1
+#define R8A7792_PD_CA15_SCU 12
+#define R8A7792_PD_SGX 20
+#define R8A7792_PD_IMP 24
+
+/* Always-on power area */
+#define R8A7792_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 06/12] ARM: dts: r8a7792: initial SoC device tree
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
2016-06-08 21:04 ` [PATCH v3 01/12] ARM: shmobile: r8a7792: add clock index macros Sergei Shtylyov
2016-06-08 21:07 ` [PATCH v3 02/12] ARM: shmobile: r8a7792: add power domain " Sergei Shtylyov
@ 2016-06-08 21:17 ` Sergei Shtylyov
2016-06-09 10:05 ` Geert Uytterhoeven
2016-06-08 21:28 ` [PATCH v3 07/12] ARM: dts: r8a7792: add SYS-DMAC support Sergei Shtylyov
` (5 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:17 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC,
and the required clock descriptions.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
Changes in version 3:
- moved the fixed factor clocks under the "soc" node;
- added back the CPU1 node, adjusted the changelog.
Changes in version 2:
- explicitly included the IRQ header;
- removed the CPU1 node;
- removed the audio and PCIe bus clocks;
- removed the SDH, SD0, and SD1 CPG clocks;
- added RCAN and ADSP CPG clocks;
- removed the PLL1/2, Z2, ZS, I, B, P, CL, M2, RCLK, OSCCLK, ZB3, ZB3D2, DDR,
and MP fixed factor clocks;
- fixed up the parent and divisor for the CP fixed factor clock;
- swapped the SYS-DMAC0/1 clocks;
- removed all gated clocks except the [H]SCIF, IRQC, and SYS-DMAC ones;
- created the "soc" subnode, moving the SoC device nodes there;
- removed the "clocks" node, moving its fixed clock subnodes to the root and
the MSTP subnodes into the "soc" node.
arch/arm/boot/dts/r8a7792.dtsi | 180 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 180 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -0,0 +1,180 @@
+/*
+ * Device Tree Source for the r8a7792 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a7792-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a7792-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7792";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg_clocks R8A7792_CLK_Z>;
+ power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1000000000>;
+ power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
+ };
+
+ L2_CA15: cache-controller@0 {
+ compatible = "cache";
+ reg = <0>;
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7792_PD_CA15_SCU>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7792-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ /* Special CPG clocks */
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7792-cpg-clocks",
+ "renesas,rcar-gen2-cpg-clocks";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "main", "pll0", "pll1", "pll3",
+ "lb", "qspi", "z", "rcan", "adsp";
+ #power-domain-cells = <0>;
+ };
+
+ /* Fixed factor clocks */
+ zs_clk: zs {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <6>;
+ clock-mult = <1>;
+ };
+ p_clk: p {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <24>;
+ clock-mult = <1>;
+ };
+ cp_clk: cp {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <3>;
+ clock-mult = <1>;
+ };
+
+ /* Gate clocks */
+ mstp2_clks: mstp2_clks@e6150138 {
+ compatible = "renesas,r8a7792-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+ clocks = <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
+ >;
+ clock-output-names = "sys-dmac1", "sys-dmac0";
+ };
+ mstp4_clks: mstp4_clks@e6150140 {
+ compatible = "renesas,r8a7792-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+ clocks = <&cp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7792_CLK_IRQC>;
+ clock-output-names = "irqc";
+ };
+ mstp7_clks: mstp7_clks@e615014c {
+ compatible = "renesas,r8a7792-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+ clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
+ <&p_clk>, <&p_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
+ R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
+ R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
+ >;
+ clock-output-names = "hscif1", "hscif0", "scif3",
+ "scif2", "scif1", "scif0",
+ "du1", "du0";
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v3 06/12] ARM: dts: r8a7792: initial SoC device tree
2016-06-08 21:17 ` [PATCH v3 06/12] ARM: dts: r8a7792: initial SoC device tree Sergei Shtylyov
@ 2016-06-09 10:05 ` Geert Uytterhoeven
2016-06-09 20:36 ` Sergei Shtylyov
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2016-06-09 10:05 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, linux-renesas-soc, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala,
devicetree@vger.kernel.org, Magnus Damm, Russell King,
linux-arm-kernel@lists.infradead.org
Hi Sergei,
On Wed, Jun 8, 2016 at 11:17 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC,
> and the required clock descriptions.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> Changes in version 3:
Thanks for the update!
> --- /dev/null
> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi
> @@ -0,0 +1,180 @@
> +/*
> + * Device Tree Source for the r8a7792 SoC
> + *
> + * Copyright (C) 2016 Cogent Embedded Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/clock/r8a7792-clock.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/r8a7792-sysc.h>
> +
> +/ {
> + compatible = "renesas,r8a7792";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
This is gonna need
enable-method = "renesas,apmu";
soon.
> + soc {
> + p_clk: p {
> + compatible = "fixed-factor-clock";
Missing TAB.
> + clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
> + #clock-cells = <0>;
> + clock-div = <24>;
> + clock-mult = <1>;
> + };
> + cp_clk: cp {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
> + #clock-cells = <0>;
> + clock-div = <3>;
48
(did you check /sys/kernel/debug/clk/clk_summary matches Table 7.2c?)
> + clock-mult = <1>;
> + };
> +
> + /* Gate clocks */
> + mstp7_clks: mstp7_clks@e615014c {
> + compatible = "renesas,r8a7792-mstp-clocks",
> + "renesas,cpg-mstp-clocks";
> + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
> + clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
> + <&p_clk>, <&p_clk>;
> + #clock-cells = <1>;
> + clock-indices = <
> + R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
> + R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
> + R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
> + >;
> + clock-output-names = "hscif1", "hscif0", "scif3",
> + "scif2", "scif1", "scif0",
> + "du1", "du0";
You forgot to drop "du1" and "du0".
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v3 06/12] ARM: dts: r8a7792: initial SoC device tree
2016-06-09 10:05 ` Geert Uytterhoeven
@ 2016-06-09 20:36 ` Sergei Shtylyov
0 siblings, 0 replies; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-09 20:36 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Simon Horman, linux-renesas-soc, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala,
devicetree@vger.kernel.org, Magnus Damm, Russell King,
linux-arm-kernel@lists.infradead.org
On 06/09/2016 01:05 PM, Geert Uytterhoeven wrote:
>> The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC,
>> and the required clock descriptions.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> Changes in version 3:
>
> Thanks for the update!
>
>> --- /dev/null
>> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi
>> @@ -0,0 +1,180 @@
>> +/*
>> + * Device Tree Source for the r8a7792 SoC
>> + *
>> + * Copyright (C) 2016 Cogent Embedded Inc.
>> + *
>> + * This file is licensed under the terms of the GNU General Public License
>> + * version 2. This program is licensed "as is" without any warranty of any
>> + * kind, whether express or implied.
>> + */
>> +
>> +#include <dt-bindings/clock/r8a7792-clock.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/power/r8a7792-sysc.h>
>> +
>> +/ {
>> + compatible = "renesas,r8a7792";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>
> This is gonna need
>
> enable-method = "renesas,apmu";
>
> soon.
When Magnus' patchset lands, we'll see...
>> + soc {
>
>> + p_clk: p {
>> + compatible = "fixed-factor-clock";
>
> Missing TAB.
Argh!
>> + clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
>> + #clock-cells = <0>;
>> + clock-div = <24>;
>> + clock-mult = <1>;
>> + };
>> + cp_clk: cp {
>> + compatible = "fixed-factor-clock";
>> + clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
>> + #clock-cells = <0>;
>> + clock-div = <3>;
>
> 48
Thank you.
>
> (did you check /sys/kernel/debug/clk/clk_summary matches Table 7.2c?)
Now I have! Only the Z clock seem to be out of range -- 1.5 GHz vs 1 GHz max.
>> + clock-mult = <1>;
>> + };
>> +
>> + /* Gate clocks */
>
>> + mstp7_clks: mstp7_clks@e615014c {
>> + compatible = "renesas,r8a7792-mstp-clocks",
>> + "renesas,cpg-mstp-clocks";
>> + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
>> + clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
>> + <&p_clk>, <&p_clk>;
>> + #clock-cells = <1>;
>> + clock-indices = <
>> + R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
>> + R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
>> + R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
>> + >;
>> + clock-output-names = "hscif1", "hscif0", "scif3",
>> + "scif2", "scif1", "scif0",
>> + "du1", "du0";
>
> You forgot to drop "du1" and "du0".
Argh again...
>> + };
>
> Gr{oetje,eeting}s,
>
> Geert
MBR, Sergei
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 07/12] ARM: dts: r8a7792: add SYS-DMAC support
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
` (2 preceding siblings ...)
2016-06-08 21:17 ` [PATCH v3 06/12] ARM: dts: r8a7792: initial SoC device tree Sergei Shtylyov
@ 2016-06-08 21:28 ` Sergei Shtylyov
2016-06-08 21:30 ` [PATCH v3 08/12] ARM: dts: r8a7792: add [H]SCIF support Sergei Shtylyov
` (4 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:28 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Describe SYS-DMAC0/1 in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 3:
- refreshed the patch.
Changes in version 2:
- resolved reject, indenting the device nodes that are now under the "soc" node;
- added Simon's ACK and Geert's tag too.
arch/arm/boot/dts/r8a7792.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -88,6 +88,70 @@
#power-domain-cells = <1>;
};
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7792",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7792",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7792-cpg-clocks",
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 08/12] ARM: dts: r8a7792: add [H]SCIF support
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
` (3 preceding siblings ...)
2016-06-08 21:28 ` [PATCH v3 07/12] ARM: dts: r8a7792: add SYS-DMAC support Sergei Shtylyov
@ 2016-06-08 21:30 ` Sergei Shtylyov
2016-06-08 21:31 ` [PATCH v3 09/12] ARM: dts: r8a7792: add IRQC support Sergei Shtylyov
` (3 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:30 UTC (permalink / raw)
To: horms, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
devicetree
Cc: linux-renesas-soc, magnus.damm, linux, linux-arm-kernel
Describe [H]SCIFs in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 3:
- refreshed the patch.
Changes in version 2:
- resolved reject, indenting the device nodes that are now under the "soc" node;
- added Geert's tag.
arch/arm/boot/dts/r8a7792.dtsi | 90 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -152,6 +152,96 @@
dma-channels = <15>;
};
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7792",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7792",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7792-cpg-clocks",
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 09/12] ARM: dts: r8a7792: add IRQC support
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
` (4 preceding siblings ...)
2016-06-08 21:30 ` [PATCH v3 08/12] ARM: dts: r8a7792: add [H]SCIF support Sergei Shtylyov
@ 2016-06-08 21:31 ` Sergei Shtylyov
2016-06-08 21:33 ` [PATCH v3 10/12] DT: arm: shmobile: document Blanche board Sergei Shtylyov
` (2 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:31 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Describe the IRQC interrupt controller in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 3:
- refreshed the patch.
Changes in version 2:
- resolved reject, indenting the IRQC node that is now under the "soc" node;
- added Geert's tag.
arch/arm/boot/dts/r8a7792.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -70,6 +70,19 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7792", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 10/12] DT: arm: shmobile: document Blanche board
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
` (5 preceding siblings ...)
2016-06-08 21:31 ` [PATCH v3 09/12] ARM: dts: r8a7792: add IRQC support Sergei Shtylyov
@ 2016-06-08 21:33 ` Sergei Shtylyov
2016-06-08 21:35 ` [PATCH v3 11/12] ARM: dts: blanche: initial device tree Sergei Shtylyov
2016-06-08 21:36 ` [PATCH v3 12/12] ARM: dts: blanche: add Ethernet support Sergei Shtylyov
8 siblings, 0 replies; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:33 UTC (permalink / raw)
To: linux-renesas-soc, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Document the Blanche device tree bindings, listing it as a supported board.
This allows to use checkpatch.pl to validate .dts files referring to the
Blanche board.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in version 2:
- added Rob's ACK.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)
Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt
===================================================================
--- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt
+++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -39,6 +39,8 @@ Boards:
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
compatible = "renesas,armadillo800eva"
+ - Blanche (RTP0RC7792SEB00010S)
+ compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 11/12] ARM: dts: blanche: initial device tree
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
` (6 preceding siblings ...)
2016-06-08 21:33 ` [PATCH v3 10/12] DT: arm: shmobile: document Blanche board Sergei Shtylyov
@ 2016-06-08 21:35 ` Sergei Shtylyov
2016-06-08 21:36 ` [PATCH v3 12/12] ARM: dts: blanche: add Ethernet support Sergei Shtylyov
8 siblings, 0 replies; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:35 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Add the initial device tree for the R8A7792 SoC based Blanche board.
The board has 2 debug serial ports: SCIF0 and SCIF3; include support for
them, so that the serial console can work.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 3:
- added Renesas Electronics' copyright.
Changes in version 2:
- added Simon's ACK and Geert's tag too.
arch/arm/boot/dts/Makefile | 1
arch/arm/boot/dts/r8a7792-blanche.dts | 45 ++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
Index: renesas/arch/arm/boot/dts/Makefile
===================================================================
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -638,6 +638,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7790-lager.dtb \
r8a7791-koelsch.dtb \
r8a7791-porter.dtb \
+ r8a7792-blanche.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -0,0 +1,45 @@
+/*
+ * Device Tree Source for the Blanche board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7792.dtsi"
+
+/ {
+ model = "Blanche";
+ compatible = "renesas,blanche", "renesas,r8a7792";
+
+ aliases {
+ serial0 = &scif0;
+ serial1 = &scif3;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&scif0 {
+ status = "okay";
+};
+
+&scif3 {
+ status = "okay";
+};
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 12/12] ARM: dts: blanche: add Ethernet support
2016-06-08 21:01 [PATCH v3 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
` (7 preceding siblings ...)
2016-06-08 21:35 ` [PATCH v3 11/12] ARM: dts: blanche: initial device tree Sergei Shtylyov
@ 2016-06-08 21:36 ` Sergei Shtylyov
8 siblings, 0 replies; 13+ messages in thread
From: Sergei Shtylyov @ 2016-06-08 21:36 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
R8A7792 SoC doesn't have the EtherMAC core, so SMSC LAN89218 Ethernet
chip was used instead on the Blanche board; this chip is compatible with
SMSC LAN9115 for which there's a (device tree aware) driver. Describe
the chip in the Blanche device tree; enable DHCP and NFS root in the
kernel command line for the kernel booting.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
---
Changes in version 3:
- refreshed the patch.
Changes in version 2:
- added Simon's ACK.
arch/arm/boot/dts/r8a7792-blanche.dts | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792-blanche.dts
+++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -22,7 +22,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -30,6 +30,27 @@
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
+
+ d3_3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "D3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ethernet@18000000 {
+ compatible = "smsc,lan89218", "smsc,lan9115";
+ reg = <0 0x18000000 0 0x100>;
+ phy-mode = "mii";
+ interrupt-parent = <&irqc>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ smsc,irq-push-pull;
+ reg-io-width = <4>;
+ vddvario-supply = <&d3_3v>;
+ vdd33a-supply = <&d3_3v>;
+ };
};
&extal_clk {
^ permalink raw reply [flat|nested] 13+ messages in thread