Re: [PATCH v3 0/7] ISA string parser cleanups

[patchwork-bot+linux-riscv@kernel.org]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Wed,  7 Jun 2023 21:28:24 +0100 you wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> With that out of the way, here are some cleanups for our riscv,isa
> handling.
> 
> Here are some bits that were discussed with Drew on the "should we
> allow caps" threads that I have now created patches for:
> - splitting of riscv_of_processor_hartid() into two distinct functions,
>   one for use purely during early boot, prior to the establishment of
>   the possible-cpus mask & another to fit the other current use-cases
> - that then allows us to then completely skip some validation of the
>   hartid in the parser
> - the biggest diff in the series is a rework of the comments in the
>   parser, as I have mostly found the existing (sparse) ones to not be
>   all that helpful whenever I have to go back and look at it
> - from writing the comments, I found a conditional doing a bit of a
>   dance that I found counter-intuitive, so I've had a go at making that
>   match what I would expect a little better
> - `i` implies 4 other extensions, so add them as extensions and set
>   them for the craic. Sure why not like...
> 
> [...]

Here is the summary with links:
  - [v3,1/7] RISC-V: simplify register width check in ISA string parsing
    https://git.kernel.org/riscv/c/fed14be476f0
  - [v3,2/7] RISC-V: split early & late of_node to hartid mapping
    https://git.kernel.org/riscv/c/2ac874343749
  - [v3,3/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing
    https://git.kernel.org/riscv/c/069b0d517077
  - [v3,4/7] RISC-V: rework comments in ISA string parser
    https://git.kernel.org/riscv/c/6b913e3da87d
  - [v3,5/7] RISC-V: remove decrement/increment dance in ISA string parser
    https://git.kernel.org/riscv/c/7816ebc1ddd1
  - [v3,6/7] dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support
    https://git.kernel.org/riscv/c/1e5cae98e46d
  - [v3,7/7] RISC-V: always report presence of extensions formerly part of the base ISA
    https://git.kernel.org/riscv/c/07edc32779e3

You are awesome, thank you!
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