From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Magnus Damm <magnus.damm@gmail.com>,
Simon Horman <horms@verge.net.au>,
SH-Linux <linux-sh@vger.kernel.org>,
devicetree-discuss@lists.ozlabs.org,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3] irqchip: renesas-intc-irqpin: DT binding for sense bitfield width
Date: Mon, 08 Apr 2013 11:56:26 +0200 [thread overview]
Message-ID: <1694336.shM2ct4pzX@avalon> (raw)
In-Reply-To: <Pine.LNX.4.64.1304081002190.29945@axis700.grange>
Hi Guennadi,
Thanks for the patch.
On Monday 08 April 2013 10:08:40 Guennadi Liakhovetski wrote:
> Most Renesas irqpin controllers have 4-bit sense fields, however, some
> have different widths. This patch adds a DT binding to optionally
> specify such non-standard values.
>
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
> ---
>
> v3: move the code to a common location, where device configuration
> parameters are retrieved
>
> .../interrupt-controller/renesas,intc-irqpin.txt | 13 +++++++++++++
> drivers/irqchip/irq-renesas-intc-irqpin.c | 4 ++++
> 2 files changed, 17 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.
> txt
>
> diff --git
> a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi
> n.txt
> b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi
> n.txt new file mode 100644
> index 0000000..c6f09b7
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpi
> n.txt @@ -0,0 +1,13 @@
> +DT bindings for the R-/SH-Mobile irqpin controller
> +
> +Required properties:
> +
> +- compatible: has to be "renesas,intc-irqpin"
> +- #interrupt-cells: has to be <2>
> +
> +Optional properties:
> +
> +- any properties, listed in interrupts.txt in this directory, and any
> standard
> + resource allocation properties
> +- sense-bitfield-width: width of a single sense bitfield in the SENSE
> register,
> + if different from the default 4 bits
Wouldn't it be better to define per-SoC compatible strings, and infer the
sense bitfield width from that ?
> diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c
> b/drivers/irqchip/irq-renesas-intc-irqpin.c index 5a68e5a..4aca1b2 100644
> --- a/drivers/irqchip/irq-renesas-intc-irqpin.c
> +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
> @@ -18,6 +18,7 @@
> */
>
> #include <linux/init.h>
> +#include <linux/of.h>
> #include <linux/platform_device.h>
> #include <linux/spinlock.h>
> #include <linux/interrupt.h>
> @@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device
> *pdev) /* deal with driver instance configuration */
> if (pdata)
> memcpy(&p->config, pdata, sizeof(*pdata));
> + else
> + of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
> + &p->config.sense_bitfield_width);
> if (!p->config.sense_bitfield_width)
> p->config.sense_bitfield_width = 4; /* default to 4 bits */
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2013-04-08 9:56 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-08 8:08 [PATCH v3] irqchip: renesas-intc-irqpin: DT binding for sense bitfield width Guennadi Liakhovetski
2013-04-08 9:56 ` Laurent Pinchart [this message]
2013-04-08 11:25 ` Guennadi Liakhovetski
[not found] ` <Pine.LNX.4.64.1304081324370.29945-0199iw4Nj15frtckUFj5Ag@public.gmane.org>
2013-04-08 11:37 ` Laurent Pinchart
2013-04-08 12:15 ` Guennadi Liakhovetski
2013-04-08 23:22 ` Laurent Pinchart
2013-04-09 8:44 ` Simon Horman
2013-04-09 22:23 ` Magnus Damm
2013-04-10 0:48 ` Simon Horman
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