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From: Mrinmay Sarkar <quic_msarkar@quicinc.com>
To: agross@kernel.org, andersson@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	konrad.dybcio@linaro.org, mani@kernel.org, robh+dt@kernel.org
Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com,
	quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com,
	dmitry.baryshkov@linaro.org, robh@kernel.org,
	quic_krichai@quicinc.com, quic_vbadigan@quicinc.com,
	quic_parass@quicinc.com, quic_schintav@quicinc.com,
	quic_shijjose@quicinc.com,
	"Mrinmay Sarkar" <quic_msarkar@quicinc.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH v1 2/3] PCI: qcom-ep: Enable cache coherency for SA8775P EP
Date: Tue, 31 Oct 2023 21:16:25 +0530	[thread overview]
Message-ID: <1698767186-5046-3-git-send-email-quic_msarkar@quicinc.com> (raw)
In-Reply-To: <1698767186-5046-1-git-send-email-quic_msarkar@quicinc.com>

This change will enable cache snooping logic to support
cache coherency for SA8755P EP platform.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
 drivers/pci/controller/dwc/pcie-qcom-ep.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 3a53d97..bc958a0 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -47,6 +47,7 @@
 #define PARF_DBI_BASE_ADDR_HI			0x354
 #define PARF_SLV_ADDR_SPACE_SIZE		0x358
 #define PARF_SLV_ADDR_SPACE_SIZE_HI		0x35c
+#define PCIE_PARF_NO_SNOOP_OVERIDE		0x3d4
 #define PARF_ATU_BASE_ADDR			0x634
 #define PARF_ATU_BASE_ADDR_HI			0x638
 #define PARF_SRIS_MODE				0x644
@@ -86,6 +87,9 @@
 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN	BIT(2)
 #define PARF_DEBUG_INT_RADM_PM_TURNOFF		BIT(3)
 
+/* PARF_NO_SNOOP_OVERIDE register value */
+#define NO_SNOOP_OVERIDE_EN			0xa
+
 /* PARF_DEVICE_TYPE register fields */
 #define PARF_DEVICE_TYPE_EP			0x0
 
@@ -489,6 +493,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
 	val |= BIT(8);
 	writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
 
+	/* Enable cache snooping for SA8775P */
+	if (of_device_is_compatible(dev->of_node, "qcom,sa8775p-pcie-ep"))
+		writel_relaxed(NO_SNOOP_OVERIDE_EN, pcie_ep->parf + PCIE_PARF_NO_SNOOP_OVERIDE);
+
 	return 0;
 
 err_disable_resources:
-- 
2.7.4


  parent reply	other threads:[~2023-10-31 15:46 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-31 15:46 [PATCH v1 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Mrinmay Sarkar
2023-10-31 15:46 ` [PATCH v1 1/3] PCI: qcom: Enable cache coherency for SA8775P RC Mrinmay Sarkar
2023-10-31 16:50   ` Konrad Dybcio
2023-11-02 10:16     ` Mrinmay Sarkar
2023-11-02 22:27       ` Konrad Dybcio
2023-11-02 15:34   ` Dmitry Baryshkov
2023-11-02 16:36     ` Manivannan Sadhasivam
2023-11-02 22:25       ` Konrad Dybcio
2023-11-03  7:58         ` Manivannan Sadhasivam
2023-11-06  7:19           ` Mrinmay Sarkar
2023-10-31 15:46 ` Mrinmay Sarkar [this message]
2023-10-31 16:50   ` [PATCH v1 2/3] PCI: qcom-ep: Enable cache coherency for SA8775P EP Konrad Dybcio
2023-10-31 15:46 ` [PATCH v1 3/3] arm64: dts: qcom: sa8775p: Mark PCIe controller as cache coherent Mrinmay Sarkar
2023-10-31 16:57 ` [PATCH v1 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Manivannan Sadhasivam

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