From: Mrinmay Sarkar <quic_msarkar@quicinc.com>
To: agross@kernel.org, andersson@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
konrad.dybcio@linaro.org, mani@kernel.org, robh+dt@kernel.org
Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com,
quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com,
dmitry.baryshkov@linaro.org, robh@kernel.org,
quic_krichai@quicinc.com, quic_vbadigan@quicinc.com,
quic_parass@quicinc.com, quic_schintav@quicinc.com,
quic_shijjose@quicinc.com,
"Mrinmay Sarkar" <quic_msarkar@quicinc.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH v2 1/3] PCI: qcom: Enable cache coherency for SA8775P RC
Date: Sat, 11 Nov 2023 09:24:33 +0530 [thread overview]
Message-ID: <1699674876-4982-2-git-send-email-quic_msarkar@quicinc.com> (raw)
In-Reply-To: <1699674876-4982-1-git-send-email-quic_msarkar@quicinc.com>
This change will enable cache snooping logic to support
cache coherency for 8755 RC platform.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 6902e97..b82ccd1 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -51,6 +51,7 @@
#define PARF_SID_OFFSET 0x234
#define PARF_BDF_TRANSLATE_CFG 0x24c
#define PARF_SLV_ADDR_SPACE_SIZE 0x358
+#define PCIE_PARF_NO_SNOOP_OVERIDE 0x3d4
#define PARF_DEVICE_TYPE 0x1000
#define PARF_BDF_TO_SID_TABLE_N 0x2000
@@ -117,6 +118,10 @@
/* PARF_LTSSM register fields */
#define LTSSM_EN BIT(8)
+/* PARF_NO_SNOOP_OVERIDE register fields */
+#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
+#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
+
/* PARF_DEVICE_TYPE register fields */
#define DEVICE_TYPE_RC 0x4
@@ -961,6 +966,14 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+
+ /* Enable cache snooping for SA8775P */
+ if (of_device_is_compatible(dev->of_node, "qcom,pcie-sa8775p"))
+ writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
+ pcie->parf + PCIE_PARF_NO_SNOOP_OVERIDE);
+
qcom_pcie_clear_hpc(pcie->pci);
return 0;
--
2.7.4
next prev parent reply other threads:[~2023-11-11 3:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-11 3:54 [PATCH v2 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Mrinmay Sarkar
2023-11-11 3:54 ` Mrinmay Sarkar [this message]
2023-11-11 3:54 ` [PATCH v2 2/3] PCI: qcom-ep: Enable cache coherency for SA8775P EP Mrinmay Sarkar
2023-11-11 3:54 ` [PATCH v2 3/3] arm64: dts: qcom: sa8775p: Mark PCIe controller as cache coherent Mrinmay Sarkar
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