Re: [PATCH v4 02/10] arm64: dts: qcom: qcs6490-rb3gen2: Add TC956x PCIe switch node

[Krishna Chaitanya Chundru <quic_krichai@quicinc.com>]

On 3/18/2025 10:30 PM, Dmitry Baryshkov wrote:
> On Tue, 18 Mar 2025 at 18:11, Krishna Chaitanya Chundru
> <krishna.chundru@oss.qualcomm.com> wrote:
>>
>>
>>
>> On 3/17/2025 4:57 PM, Dmitry Baryshkov wrote:
>>> On Tue, Feb 25, 2025 at 03:03:59PM +0530, Krishna Chaitanya Chundru wrote:
>>>> Add a node for the TC956x PCIe switch, which has three downstream ports.
>>>> Two embedded Ethernet devices are present on one of the downstream ports.
>>>>
>>>> Power to the TC956x is supplied through two LDO regulators, controlled by
>>>> two GPIOs, which are added as fixed regulators. Configure the TC956x
>>>> through I2C.
>>>>
>>>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>>>> Reviewed-by: Bjorn Andersson <andersson@kernel.org>
>>>> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 116 +++++++++++++++++++++++++++
>>>>    arch/arm64/boot/dts/qcom/sc7280.dtsi         |   2 +-
>>>>    2 files changed, 117 insertions(+), 1 deletion(-)
>>>>
>>>> @@ -735,6 +760,75 @@ &pcie1_phy {
>>>>       status = "okay";
>>>>    };
>>>>
>>>> +&pcie1_port {
>>>> +    pcie@0,0 {
>>>> +            compatible = "pci1179,0623", "pciclass,0604";
>>>> +            reg = <0x10000 0x0 0x0 0x0 0x0>;
>>>> +            #address-cells = <3>;
>>>> +            #size-cells = <2>;
>>>> +
>>>> +            device_type = "pci";
>>>> +            ranges;
>>>> +            bus-range = <0x2 0xff>;
>>>> +
>>>> +            vddc-supply = <&vdd_ntn_0p9>;
>>>> +            vdd18-supply = <&vdd_ntn_1p8>;
>>>> +            vdd09-supply = <&vdd_ntn_0p9>;
>>>> +            vddio1-supply = <&vdd_ntn_1p8>;
>>>> +            vddio2-supply = <&vdd_ntn_1p8>;
>>>> +            vddio18-supply = <&vdd_ntn_1p8>;
>>>> +
>>>> +            i2c-parent = <&i2c0 0x77>;
>>>> +
>>>> +            reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>;
>>>> +
>>>
>>> I think I've responded here, but I'm not sure where the message went:
>>> please add pinctrl entry for this pin.
>>>
>> Do we need to also add pinctrl property for this node and refer the
>> pinctrl entry for this pin?
> 
> I think that is what I've asked for, was that not?
Currently there is no pincntrl property defined for this.

- Krishna Chaitanya.
>