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[195.231.44.239]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4814a72cdb8sm3375919f8f.35.2026.08.11.03.35.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Aug 2026 03:35:52 -0700 (PDT) Message-ID: <16b71fd7-9911-429b-a5a0-577f6ba0e999@redhat.com> Date: Tue, 11 Aug 2026 12:35:50 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v11 0/9] net: dsa: add DSA support for the LAN9645x switch chip family To: =?UTF-8?Q?Jens_Emil_Schulz_=C3=98stergaard?= , UNGLinuxDriver@microchip.com, Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Simon Horman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Woojung Huh , Russell King , Steen Hegelund , Daniel Machon Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org References: <20260805-dsa_lan9645x_switch_driver_base-v11-0-007ebc983a0a@microchip.com> From: Paolo Abeni Content-Language: en-US In-Reply-To: <20260805-dsa_lan9645x_switch_driver_base-v11-0-007ebc983a0a@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 8/5/26 4:34 PM, Jens Emil Schulz Østergaard wrote: > This series provides the Microchip LAN9645X Switch driver. > > The LAN9645x is a family of chips with ethernet switch functionality and > multiple peripheral functions. The switch delivers up to 9 ethernet > ports and 12 Gbps switching bandwidth. > > The switch chip has 5 integrated copper PHYs, support for 2x RGMII > interfaces, 2x SGMII and one QSGMII interface. > > The switch chip is from the same design architecture family as ocelot > and lan966x, and the driver reflects this similarity. However, LAN9645x > does not have an internal CPU in any package, and must be driven > externally. For register IO it supports interfaces such as SPI, I2C and > MDIO. > > The chip supports a variety of network features such as > > * Mactable for MDB/FDB functionality > * Bridge forwarding offload > * VLAN-aware bridging > * IGMP/MLD snooping > * Link aggregation > * PTP timestamping > * FRER (802.1CB) > * Media Redundancy Protocol > * Parallel Redundancy and High-Availability Seamless Redundancy > (HSR/PRP) in DANH/DANP mode > * Per stream filtering and policing > * Shapers such as Credit Based Shaping and Time Aware Shaing > * Frame preemption > * A TCAM (VCAP) for line-rate frame processing > > The LAN9645x family consists of the following SKUs: > > LAN96455F > LAN96457F > LAN96459F > LAN96455S > LAN96457S > LAN96459S > > The difference between the SKUs is the number of supported ports (5, 7 > or 9) and features supported. The F subfamily supports HSR/PRP and TSN, > while the S subfamily does not. > > The intended way to bind this driver is using a parent MFD driver, > responsible for the register IO protocol, and distributing regmaps to > child devices. The goal is to use the same approach as the MFD driver in > drivers/mfd/ocelot-spi.c. > > This driver expects to request named regmaps from a parent device. This > approach is similar to the DSA driver > > drivers/net/dsa/ocelot/ocelot_ext.c > > which supports being driven by an external CPU via SPI with parent > device drivers/mfd/ocelot-spi.c. > > The MFD driver will come in a later series, because there are > requirements on the number of child devices before a driver qualifies as > a MFD device. > > Development is done using the LAN966x as a host CPU, running the lan966x > swichdev driver, using the EVB-LAN9668 EDS2 board. > > The datasheet is available here: > https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/LAN9645xF-Data-Sheet-DS00006065.pdf > > This series will deliver the following features: > > * Standalone ports > * Bridge forwarding and FDB offloading > * VLAN-aware bridge > * Stats integration > > More support will be added at a later stage. Here is a tentative plan of > future patches for this DSA driver: > > * Add LAG support. > * Add MDB support. > * Add TC matchall mirror support. > * Add TC matchall police support. > * Add DCB/qos support. > * Add simple TC support: mqprio, cbs, tbf, ebf. > * Add TC flower filter support. > * Add HSR/PRP offloading support. > * Add PTP support. > * Add TC taprio support. > > For completeness I include tentative plan of planned patches for > LAN9645x peripherals: > > * Extend pinctrl-ocelot for LAN9645x: > https://lore.kernel.org/linux-gpio/20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-0-1228155ed0ee@microchip.com/ > * Add driver for internal PHY: > https://lore.kernel.org/netdev/20260123-phy_micrel_add_support_for_lan9645x_internal_phy-v1-1-8484b1a5a7fd@microchip.com/ > * MFD driver for managing register IO protocol and child device > initialization. > * Extend pinctrl-microchip-sgpio for LAN9645x support. > * Extend i2c_designware for LAN9645x support. > * Add driver for outbound interrupt controller. > * Add serdes driver for lan9645x. > > Signed-off-by: Jens Emil Schulz Østergaard I forwarded the feedback from sashiko/nipa, but sashiko gemini has more comments: https://sashiko.dev/#/patchset/20260805-dsa_lan9645x_switch_driver_base-v11-0-007ebc983a0a%40microchip.com please have a look and also to net-next commit c82ff94592fb /P