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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Dan Carpenter <dan.carpenter@linaro.org>,
	Jan Petrous <jan.petrous@oss.nxp.com>
Cc: s32@nxp.com, Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	netdev@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linaro-s32@linaro.org
Subject: Re: [PATCH 3/4] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
Date: Mon, 1 Dec 2025 18:33:07 +0100	[thread overview]
Message-ID: <16bb96e9-c632-457c-8179-82c17bd2a685@kernel.org> (raw)
In-Reply-To: <333487ea3d23699c7953524cda082813ac4d7be3.1764592300.git.dan.carpenter@linaro.org>

On 01/12/2025 14:08, Dan Carpenter wrote:
> The S32 chipset has a GPR region which has a miscellaneous registers
> including the GMAC_0_CTRL_STS register.  Originally this code accessed
> that register in a sort of ad-hoc way, but we want to access it using
> the syscon interface.
> 
> We still need to maintain the old method of accessing the GMAC register
> but using a syscon will let us access other registers more cleanly.
> 
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
>  Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..17f6c50dca03 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> @@ -32,6 +32,11 @@ properties:
>        - description: Main GMAC registers
>        - description: GMAC PHY mode control register
>  
> +  phy-sel:

Missing vendor prefix.

> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - description: The offset into the s32 GPR syscon

No, first item is not the offset but the phandle. You need syntax like here:

https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42

The description of the first item (unlike in example above) should say
what is the purpose, how this device is using GPR region, what is it
needed for.

Best regards,
Krzysztof

  reply	other threads:[~2025-12-01 17:33 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-01 13:08 [PATCH 0/4] s32g: Use a syscon for GPR Dan Carpenter
2025-12-01 13:08 ` [PATCH 2/4] dt-bindings: mfd: syscon: Document the GPR syscon for the NXP S32 SoCs Dan Carpenter
2025-12-01 17:30   ` Krzysztof Kozlowski
2025-12-01 13:08 ` [PATCH 3/4] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
2025-12-01 17:33   ` Krzysztof Kozlowski [this message]
2025-12-15 10:59     ` Dan Carpenter
2025-12-15 11:03       ` Dan Carpenter
2025-12-01 13:08 ` [PATCH 4/4] dts: s32g: Add GPR syscon region Dan Carpenter
2025-12-01 16:42   ` Frank Li
2025-12-01 16:55     ` Russell King (Oracle)
2025-12-01 14:31 ` [PATCH 0/4] s32g: Use a syscon for GPR Dan Carpenter

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