[PATCH v4 00/20] riscv: report more ISA extensions through hwprobe

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* [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe
@ 2023-11-14 14:12 Clément Léger
  2023-11-14 14:12 ` [PATCH v4 01/20] riscv: add ISA extension parsing for Zbc Clément Léger
                   ` (21 more replies)
  0 siblings, 22 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

In order to be able to gather more information about the supported ISA
extensions from userspace using the hwprobe syscall, add more ISA
extensions report. This series adds the following ISA extensions parsing
support:

- Zfh[min]
- Zvfh[min]
- Zihintntl
- Zbc
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknh[ab]
- Zvksed
- Zvksh
- Zvkn
- Zvknc
- Zvkng
- Zvks
- Zvksc
- Zvksg
- Zvkt
- Zfa
- Zbkb
- Zbkc
- Zbkx
- Zknd
- Zkne
- Zknh
- Zkr
- Zksed
- Zksh
- Zkt

Some of these extensions are actually shorthands for other "sub"
extensions. This series includes a patch from Conor/Evan that adds a way
to specify such "bundled" extensions. When exposing these bundled
extensions to userspace through hwprobe, only the "sub" extensions are
exposed.

In order to test it, one can use qemu and the small hwprobe utility
provided[1]. Run qemu by specifying additional ISA extensions, for
instance:

$ qemu-system-riscv64 -cpu rv64,v=true,zk=true,zvksh=true,zvkned=true
  <whatever options you want>

Then, run hwprobe:

$ ./hwprobe
Base system ISA:
 - IMA_FD
 - C
 - V
Supported extensions:
 - Zba
 - Zbb
 - Zbs
 - Zbc
 - Zbkb
 - Zbkc
 - Zbkx
 - Zknd
 - Zkne
 - Zknh
 - Zkt
 - Zvkned
 - Zvksh
 - Zihintntl
 - Zfa

Link: https://github.com/clementleger/hwprobe_dump [1]

---
Changes in V4:
 - Rebase on master
 - Do not represent zvknhb as a superset anymore
 - Remove mention to hwprobe in dt-bindings documents
 - Add a text specifying that Zkr string dt binding means that the CSR
   provided by Zkr are accessible only by the privilege level to which
the device-tree has been provided.
 - Use a pointer for extension instead of struct copy in patch 1
 - Add missing RISCV_ISA_EXT_ZBC define
 - Remove ISA check macro since another similar commit was merged

Changes in V3:
 - Rebased on top of origin/master
 - Rename bundle_ext to subset_ext since it is used for superset
   extensions (Zvbb for instance).
 - Add an invalid id for pure lasso extension
 - Fix wrong type for check_isa ext, int -> unsigned int
 - Use bundled extension for ZVBB/ZVNHB
 - Split ZBC hwprobe support from scalar crypto patch
 - Fix typos (Evan)
 - Added a few Rb: from Evan
 - Change Zfh/Zfhmin to Zfh[min] to be more coherent with other commits
 - Reword comment about CHECK_ISA_EXT to be more clear

Changes in V2:
 - Fix typo in first commit title (fatorize->factorize)
 - Add Zfa support
 - Fix missing uppercase for Zvkt naming in dt-bindings
 - Add Conor Acked-by on dt-bindings commits
 - Add scalar crypto support from Conor/Evan.
 - Use reporting of bunbled extensions for vector crypto

Clément Léger (19):
  riscv: add ISA extension parsing for Zbc
  riscv: hwprobe: export missing Zbc ISA extension
  riscv: hwprobe: add support for scalar crypto ISA extensions
  dt-bindings: riscv: add scalar crypto ISA extensions description
  riscv: add ISA extension parsing for vector crypto
  riscv: hwprobe: export vector crypto ISA extensions
  dt-bindings: riscv: add vector crypto ISA extensions description
  riscv: add ISA extension parsing for Zfh/Zfh[min]
  riscv: hwprobe: export Zfh[min] ISA extensions
  dt-bindings: riscv: add Zfh[min] ISA extensions description
  riscv: add ISA extension parsing for Zihintntl
  riscv: hwprobe: export Zhintntl ISA extension
  dt-bindings: riscv: add Zihintntl ISA extension description
  riscv: add ISA extension parsing for Zvfh[min]
  riscv: hwprobe: export Zvfh[min] ISA extensions
  dt-bindings: riscv: add Zvfh[min] ISA extension description
  riscv: add ISA extension parsing for Zfa
  riscv: hwprobe: export Zfa ISA extension
  dt-bindings: riscv: add Zfa ISA extension description

Evan Green (1):
  riscv: add ISA extension parsing for scalar crypto

 Documentation/arch/riscv/hwprobe.rst          |  81 +++++++
 .../devicetree/bindings/riscv/extensions.yaml | 213 ++++++++++++++++++
 arch/riscv/include/asm/cpufeature.h           |   4 +-
 arch/riscv/include/asm/hwcap.h                |  30 ++-
 arch/riscv/include/uapi/asm/hwprobe.h         |  26 +++
 arch/riscv/kernel/cpufeature.c                | 189 ++++++++++++++--
 arch/riscv/kernel/sys_riscv.c                 |  33 +++
 7 files changed, 551 insertions(+), 25 deletions(-)

-- 
2.42.0


^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v4 01/20] riscv: add ISA extension parsing for Zbc
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 02/20] riscv: hwprobe: export missing Zbc ISA extension Clément Léger
                   ` (20 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Zbc was documented in the dt-bindings but actually not supported in ISA
string parsing. Add it.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 06d30526ef3b..afa9abc1a0b0 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -57,6 +57,7 @@
 #define RISCV_ISA_EXT_ZIHPM		42
 #define RISCV_ISA_EXT_SMSTATEEN		43
 #define RISCV_ISA_EXT_ZICOND		44
+#define RISCV_ISA_EXT_ZBC		45
 
 #define RISCV_ISA_EXT_MAX		64
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b3785ffc1570..eae14daa5a75 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -176,6 +176,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
+	__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
 	__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 02/20] riscv: hwprobe: export missing Zbc ISA extension
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
  2023-11-14 14:12 ` [PATCH v4 01/20] riscv: add ISA extension parsing for Zbc Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 03/20] riscv: add ISA extension parsing for scalar crypto Clément Léger
                   ` (19 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

While Zba and Zbb were exported through hwprobe, Zbc was not. Export it.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 3 +++
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_riscv.c         | 1 +
 3 files changed, 5 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 7b2384de471f..3f71da935a65 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -80,6 +80,9 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
        ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
+       in version 1.0 of the Bit-Manipulation ISA extensions.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index b659ffcfcdb4..aca5abc7ebee 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -30,6 +30,7 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZBB		(1 << 4)
 #define		RISCV_HWPROBE_EXT_ZBS		(1 << 5)
 #define		RISCV_HWPROBE_EXT_ZICBOZ	(1 << 6)
+#define		RISCV_HWPROBE_EXT_ZBC		(1 << 7)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index c712037dbe10..7a40145e9628 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -162,6 +162,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZBB);
 		EXT_KEY(ZBS);
 		EXT_KEY(ZICBOZ);
+		EXT_KEY(ZBC);
 #undef EXT_KEY
 	}
 
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 03/20] riscv: add ISA extension parsing for scalar crypto
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
  2023-11-14 14:12 ` [PATCH v4 01/20] riscv: add ISA extension parsing for Zbc Clément Léger
  2023-11-14 14:12 ` [PATCH v4 02/20] riscv: hwprobe: export missing Zbc ISA extension Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 04/20] riscv: hwprobe: add support for scalar crypto ISA extensions Clément Léger
                   ` (18 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih,
	Conor Dooley

From: Evan Green <evan@rivosinc.com>

The Scalar Crypto specification defines Zk as a shorthand for the
Zkn, Zkr and Zkt extensions. The same follows for both Zkn, Zks and Zbk,
which are all shorthands for various other extensions. The detailed
breakdown can be found in their dt-binding entries.

Since Zkn also implies the Zbkb, Zbkc and Zbkx extensions, simply passing
"zk" through a DT should enable all of Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt.
For example, setting the "riscv,isa" DT property to "rv64imafdc_zk"
should generate the following cpuinfo output:
"rv64imafdc_zicntr_zicsr_zifencei_zihpm_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zkt"

riscv_isa_ext_data grows a pair of new members, to permit setting the
relevant bits for "bundled" extensions, both while parsing the ISA string
and the new dedicated extension properties.

Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Evan Green <evan@rivosinc.com>
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/include/asm/cpufeature.h |   4 +-
 arch/riscv/include/asm/hwcap.h      |  11 +++
 arch/riscv/kernel/cpufeature.c      | 118 ++++++++++++++++++++++------
 3 files changed, 109 insertions(+), 24 deletions(-)

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index a418c3112cd6..fbdde8b8a47e 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -59,6 +59,8 @@ struct riscv_isa_ext_data {
 	const unsigned int id;
 	const char *name;
 	const char *property;
+	const unsigned int *subset_ext_ids;
+	const unsigned int subset_ext_size;
 };
 
 extern const struct riscv_isa_ext_data riscv_isa_ext[];
@@ -67,7 +69,7 @@ extern bool riscv_isa_fallback;
 
 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
 
-bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
+bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit);
 #define riscv_isa_extension_available(isa_bitmap, ext)	\
 	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
 
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index afa9abc1a0b0..b0857c64bf6e 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -58,8 +58,19 @@
 #define RISCV_ISA_EXT_SMSTATEEN		43
 #define RISCV_ISA_EXT_ZICOND		44
 #define RISCV_ISA_EXT_ZBC		45
+#define RISCV_ISA_EXT_ZBKB		46
+#define RISCV_ISA_EXT_ZBKC		47
+#define RISCV_ISA_EXT_ZBKX		48
+#define RISCV_ISA_EXT_ZKND		49
+#define RISCV_ISA_EXT_ZKNE		50
+#define RISCV_ISA_EXT_ZKNH		51
+#define RISCV_ISA_EXT_ZKR		52
+#define RISCV_ISA_EXT_ZKSED		53
+#define RISCV_ISA_EXT_ZKSH		54
+#define RISCV_ISA_EXT_ZKT		55
 
 #define RISCV_ISA_EXT_MAX		64
+#define RISCV_ISA_EXT_INVALID		U32_MAX
 
 #ifdef CONFIG_RISCV_M_MODE
 #define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SMAIA
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index eae14daa5a75..a2871bceaad9 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -70,7 +70,7 @@ EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
  *
  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  */
-bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
+bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit)
 {
 	const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
 
@@ -102,17 +102,53 @@ static bool riscv_isa_extension_check(int id)
 			return false;
 		}
 		return true;
+	case RISCV_ISA_EXT_INVALID:
+		return false;
 	}
 
 	return true;
 }
 
-#define __RISCV_ISA_EXT_DATA(_name, _id) {	\
-	.name = #_name,				\
-	.property = #_name,			\
-	.id = _id,				\
+#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) {	\
+	.name = #_name,								\
+	.property = #_name,							\
+	.id = _id,								\
+	.subset_ext_ids = _subset_exts,						\
+	.subset_ext_size = _subset_exts_size					\
 }
 
+#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0)
+
+/* Used to declare pure "lasso" extension (Zk for instance) */
+#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \
+	_RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts))
+
+static const unsigned int riscv_zk_bundled_exts[] = {
+	RISCV_ISA_EXT_ZBKB,
+	RISCV_ISA_EXT_ZBKC,
+	RISCV_ISA_EXT_ZBKX,
+	RISCV_ISA_EXT_ZKND,
+	RISCV_ISA_EXT_ZKNE,
+	RISCV_ISA_EXT_ZKR,
+	RISCV_ISA_EXT_ZKT,
+};
+
+static const unsigned int riscv_zkn_bundled_exts[] = {
+	RISCV_ISA_EXT_ZBKB,
+	RISCV_ISA_EXT_ZBKC,
+	RISCV_ISA_EXT_ZBKX,
+	RISCV_ISA_EXT_ZKND,
+	RISCV_ISA_EXT_ZKNE,
+	RISCV_ISA_EXT_ZKNH,
+};
+
+static const unsigned int riscv_zks_bundled_exts[] = {
+	RISCV_ISA_EXT_ZBKB,
+	RISCV_ISA_EXT_ZBKC,
+	RISCV_ISA_EXT_ZKSED,
+	RISCV_ISA_EXT_ZKSH
+};
+
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
  * chapter 27 of the unprivileged specification.
@@ -177,7 +213,20 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
 	__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
+	__RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
+	__RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
+	__RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
 	__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
+	__RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts),
+	__RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts),
+	__RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
+	__RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
+	__RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
+	__RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
+	__RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts),
+	__RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
+	__RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
+	__RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
@@ -190,6 +239,31 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 
 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
 
+static void __init match_isa_ext(const struct riscv_isa_ext_data *ext, const char *name,
+				 const char *name_end, struct riscv_isainfo *isainfo)
+{
+	if ((name_end - name == strlen(ext->name)) &&
+	     !strncasecmp(name, ext->name, name_end - name)) {
+		/*
+		 * If this is a bundle, enable all the ISA extensions that
+		 * comprise the bundle.
+		 */
+		if (ext->subset_ext_size) {
+			for (int i = 0; i < ext->subset_ext_size; i++) {
+				if (riscv_isa_extension_check(ext->subset_ext_ids[i]))
+					set_bit(ext->subset_ext_ids[i], isainfo->isa);
+			}
+		}
+
+		/*
+		 * This is valid even for bundle extensions which uses the RISCV_ISA_EXT_INVALID id
+		 * (rejected by riscv_isa_extension_check()).
+		 */
+		if (riscv_isa_extension_check(ext->id))
+			set_bit(ext->id, isainfo->isa);
+	}
+}
+
 static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct riscv_isainfo *isainfo,
 					  unsigned long *isa2hwcap, const char *isa)
 {
@@ -322,14 +396,6 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
 		if (*isa == '_')
 			++isa;
 
-#define SET_ISA_EXT_MAP(name, bit)						\
-		do {								\
-			if ((ext_end - ext == strlen(name)) &&			\
-			     !strncasecmp(ext, name, strlen(name)) &&		\
-			     riscv_isa_extension_check(bit))			\
-				set_bit(bit, isainfo->isa);			\
-		} while (false)							\
-
 		if (unlikely(ext_err))
 			continue;
 		if (!ext_long) {
@@ -341,10 +407,8 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
 			}
 		} else {
 			for (int i = 0; i < riscv_isa_ext_count; i++)
-				SET_ISA_EXT_MAP(riscv_isa_ext[i].name,
-						riscv_isa_ext[i].id);
+				match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
 		}
-#undef SET_ISA_EXT_MAP
 	}
 }
 
@@ -443,18 +507,26 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
 		}
 
 		for (int i = 0; i < riscv_isa_ext_count; i++) {
+			const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
+
 			if (of_property_match_string(cpu_node, "riscv,isa-extensions",
-						     riscv_isa_ext[i].property) < 0)
+						     ext->property) < 0)
 				continue;
 
-			if (!riscv_isa_extension_check(riscv_isa_ext[i].id))
-				continue;
+			if (ext->subset_ext_size) {
+				for (int j = 0; j < ext->subset_ext_size; j++) {
+					if (riscv_isa_extension_check(ext->subset_ext_ids[i]))
+						set_bit(ext->subset_ext_ids[j], isainfo->isa);
+				}
+			}
 
-			/* Only single letter extensions get set in hwcap */
-			if (strnlen(riscv_isa_ext[i].name, 2) == 1)
-				this_hwcap |= isa2hwcap[riscv_isa_ext[i].id];
+			if (riscv_isa_extension_check(ext->id)) {
+				set_bit(ext->id, isainfo->isa);
 
-			set_bit(riscv_isa_ext[i].id, isainfo->isa);
+				/* Only single letter extensions get set in hwcap */
+				if (strnlen(riscv_isa_ext[i].name, 2) == 1)
+					this_hwcap |= isa2hwcap[riscv_isa_ext[i].id];
+			}
 		}
 
 		of_node_put(cpu_node);
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 04/20] riscv: hwprobe: add support for scalar crypto ISA extensions
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (2 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 03/20] riscv: add ISA extension parsing for scalar crypto Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description Clément Léger
                   ` (17 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Export the following scalar crypto extensions through hwprobe:

- Zbkb
- Zbkc
- Zbkx
- Zknd
- Zkne
- Zknh
- Zksed
- Zksh
- Zkt

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 27 +++++++++++++++++++++++++++
 arch/riscv/include/uapi/asm/hwprobe.h |  9 +++++++++
 arch/riscv/kernel/sys_riscv.c         | 10 ++++++++++
 3 files changed, 46 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 3f71da935a65..3a18a31e32c3 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -83,6 +83,33 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
        in version 1.0 of the Bit-Manipulation ISA extensions.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as
+       defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as
+       defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as
+       defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as
+       defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as
+       defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as
+       defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as
+       defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as
+       defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
+       in version 1.0 of the Scalar Crypto ISA extensions.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index aca5abc7ebee..624abd5cde29 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -31,6 +31,15 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZBS		(1 << 5)
 #define		RISCV_HWPROBE_EXT_ZICBOZ	(1 << 6)
 #define		RISCV_HWPROBE_EXT_ZBC		(1 << 7)
+#define		RISCV_HWPROBE_EXT_ZBKB		(1 << 8)
+#define		RISCV_HWPROBE_EXT_ZBKC		(1 << 9)
+#define		RISCV_HWPROBE_EXT_ZBKX		(1 << 10)
+#define		RISCV_HWPROBE_EXT_ZKND		(1 << 11)
+#define		RISCV_HWPROBE_EXT_ZKNE		(1 << 12)
+#define		RISCV_HWPROBE_EXT_ZKNH		(1 << 13)
+#define		RISCV_HWPROBE_EXT_ZKSED		(1 << 14)
+#define		RISCV_HWPROBE_EXT_ZKSH		(1 << 15)
+#define		RISCV_HWPROBE_EXT_ZKT		(1 << 16)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 7a40145e9628..43aa66e71418 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -163,6 +163,16 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZBS);
 		EXT_KEY(ZICBOZ);
 		EXT_KEY(ZBC);
+
+		EXT_KEY(ZBKB);
+		EXT_KEY(ZBKC);
+		EXT_KEY(ZBKX);
+		EXT_KEY(ZKND);
+		EXT_KEY(ZKNE);
+		EXT_KEY(ZKNH);
+		EXT_KEY(ZKSED);
+		EXT_KEY(ZKSH);
+		EXT_KEY(ZKT);
 #undef EXT_KEY
 	}
 
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (3 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 04/20] riscv: hwprobe: add support for scalar crypto ISA extensions Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-22 16:13   ` Conor Dooley
  2023-11-14 14:12 ` [PATCH v4 06/20] riscv: add ISA extension parsing for vector crypto Clément Léger
                   ` (16 subsequent siblings)
  21 siblings, 1 reply; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Add description for scalar crypto ISA extensions:

- Zbkb
- Zbkc
- Zbkx
- Zknd
- Zkne
- Zknh
- Zkr
- Zksed
- Zksh
- Zkt

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 .../devicetree/bindings/riscv/extensions.yaml | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index c91ab0e46648..a3803b22cf4f 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -190,12 +190,92 @@ properties:
             multiplication as ratified at commit 6d33919 ("Merge pull request
             #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
 
+        - const: zbkb
+          description:
+            The standard Zbkb bitmanip instructions for cryptography as ratified
+            in version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
+        - const: zbkc
+          description:
+            The standard Zbkc carry-less multiply instructions as ratified
+            in version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
+        - const: zbkx
+          description:
+            The standard Zbkx crossbar permutation instructions as ratified
+            in version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
         - const: zbs
           description: |
             The standard Zbs bit-manipulation extension for single-bit
             instructions as ratified at commit 6d33919 ("Merge pull request #158
             from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
 
+        - const: zk
+          description:
+            The standard Zk Standard Scalar cryptography extension as ratified
+            in version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
+        - const: zkn
+          description:
+            The standard Zkn NIST algorithm suite extensions as ratified in
+            version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
+        - const: zknd
+          description: |
+            The standard Zknd for NIST suite: AES decryption instructions as
+            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
+        - const: zkne
+          description: |
+            The standard Zkne for NIST suite: AES encryption instructions as
+            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
+        - const: zknh
+          description: |
+            The standard Zknh for NIST suite: hash function instructions as
+            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
+        - const: zkr
+          description:
+            The standard Zkr entropy source extension as ratified in version
+            1.0 of RISC-V Cryptography Extensions Volume I specification.
+            This string being present means that the CSR associated to this
+            extension is accessible at the privilege level to which that
+            device-tree has been provided.
+
+        - const: zks
+          description:
+            The standard Zks ShangMi algorithm suite extensions as ratified in
+            version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
+        - const: zksed
+          description: |
+            The standard Zksed for ShangMi suite: SM4 block cipher instructions
+            as ratified in version 1.0 of RISC-V Cryptography Extensions
+            Volume I specification.
+
+        - const: zksh
+          description: |
+            The standard Zksh for ShangMi suite: SM3 hash function instructions
+            as ratified in version 1.0 of RISC-V Cryptography Extensions
+            Volume I specification.
+
+        - const: zkt
+          description:
+            The standard Zkt for data independent execution latency as ratified
+            in version 1.0 of RISC-V Cryptography Extensions Volume I
+            specification.
+
         - const: zicbom
           description:
             The standard Zicbom extension for base cache management operations as
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* Re: [PATCH v4 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description
  2023-11-14 14:12 ` [PATCH v4 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description Clément Léger
@ 2023-11-22 16:13   ` Conor Dooley
  0 siblings, 0 replies; 24+ messages in thread
From: Conor Dooley @ 2023-11-22 16:13 UTC (permalink / raw)
  To: Clément Léger
  Cc: linux-riscv, devicetree, linux-kernel, linux-doc, Palmer Dabbelt,
	Paul Walmsley, Rob Herring, Krzysztof Kozlowski, Albert Ou,
	Jonathan Corbet, Andrew Jones, Evan Green, Samuel Ortiz,
	Jerry Shih

[-- Attachment #1: Type: text/plain, Size: 355 bytes --]

On Tue, Nov 14, 2023 at 09:12:41AM -0500, Clément Léger wrote:
> Add description for scalar crypto ISA extensions:
> 
> - Zbkb
> - Zbkc
> - Zbkx
> - Zknd
> - Zkne
> - Zknh
> - Zkr
> - Zksed
> - Zksh
> - Zkt
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [PATCH v4 06/20] riscv: add ISA extension parsing for vector crypto
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (4 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 07/20] riscv: hwprobe: export vector crypto ISA extensions Clément Léger
                   ` (15 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Add parsing of some Zv* vector crypto ISA extensions that are mentioned
in "RISC-V Cryptography Extensions Volume II" [1]. These ISA extensions
are the following:

- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvkn: NIST Algorithm Suite
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvks: ShangMi Algorithm Suite
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.

Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 12 ++++++-
 arch/riscv/kernel/cpufeature.c | 64 ++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b0857c64bf6e..477254668d82 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -68,8 +68,18 @@
 #define RISCV_ISA_EXT_ZKSED		53
 #define RISCV_ISA_EXT_ZKSH		54
 #define RISCV_ISA_EXT_ZKT		55
+#define RISCV_ISA_EXT_ZVBB		56
+#define RISCV_ISA_EXT_ZVBC		57
+#define RISCV_ISA_EXT_ZVKB		58
+#define RISCV_ISA_EXT_ZVKG		59
+#define RISCV_ISA_EXT_ZVKNED		60
+#define RISCV_ISA_EXT_ZVKNHA		61
+#define RISCV_ISA_EXT_ZVKNHB		62
+#define RISCV_ISA_EXT_ZVKSED		63
+#define RISCV_ISA_EXT_ZVKSH		64
+#define RISCV_ISA_EXT_ZVKT		65
 
-#define RISCV_ISA_EXT_MAX		64
+#define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
 
 #ifdef CONFIG_RISCV_M_MODE
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a2871bceaad9..c4d0f16c29b9 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -123,6 +123,10 @@ static bool riscv_isa_extension_check(int id)
 #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \
 	_RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts))
 
+/* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
+#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \
+	_RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts))
+
 static const unsigned int riscv_zk_bundled_exts[] = {
 	RISCV_ISA_EXT_ZBKB,
 	RISCV_ISA_EXT_ZBKC,
@@ -149,6 +153,50 @@ static const unsigned int riscv_zks_bundled_exts[] = {
 	RISCV_ISA_EXT_ZKSH
 };
 
+#define RISCV_ISA_EXT_ZVKN	\
+	RISCV_ISA_EXT_ZVKNED,	\
+	RISCV_ISA_EXT_ZVKNHB,	\
+	RISCV_ISA_EXT_ZVKB,	\
+	RISCV_ISA_EXT_ZVKT
+
+static const unsigned int riscv_zvkn_bundled_exts[] = {
+	RISCV_ISA_EXT_ZVKN
+};
+
+static const unsigned int riscv_zvknc_bundled_exts[] = {
+	RISCV_ISA_EXT_ZVKN,
+	RISCV_ISA_EXT_ZVBC
+};
+
+static const unsigned int riscv_zvkng_bundled_exts[] = {
+	RISCV_ISA_EXT_ZVKN,
+	RISCV_ISA_EXT_ZVKG
+};
+
+#define RISCV_ISA_EXT_ZVKS	\
+	RISCV_ISA_EXT_ZVKSED,	\
+	RISCV_ISA_EXT_ZVKSH,	\
+	RISCV_ISA_EXT_ZVKB,	\
+	RISCV_ISA_EXT_ZVKT
+
+static const unsigned int riscv_zvks_bundled_exts[] = {
+	RISCV_ISA_EXT_ZVKS
+};
+
+static const unsigned int riscv_zvksc_bundled_exts[] = {
+	RISCV_ISA_EXT_ZVKS,
+	RISCV_ISA_EXT_ZVBC
+};
+
+static const unsigned int riscv_zvksg_bundled_exts[] = {
+	RISCV_ISA_EXT_ZVKS,
+	RISCV_ISA_EXT_ZVKG
+};
+
+static const unsigned int riscv_zvbb_exts[] = {
+	RISCV_ISA_EXT_ZVKB
+};
+
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
  * chapter 27 of the unprivileged specification.
@@ -227,6 +275,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
 	__RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
 	__RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
+	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
+	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
+	__RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
+	__RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
+	__RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts),
+	__RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
+	__RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts),
+	__RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
+	__RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
+	__RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts),
+	__RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts),
+	__RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
+	__RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
+	__RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
+	__RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 07/20] riscv: hwprobe: export vector crypto ISA extensions
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (5 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 06/20] riscv: add ISA extension parsing for vector crypto Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 08/20] dt-bindings: riscv: add vector crypto ISA extensions description Clément Léger
                   ` (14 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Export Zv* vector crypto ISA extensions that were added in "RISC-V
Cryptography Extensions Volume II" specification[1] through hwprobe.
This adds support for the following instructions:

- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.

Zvkn and Zvks are ommited since they are a superset of other extensions.

Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 30 +++++++++++++++++++++++++++
 arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++++++
 arch/riscv/kernel/sys_riscv.c         | 13 ++++++++++++
 3 files changed, 53 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 3a18a31e32c3..a08fcd899b6d 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -110,6 +110,36 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
        in version 1.0 of the Scalar Crypto ISA extensions.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
+       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 624abd5cde29..89628a76ca04 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -40,6 +40,16 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZKSED		(1 << 14)
 #define		RISCV_HWPROBE_EXT_ZKSH		(1 << 15)
 #define		RISCV_HWPROBE_EXT_ZKT		(1 << 16)
+#define		RISCV_HWPROBE_EXT_ZVBB		(1 << 17)
+#define		RISCV_HWPROBE_EXT_ZVBC		(1 << 18)
+#define		RISCV_HWPROBE_EXT_ZVKB		(1 << 19)
+#define		RISCV_HWPROBE_EXT_ZVKG		(1 << 20)
+#define		RISCV_HWPROBE_EXT_ZVKNED	(1 << 21)
+#define		RISCV_HWPROBE_EXT_ZVKNHA	(1 << 22)
+#define		RISCV_HWPROBE_EXT_ZVKNHB	(1 << 23)
+#define		RISCV_HWPROBE_EXT_ZVKSED	(1 << 24)
+#define		RISCV_HWPROBE_EXT_ZVKSH		(1 << 25)
+#define		RISCV_HWPROBE_EXT_ZVKT		(1 << 26)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 43aa66e71418..9bbcd7334d96 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -173,6 +173,19 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZKSED);
 		EXT_KEY(ZKSH);
 		EXT_KEY(ZKT);
+
+		if (has_vector()) {
+			EXT_KEY(ZVBB);
+			EXT_KEY(ZVBC);
+			EXT_KEY(ZVKB);
+			EXT_KEY(ZVKG);
+			EXT_KEY(ZVKNED);
+			EXT_KEY(ZVKNHA);
+			EXT_KEY(ZVKNHB);
+			EXT_KEY(ZVKSED);
+			EXT_KEY(ZVKSH);
+			EXT_KEY(ZVKT);
+		}
 #undef EXT_KEY
 	}
 
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 08/20] dt-bindings: riscv: add vector crypto ISA extensions description
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (6 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 07/20] riscv: hwprobe: export vector crypto ISA extensions Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 09/20] riscv: add ISA extension parsing for Zfh/Zfh[min] Clément Léger
                   ` (13 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih,
	Conor Dooley

Add Zv* vector crypto extensions that were added in "RISC-V Cryptography
Extensions Volume II" specificationi[1]:

- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvkn: NIST Algorithm Suite
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvks: ShangMi Algorithm Suite
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.

Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/riscv/extensions.yaml | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index a3803b22cf4f..e845e461b6e1 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -338,5 +338,101 @@ properties:
             in commit 2e5236 ("Ztso is now ratified.") of the
             riscv-isa-manual.
 
+        - const: zvbb
+          description:
+            The standard Zvbb extension for vectored basic bit-manipulation
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvbc
+          description:
+            The standard Zvbc extension for vectored carryless multiplication
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvkb
+          description:
+            The standard Zvkb extension for vector cryptography bit-manipulation
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvkg
+          description:
+            The standard Zvkg extension for vector GCM/GMAC instructions, as
+            ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
+            of riscv-crypto.
+
+        - const: zvkn
+          description:
+            The standard Zvkn extension for NIST algorithm suite instructions, as
+            ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
+            of riscv-crypto.
+
+        - const: zvknc
+          description:
+            The standard Zvknc extension for NIST algorithm suite with carryless
+            multiply instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvkned
+          description:
+            The standard Zvkned extension for Vector AES block cipher
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvkng
+          description:
+            The standard Zvkng extension for NIST algorithm suite with GCM
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvknha
+          description: |
+            The standard Zvknha extension for NIST suite: vector SHA-2 secure,
+            hash (SHA-256 only) instructions, as ratified in commit
+            56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvknhb
+          description: |
+            The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
+            hash (SHA-256 and SHA-512) instructions, as ratified in commit
+            56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvks
+          description:
+            The standard Zvks extension for ShangMi algorithm suite
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvksc
+          description:
+            The standard Zvksc extension for ShangMi algorithm suite with
+            carryless multiplication instructions, as ratified in commit 56ed795
+            ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvksed
+          description: |
+            The standard Zvksed extension for ShangMi suite: SM4 block cipher
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvksh
+          description: |
+            The standard Zvksh extension for ShangMi suite: SM3 secure hash
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvksg
+          description:
+            The standard Zvksg extension for ShangMi algorithm suite with GCM
+            instructions, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+        - const: zvkt
+          description:
+            The standard Zvkt extension for vector data-independent execution
+            latency, as ratified in commit 56ed795 ("Update
+            riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
 additionalProperties: true
 ...
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 09/20] riscv: add ISA extension parsing for Zfh/Zfh[min]
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (7 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 08/20] dt-bindings: riscv: add vector crypto ISA extensions description Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 10/20] riscv: hwprobe: export Zfh[min] ISA extensions Clément Léger
                   ` (12 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Add parsing for Zfh[min] ISA extensions[1].

Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 2 ++
 arch/riscv/kernel/cpufeature.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 477254668d82..6a6ee93a3c9a 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -78,6 +78,8 @@
 #define RISCV_ISA_EXT_ZVKSED		63
 #define RISCV_ISA_EXT_ZVKSH		64
 #define RISCV_ISA_EXT_ZVKT		65
+#define RISCV_ISA_EXT_ZFH		66
+#define RISCV_ISA_EXT_ZFHMIN		67
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c4d0f16c29b9..7182cf278b1c 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -258,6 +258,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
+	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
+	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
 	__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 10/20] riscv: hwprobe: export Zfh[min] ISA extensions
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (8 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 09/20] riscv: add ISA extension parsing for Zfh/Zfh[min] Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description Clément Léger
                   ` (11 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Export Zfh[min] ISA extensions[1] through hwprobe only if FPU support
is available.

Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 6 ++++++
 arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
 arch/riscv/kernel/sys_riscv.c         | 5 +++++
 3 files changed, 13 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index a08fcd899b6d..397d53195f49 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -140,6 +140,12 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
        defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
+       as defined in the RISC-V ISA manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
+       supported as defined in the RISC-V ISA manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 89628a76ca04..2d960777ea43 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -50,6 +50,8 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZVKSED	(1 << 24)
 #define		RISCV_HWPROBE_EXT_ZVKSH		(1 << 25)
 #define		RISCV_HWPROBE_EXT_ZVKT		(1 << 26)
+#define		RISCV_HWPROBE_EXT_ZFH		(1 << 27)
+#define		RISCV_HWPROBE_EXT_ZFHMIN	(1 << 28)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 9bbcd7334d96..d776c6c39fcd 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -186,6 +186,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 			EXT_KEY(ZVKSH);
 			EXT_KEY(ZVKT);
 		}
+
+		if (has_fpu()) {
+			EXT_KEY(ZFH);
+			EXT_KEY(ZFHMIN);
+		}
 #undef EXT_KEY
 	}
 
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (9 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 10/20] riscv: hwprobe: export Zfh[min] ISA extensions Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 12/20] riscv: add ISA extension parsing for Zihintntl Clément Léger
                   ` (10 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih,
	Conor Dooley

Add description of Zfh[min] ISA extensions[1].

Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/riscv/extensions.yaml       | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index e845e461b6e1..f3c99e69619b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -214,6 +214,19 @@ properties:
             instructions as ratified at commit 6d33919 ("Merge pull request #158
             from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
 
+        - const: zfh
+          description:
+            The standard Zfh extension for 16-bit half-precision binary
+            floating-point instructions, as ratified in commit 64074bc ("Update
+            version numbers for Zfh/Zfinx") of riscv-isa-manual.
+
+        - const: zfhmin
+          description:
+            The standard Zfhmin extension which provides minimal support for
+            16-bit half-precision binary floating-point instructions, as ratified
+            in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
+            riscv-isa-manual.
+
         - const: zk
           description:
             The standard Zk Standard Scalar cryptography extension as ratified
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 12/20] riscv: add ISA extension parsing for Zihintntl
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (10 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 13/20] riscv: hwprobe: export Zhintntl ISA extension Clément Léger
                   ` (9 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Add parsing for Zihintntl ISA extension[1] that was ratified in commit
0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2].

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d [2]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 6a6ee93a3c9a..97d106fa0f54 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -80,6 +80,7 @@
 #define RISCV_ISA_EXT_ZVKT		65
 #define RISCV_ISA_EXT_ZFH		66
 #define RISCV_ISA_EXT_ZFHMIN		67
+#define RISCV_ISA_EXT_ZIHINTNTL		68
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 7182cf278b1c..e73ee4cfd84a 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -256,6 +256,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
 	__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
 	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
+	__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
 	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 13/20] riscv: hwprobe: export Zhintntl ISA extension
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (11 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 12/20] riscv: add ISA extension parsing for Zihintntl Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 14/20] dt-bindings: riscv: add Zihintntl ISA extension description Clément Léger
                   ` (8 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Export Zihintntl extension[1] through hwprobe.

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 3 +++
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_riscv.c         | 1 +
 3 files changed, 5 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 397d53195f49..aa8ebeeddfe6 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -146,6 +146,9 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
        supported as defined in the RISC-V ISA manual.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
+       is supported as defined in the RISC-V ISA manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 2d960777ea43..d72c69ea0740 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -52,6 +52,7 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZVKT		(1 << 26)
 #define		RISCV_HWPROBE_EXT_ZFH		(1 << 27)
 #define		RISCV_HWPROBE_EXT_ZFHMIN	(1 << 28)
+#define		RISCV_HWPROBE_EXT_ZIHINTNTL	(1 << 29)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index d776c6c39fcd..a46e4f6821dd 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -173,6 +173,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZKSED);
 		EXT_KEY(ZKSH);
 		EXT_KEY(ZKT);
+		EXT_KEY(ZIHINTNTL);
 
 		if (has_vector()) {
 			EXT_KEY(ZVBB);
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 14/20] dt-bindings: riscv: add Zihintntl ISA extension description
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (12 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 13/20] riscv: hwprobe: export Zhintntl ISA extension Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 15/20] riscv: add ISA extension parsing for Zvfh[min] Clément Léger
                   ` (7 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih,
	Conor Dooley

Add description for Zihintntl ISA extension[1].

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index f3c99e69619b..f953c49be90d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -339,6 +339,12 @@ properties:
             The standard Zihintpause extension for pause hints, as ratified in
             commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
 
+        - const: zihintntl
+          description:
+            The standard Zihintntl extension for non-temporal locality hints, as
+            ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
+            riscv-isa-manual.
+
         - const: zihpm
           description:
             The standard Zihpm extension for hardware performance counters, as
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 15/20] riscv: add ISA extension parsing for Zvfh[min]
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (13 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 14/20] dt-bindings: riscv: add Zihintntl ISA extension description Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 16/20] riscv: hwprobe: export Zvfh[min] ISA extensions Clément Léger
                   ` (6 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Add parsing for Zvfh[min] ISA extension[1] which were ratified in
june 2023 around commit e2ccd0548d6c ("Remove draft warnings from
Zvfh[min]") in riscv-v-spec[2].

Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1]
Link: https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c [2]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 2 ++
 arch/riscv/kernel/cpufeature.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 97d106fa0f54..103d4f0aaf15 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -81,6 +81,8 @@
 #define RISCV_ISA_EXT_ZFH		66
 #define RISCV_ISA_EXT_ZFHMIN		67
 #define RISCV_ISA_EXT_ZIHINTNTL		68
+#define RISCV_ISA_EXT_ZVFH		69
+#define RISCV_ISA_EXT_ZVFHMIN		70
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index e73ee4cfd84a..623a5fa48cf4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -280,6 +280,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
 	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
 	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
+	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
 	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
 	__RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
 	__RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 16/20] riscv: hwprobe: export Zvfh[min] ISA extensions
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (14 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 15/20] riscv: add ISA extension parsing for Zvfh[min] Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description Clément Léger
                   ` (5 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Export Zvfh[min] ISA extension[1] through hwprobe.

Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 8 ++++++++
 arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
 arch/riscv/kernel/sys_riscv.c         | 2 ++
 3 files changed, 12 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index aa8ebeeddfe6..896ecfbbe5f4 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -149,6 +149,14 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
        is supported as defined in the RISC-V ISA manual.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
+       defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
+       ("Remove draft warnings from Zvfh[min]").
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
+       defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
+       ("Remove draft warnings from Zvfh[min]").
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index d72c69ea0740..fffc69d9f6ba 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -53,6 +53,8 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZFH		(1 << 27)
 #define		RISCV_HWPROBE_EXT_ZFHMIN	(1 << 28)
 #define		RISCV_HWPROBE_EXT_ZIHINTNTL	(1 << 29)
+#define		RISCV_HWPROBE_EXT_ZVFH		(1 << 30)
+#define		RISCV_HWPROBE_EXT_ZVFHMIN	(1 << 31)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index a46e4f6821dd..e90537593f5f 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -186,6 +186,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 			EXT_KEY(ZVKSED);
 			EXT_KEY(ZVKSH);
 			EXT_KEY(ZVKT);
+			EXT_KEY(ZVFH);
+			EXT_KEY(ZVFHMIN);
 		}
 
 		if (has_fpu()) {
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (15 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 16/20] riscv: hwprobe: export Zvfh[min] ISA extensions Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 18/20] riscv: add ISA extension parsing for Zfa Clément Léger
                   ` (4 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih,
	Conor Dooley

Add description for Zvfh[min] ISA extension[1].

Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/riscv/extensions.yaml        | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index f953c49be90d..b91d49b7c3a0 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -369,6 +369,18 @@ properties:
             instructions, as ratified in commit 56ed795 ("Update
             riscv-crypto-spec-vector.adoc") of riscv-crypto.
 
+        - const: zvfh
+          description:
+            The standard Zvfh extension for vectored half-precision
+            floating-point instructions, as ratified in commit e2ccd05
+            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
+        - const: zvfhmin
+          description:
+            The standard Zvfhmin extension for vectored minimal half-precision
+            floating-point instructions, as ratified in commit e2ccd05
+            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
         - const: zvkb
           description:
             The standard Zvkb extension for vector cryptography bit-manipulation
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 18/20] riscv: add ISA extension parsing for Zfa
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (16 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 19/20] riscv: hwprobe: export Zfa ISA extension Clément Léger
                   ` (3 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Add parsing for Zfa ISA extension [1] which were ratified in commit
056b6ff467c7 ("Zfa is ratified") of riscv-isa-manual[2].

Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1]
Link: https://github.com/riscv/riscv-isa-manual/commits/056b6ff467c7 [2]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 103d4f0aaf15..2438d4685da6 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -83,6 +83,7 @@
 #define RISCV_ISA_EXT_ZIHINTNTL		68
 #define RISCV_ISA_EXT_ZVFH		69
 #define RISCV_ISA_EXT_ZVFHMIN		70
+#define RISCV_ISA_EXT_ZFA		71
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 623a5fa48cf4..dc0ab3e97cd2 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -259,6 +259,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
+	__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
 	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
 	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 19/20] riscv: hwprobe: export Zfa ISA extension
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (17 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 18/20] riscv: add ISA extension parsing for Zfa Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-14 14:12 ` [PATCH v4 20/20] dt-bindings: riscv: add Zfa ISA extension description Clément Léger
                   ` (2 subsequent siblings)
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih

Export Zfa ISA extension[1] through hwprobe.

Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 4 ++++
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_riscv.c         | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 896ecfbbe5f4..41463b932268 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -157,6 +157,10 @@ The following keys are defined:
        defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
        ("Remove draft warnings from Zvfh[min]").
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as
+       defined in the RISC-V ISA manual starting from commit 056b6ff467c7
+       ("Zfa is ratified").
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index fffc69d9f6ba..91fbe1a7f2e2 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -55,6 +55,7 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZIHINTNTL	(1 << 29)
 #define		RISCV_HWPROBE_EXT_ZVFH		(1 << 30)
 #define		RISCV_HWPROBE_EXT_ZVFHMIN	(1 << 31)
+#define		RISCV_HWPROBE_EXT_ZFA		(1ULL << 32)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index e90537593f5f..f0bd7b480b7f 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -193,6 +193,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		if (has_fpu()) {
 			EXT_KEY(ZFH);
 			EXT_KEY(ZFHMIN);
+			EXT_KEY(ZFA);
 		}
 #undef EXT_KEY
 	}
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [PATCH v4 20/20] dt-bindings: riscv: add Zfa ISA extension description
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (18 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 19/20] riscv: hwprobe: export Zfa ISA extension Clément Léger
@ 2023-11-14 14:12 ` Clément Léger
  2023-11-22 16:16 ` [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Conor Dooley
  2023-12-12 22:20 ` patchwork-bot+linux-riscv
  21 siblings, 0 replies; 24+ messages in thread
From: Clément Léger @ 2023-11-14 14:12 UTC (permalink / raw)
  To: linux-riscv, devicetree, linux-kernel, linux-doc
  Cc: Clément Léger, Palmer Dabbelt, Paul Walmsley,
	Rob Herring, Krzysztof Kozlowski, Albert Ou, Jonathan Corbet,
	Andrew Jones, Evan Green, Conor Dooley, Samuel Ortiz, Jerry Shih,
	Conor Dooley

Add description for the Zfa ISA extension[1].

Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index b91d49b7c3a0..3574a0b70be4 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -214,6 +214,12 @@ properties:
             instructions as ratified at commit 6d33919 ("Merge pull request #158
             from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
 
+        - const: zfa
+          description:
+            The standard Zfa extension for additional floating point
+            instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
+            riscv-isa-manual.
+
         - const: zfh
           description:
             The standard Zfh extension for 16-bit half-precision binary
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 24+ messages in thread

* Re: [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (19 preceding siblings ...)
  2023-11-14 14:12 ` [PATCH v4 20/20] dt-bindings: riscv: add Zfa ISA extension description Clément Léger
@ 2023-11-22 16:16 ` Conor Dooley
  2023-12-12 22:20 ` patchwork-bot+linux-riscv
  21 siblings, 0 replies; 24+ messages in thread
From: Conor Dooley @ 2023-11-22 16:16 UTC (permalink / raw)
  To: Clément Léger
  Cc: linux-riscv, devicetree, linux-kernel, linux-doc, Palmer Dabbelt,
	Paul Walmsley, Rob Herring, Krzysztof Kozlowski, Albert Ou,
	Jonathan Corbet, Andrew Jones, Evan Green, Samuel Ortiz,
	Jerry Shih

[-- Attachment #1: Type: text/plain, Size: 404 bytes --]

On Tue, Nov 14, 2023 at 09:12:36AM -0500, Clément Léger wrote:
> Changes in V4:
>  - Add a text specifying that Zkr string dt binding means that the CSR
>    provided by Zkr are accessible only by the privilege level to which
> the device-tree has been provided.

This text don't match what the change was. Here you say "only", but the
binding has the IMO correct wording, with "only" removed.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 24+ messages in thread

* Re: [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe
  2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
                   ` (20 preceding siblings ...)
  2023-11-22 16:16 ` [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Conor Dooley
@ 2023-12-12 22:20 ` patchwork-bot+linux-riscv
  21 siblings, 0 replies; 24+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-12-12 22:20 UTC (permalink / raw)
  To: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2VyIDxjbGVnZXJAcml2b3NpbmMuY29tPg==?=
  Cc: linux-riscv, devicetree, linux-kernel, linux-doc, palmer,
	paul.walmsley, robh+dt, krzysztof.kozlowski+dt, aou, corbet,
	ajones, evan, conor, sameo, jerry.shih

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Tue, 14 Nov 2023 09:12:36 -0500 you wrote:
> In order to be able to gather more information about the supported ISA
> extensions from userspace using the hwprobe syscall, add more ISA
> extensions report. This series adds the following ISA extensions parsing
> support:
> 
> - Zfh[min]
> - Zvfh[min]
> - Zihintntl
> - Zbc
> - Zvbb
> - Zvbc
> - Zvkb
> - Zvkg
> - Zvkned
> - Zvknh[ab]
> - Zvksed
> - Zvksh
> - Zvkn
> - Zvknc
> - Zvkng
> - Zvks
> - Zvksc
> - Zvksg
> - Zvkt
> - Zfa
> - Zbkb
> - Zbkc
> - Zbkx
> - Zknd
> - Zkne
> - Zknh
> - Zkr
> - Zksed
> - Zksh
> - Zkt
> 
> [...]

Here is the summary with links:
  - [v4,01/20] riscv: add ISA extension parsing for Zbc
    https://git.kernel.org/riscv/c/88e752f0986f
  - [v4,02/20] riscv: hwprobe: export missing Zbc ISA extension
    https://git.kernel.org/riscv/c/2ae2b9097b2e
  - [v4,03/20] riscv: add ISA extension parsing for scalar crypto
    https://git.kernel.org/riscv/c/5ee88a915d4b
  - [v4,04/20] riscv: hwprobe: add support for scalar crypto ISA extensions
    https://git.kernel.org/riscv/c/18883cef7e64
  - [v4,05/20] dt-bindings: riscv: add scalar crypto ISA extensions description
    https://git.kernel.org/riscv/c/ffd19e815367
  - [v4,06/20] riscv: add ISA extension parsing for vector crypto
    https://git.kernel.org/riscv/c/4fa9e167b63b
  - [v4,07/20] riscv: hwprobe: export vector crypto ISA extensions
    https://git.kernel.org/riscv/c/d06b89615a9e
  - [v4,08/20] dt-bindings: riscv: add vector crypto ISA extensions description
    https://git.kernel.org/riscv/c/eb8c82b7a8c4
  - [v4,09/20] riscv: add ISA extension parsing for Zfh/Zfh[min]
    https://git.kernel.org/riscv/c/68bddb2748ac
  - [v4,10/20] riscv: hwprobe: export Zfh[min] ISA extensions
    https://git.kernel.org/riscv/c/5cb9bea00d12
  - [v4,11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description
    https://git.kernel.org/riscv/c/6853ab83405c
  - [v4,12/20] riscv: add ISA extension parsing for Zihintntl
    https://git.kernel.org/riscv/c/8ab84bf68d2b
  - [v4,13/20] riscv: hwprobe: export Zhintntl ISA extension
    https://git.kernel.org/riscv/c/814d9823088a
  - [v4,14/20] dt-bindings: riscv: add Zihintntl ISA extension description
    https://git.kernel.org/riscv/c/4bd2e33d1613
  - [v4,15/20] riscv: add ISA extension parsing for Zvfh[min]
    https://git.kernel.org/riscv/c/c7fa1ef17e6f
  - [v4,16/20] riscv: hwprobe: export Zvfh[min] ISA extensions
    https://git.kernel.org/riscv/c/9a42ab69b658
  - [v4,17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description
    https://git.kernel.org/riscv/c/1f532a7d898e
  - [v4,18/20] riscv: add ISA extension parsing for Zfa
    https://git.kernel.org/riscv/c/4758aec519ae
  - [v4,19/20] riscv: hwprobe: export Zfa ISA extension
    https://git.kernel.org/riscv/c/f838a77a4881
  - [v4,20/20] dt-bindings: riscv: add Zfa ISA extension description
    https://git.kernel.org/riscv/c/e810a257576f

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



^ permalink raw reply	[flat|nested] 24+ messages in thread

end of thread, other threads:[~2023-12-12 22:20 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-14 14:12 [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Clément Léger
2023-11-14 14:12 ` [PATCH v4 01/20] riscv: add ISA extension parsing for Zbc Clément Léger
2023-11-14 14:12 ` [PATCH v4 02/20] riscv: hwprobe: export missing Zbc ISA extension Clément Léger
2023-11-14 14:12 ` [PATCH v4 03/20] riscv: add ISA extension parsing for scalar crypto Clément Léger
2023-11-14 14:12 ` [PATCH v4 04/20] riscv: hwprobe: add support for scalar crypto ISA extensions Clément Léger
2023-11-14 14:12 ` [PATCH v4 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description Clément Léger
2023-11-22 16:13   ` Conor Dooley
2023-11-14 14:12 ` [PATCH v4 06/20] riscv: add ISA extension parsing for vector crypto Clément Léger
2023-11-14 14:12 ` [PATCH v4 07/20] riscv: hwprobe: export vector crypto ISA extensions Clément Léger
2023-11-14 14:12 ` [PATCH v4 08/20] dt-bindings: riscv: add vector crypto ISA extensions description Clément Léger
2023-11-14 14:12 ` [PATCH v4 09/20] riscv: add ISA extension parsing for Zfh/Zfh[min] Clément Léger
2023-11-14 14:12 ` [PATCH v4 10/20] riscv: hwprobe: export Zfh[min] ISA extensions Clément Léger
2023-11-14 14:12 ` [PATCH v4 11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description Clément Léger
2023-11-14 14:12 ` [PATCH v4 12/20] riscv: add ISA extension parsing for Zihintntl Clément Léger
2023-11-14 14:12 ` [PATCH v4 13/20] riscv: hwprobe: export Zhintntl ISA extension Clément Léger
2023-11-14 14:12 ` [PATCH v4 14/20] dt-bindings: riscv: add Zihintntl ISA extension description Clément Léger
2023-11-14 14:12 ` [PATCH v4 15/20] riscv: add ISA extension parsing for Zvfh[min] Clément Léger
2023-11-14 14:12 ` [PATCH v4 16/20] riscv: hwprobe: export Zvfh[min] ISA extensions Clément Léger
2023-11-14 14:12 ` [PATCH v4 17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description Clément Léger
2023-11-14 14:12 ` [PATCH v4 18/20] riscv: add ISA extension parsing for Zfa Clément Léger
2023-11-14 14:12 ` [PATCH v4 19/20] riscv: hwprobe: export Zfa ISA extension Clément Léger
2023-11-14 14:12 ` [PATCH v4 20/20] dt-bindings: riscv: add Zfa ISA extension description Clément Léger
2023-11-22 16:16 ` [PATCH v4 00/20] riscv: report more ISA extensions through hwprobe Conor Dooley
2023-12-12 22:20 ` patchwork-bot+linux-riscv

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