From: Qiang Yu <quic_qianyu@quicinc.com>
To: andersson@kernel.org, konrad.dybcio@linaro.org,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_cang@quicinc.com,
quic_mrana@quicinc.com, quic_qianyu@quicinc.com
Subject: [PATCH v2] arm64: dts: qcom: sm8550: Increase supported MSI interrupts.
Date: Wed, 27 Dec 2023 11:34:56 +0800 [thread overview]
Message-ID: <1703648096-46067-1-git-send-email-quic_qianyu@quicinc.com> (raw)
On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence,
enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1.
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
---
v1->v2: make interrupt-names one per line
arch/arm64/boot/dts/qcom/sm8550.dtsi | 36 ++++++++++++++++++++++++++++++++----
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ee1ba5a..3f413cb 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1713,8 +1713,22 @@
linux,pci-domain = <0>;
num-lanes = <2>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1804,8 +1818,22 @@
linux,pci-domain = <1>;
num-lanes = <2>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
--
2.7.4
next reply other threads:[~2023-12-27 3:35 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-27 3:34 Qiang Yu [this message]
2024-01-03 13:48 ` [PATCH v2] arm64: dts: qcom: sm8550: Increase supported MSI interrupts Konrad Dybcio
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