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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acaa1cb4204sm133546366b.116.2025.04.09.11.39.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Apr 2025 11:39:06 -0700 (PDT) Message-ID: <170e4c9a-bdf4-44f7-9dd1-9eed31fa27db@oss.qualcomm.com> Date: Wed, 9 Apr 2025 20:39:05 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node To: Loic Poulain , Bryan O'Donoghue Cc: andersson@kernel.org, konradybcio@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, robh@kernel.org References: <20250403102256.101217-1-loic.poulain@oss.qualcomm.com> <0YH8BNtmMcywwRXI3xHiLyB_zFED-XbjzCyyI1Vc4184BPadVJ-GWj23lpEwaXEHqDPiMiraMsWlOd1qA_hiog==@protonmail.internalid> <20250403102256.101217-2-loic.poulain@oss.qualcomm.com> <1b649ead-f6d6-4fb0-b5ac-02cf2dba92ca@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: N1TDE91zNJyUv1Nv2QdjbV0c00mGJhco X-Authority-Analysis: v=2.4 cv=KtdN2XWN c=1 sm=1 tr=0 ts=67f6becc cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=DQTqHzjkEM4X2CI68noA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: N1TDE91zNJyUv1Nv2QdjbV0c00mGJhco X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-09_06,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504090122 On 4/7/25 4:56 PM, Loic Poulain wrote: > Hi Bryan, > > > On Fri, Apr 4, 2025 at 2:10 PM Bryan O'Donoghue > wrote: >> >> On 03/04/2025 11:22, Loic Poulain wrote: >>> Add Camera Control Interface (CCI), supporting two I2C masters. >>> >>> Signed-off-by: Loic Poulain >>> --- >>> v2: Reorder commits; Update dts properties order and style >>> v3: No change for this patch >>> >>> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++ >>> 1 file changed, 50 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi >>> index 7fb5de92bc4c..43fcb4f40a8c 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi >>> @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state { >>> bias-disable; >>> }; >>> >>> + cci0_default: cci0-default-state { >>> + pins = "gpio22", "gpio23"; >>> + function = "cci_i2c"; >>> + drive-strength = <2>; >>> + bias-disable; >>> + }; >>> + >>> + cci1_default: cci1-default-state { >>> + pins = "gpio29", "gpio30"; >>> + function = "cci_i2c"; >>> + drive-strength = <2>; >>> + bias-disable; >>> + }; >>> + >>> sdc1_state_on: sdc1-on-state { >>> clk-pins { >>> pins = "sdc1_clk"; >>> @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 { >>> #iommu-cells = <2>; >>> }; >>> >>> + cci: cci@5c1b000 { >>> + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; >>> + reg = <0x0 0x5c1b000 0x0 0x1000>; >>> + >>> + interrupts = ; >>> + >>> + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; >>> + clock-names = "camss_top_ahb", "cci"; >> >> do you not need an axi clock GCC_CAMSS_AXI_CLK ? > > AFAIU AXI is not involved for CCI. I'm not able to infer that from statically provided infromation, try forcefully shutting the clock down (both the branch and _SRC) and poking at the CCI Konrad