Re: [PATCH v5 0/8] Support Zve32[xf] and Zve64[xfd] Vector subextensions

[patchwork-bot+linux-riscv@kernel.org]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Fri, 10 May 2024 00:26:50 +0800 you wrote:
> The series composes of two parts. The first part Specifically,
> patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
> vlenb is observed by the system. Patch 2 fixes the issue by failing the
> boot process of a secondary core if vlenb mismatches.
> 
> Here is the organization of the series:
>  - Patch 1, 2 provide a fix for mismatching vlen problem [1]. The
>    solution is to fail secondary cores if their vlenb is not the same as
>    the boot core.
>  - Patch 3 is a cleanup for introducing ZVE* Vector subextensions. It
>    gives the obsolete ISA parser the ability to expand ISA extensions for
>    sigle letter extensions.
>  - Patch 4, 5, 6 introduce Zve32x, Zve32f, Zve64x, Zve64f, Zve64d for isa
>    parsing and hwprobe, and document about it.
>  - Patch 7 makes has_vector() check against ZVE32X instead of V, so most
>    userspace Vector supports will be available for bare ZVE32X.
>  - Patch 8 updates the prctl test so that it runs on ZVE32X.
> 
> [...]

Here is the summary with links:
  - [v5,1/8] riscv: vector: add a comment when calling riscv_setup_vsize()
    https://git.kernel.org/riscv/c/77afe3e514b8
  - [v5,2/8] riscv: smp: fail booting up smp if inconsistent vlen is detected
    https://git.kernel.org/riscv/c/38a94c46660f
  - [v5,3/8] riscv: cpufeature: call match_isa_ext() for single-letter extensions
    https://git.kernel.org/riscv/c/98a5700dfaec
  - [v5,4/8] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description
    https://git.kernel.org/riscv/c/037df2966afc
  - [v5,5/8] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
    https://git.kernel.org/riscv/c/1e7483542bf8
  - [v5,6/8] riscv: hwprobe: add zve Vector subextensions into hwprobe interface
    https://git.kernel.org/riscv/c/de8f8282a969
  - [v5,7/8] riscv: vector: adjust minimum Vector requirement to ZVE32X
    https://git.kernel.org/riscv/c/ac295b67422d
  - [v5,8/8] selftest: run vector prctl test for ZVE32X
    https://git.kernel.org/riscv/c/edc96a2b4c79

You are awesome, thank you!
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