[PATCH V226/7] dt-bindings: PCI: host-generic-pci: Add snps,dw-pcie-ecam-msi binding

[Mayank Rana <quic_mrana@quicinc.com>]

To support MSI functionality using Synopsys DesignWare PCIe controller
based MSI controller with ECAM driver, add "snps,dw-pcie-ecam-msi
compatible binding which uses provided SPIs to support MSI functionality.

Signed-off-by: Mayank Rana <quic_mrana@quicinc.com>
---
 .../devicetree/bindings/pci/host-generic-pci.yaml  | 57 ++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml
index 9c714fa..9e860d5 100644
--- a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml
+++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml
@@ -81,6 +81,12 @@ properties:
               - marvell,armada8k-pcie-ecam
               - socionext,synquacer-pcie-ecam
           - const: snps,dw-pcie-ecam
+      - description: |
+         Firmware is configuring Synopsys DesignWare PCIe controller in RC mode with
+         ECAM compatible fashion. To use MSI controller of Synopsys DesignWare PCIe
+         controller for MSI functionality, this compatible is used.
+        items:
+          - const: snps,dw-pcie-ecam-msi
       - description:
           CAM or ECAM compliant PCI host controllers without any quirks
         enum:
@@ -116,6 +122,20 @@ properties:
       A phandle to the node that controls power or/and system resource or interface to firmware
       to enable ECAM compliant PCIe root complex.
 
+  interrupts:
+    description:
+      DWC PCIe Root Port/Complex specific MSI interrupt/IRQs.
+    minItems: 1
+    maxItems: 8
+
+  interrupt-names:
+    description:
+      MSI interrupt names
+    minItems: 1
+    maxItems: 8
+    items:
+        pattern: '^msi[0-9]+$'
+
 required:
   - compatible
   - reg
@@ -146,11 +166,22 @@ allOf:
         reg:
           maxItems: 1
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: snps,dw-pcie-ecam-msi
+    then:
+      required:
+        - interrupts
+        - interrupt-names
+
 unevaluatedProperties: false
 
 examples:
   - |
 
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
     bus {
         #address-cells = <2>;
         #size-cells = <2>;
@@ -180,5 +211,31 @@ examples:
             interrupt-map-mask = <0xf800 0x0 0x0  0x7>;
             power-domains = <&scmi5_pd 0>;
         };
+
+        pcie0: pci@1c00000 {
+            compatible = "snps,dw-pcie-ecam-msi";
+            reg = <0x4 0x00000000 0 0x10000000>;
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
+                  <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
+            bus-range = <0x00 0xff>;
+            dma-coherent;
+            linux,pci-domain = <0>;
+            power-domains = <&scmi5_pd 0>;
+            iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+                <0x100 &pcie_smmu 0x0001 0x1>;
+
+            interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7";
+      };
     };
 ...
-- 
2.7.4