[PATCH v5 0/2] Add one clock gate for i.MX95 HSIO block

[PATCH v5 0/2] Add one clock gate for i.MX95 HSIO block

[Richard Zhu]

REF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
enable/disable.
Add one clock gate for i.MX95 HSIO block to support PCIe REF clock
out gate.

v5 changes:
- Rebase to v6.12-rc3.

v4 changes:
- Correct typo in commit message of #2 patch.

v3 changes:
- Squash first two dt-binding patches into one.
- Add Krzysztof's Acked-by tag, and Frank's Reviewed-by tag.

v2 changes:
- Correct the compatible entries by alphabetical order
- Include all necessary To/Cc entried reminderd by Krzysztof.
Thanks.

[PATCH v5 1/2] dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible
[PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block

Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml |  5 +++--
drivers/clk/imx/clk-imx95-blk-ctl.c                            | 20 ++++++++++++++++++++
2 files changed, 23 insertions(+), 2 deletions(-)

[PATCH v5 1/2] dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL

[Richard Zhu]

Sort compatible entries by alphabetical order.
Then, add compatible string "nxp,imx95-hsio-blk-ctl" for i.MX95.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml         | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
index 5dc360b2ea4b..d0291bfff23a 100644
--- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
+++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
@@ -13,9 +13,10 @@ properties:
   compatible:
     items:
       - enum:
-          - nxp,imx95-lvds-csr
-          - nxp,imx95-display-csr
           - nxp,imx95-camera-csr
+          - nxp,imx95-display-csr
+          - nxp,imx95-hsio-blk-ctl
+          - nxp,imx95-lvds-csr
           - nxp,imx95-netcmix-blk-ctrl
           - nxp,imx95-vpu-csr
       - const: syscon
-- 
2.37.1

[PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block

[Richard Zhu]

CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
enable/disable.

Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF clock
out gate.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 19a62da74be4..25974947ad0c 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -277,6 +277,25 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
 	.clk_reg_offset = 0,
 };
 
+static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
+	[0] = {
+		.name = "hsio_blk_ctl_clk",
+		.parent_names = (const char *[]){ "hsio_pll", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 6,
+		.bit_width = 1,
+		.type = CLK_GATE,
+		.flags = CLK_SET_RATE_PARENT,
+	}
+};
+
+static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
+	.num_clks = 1,
+	.clk_dev_data = hsio_blk_ctl_clk_dev_data,
+	.clk_reg_offset = 0,
+};
+
 static int imx95_bc_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -447,6 +466,7 @@ static const struct of_device_id imx95_bc_of_match[] = {
 	{ .compatible = "nxp,imx95-display-master-csr", },
 	{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
 	{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
+	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
 	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
 	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
 	{ /* Sentinel */ },
-- 
2.37.1

Re: [PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block

[Alexander Stein]

Hi Richard,

Am Dienstag, 15. Oktober 2024, 09:34:04 CEST schrieb Richard Zhu:
> CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
> enable/disable.
> 
> Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF clock
> out gate.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-imx95-blk-ctl.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
> index 19a62da74be4..25974947ad0c 100644
> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> @@ -277,6 +277,25 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
>  	.clk_reg_offset = 0,
>  };
>  
> +static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
> +	[0] = {
> +		.name = "hsio_blk_ctl_clk",
> +		.parent_names = (const char *[]){ "hsio_pll", },
> +		.num_parents = 1,
> +		.reg = 0,

According to RM the register LFAST_IO_REG has offset 0xc0. How does the DT node look like?
If this is the HSIO block control I would have expected this to control the whole block.

Best regards,
Alexander

> +		.bit_idx = 6,
> +		.bit_width = 1,
> +		.type = CLK_GATE,
> +		.flags = CLK_SET_RATE_PARENT,
> +	}
> +};
> +
> +static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
> +	.num_clks = 1,
> +	.clk_dev_data = hsio_blk_ctl_clk_dev_data,
> +	.clk_reg_offset = 0,
> +};
> +
>  static int imx95_bc_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -447,6 +466,7 @@ static const struct of_device_id imx95_bc_of_match[] = {
>  	{ .compatible = "nxp,imx95-display-master-csr", },
>  	{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
>  	{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
> +	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
>  	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
>  	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
>  	{ /* Sentinel */ },
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

RE: [PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block

[Hongxing Zhu]

Hi Alexander:

> -----Original Message-----
> From: Alexander Stein <alexander.stein@ew.tq-group.com>
> Sent: 2024年10月15日 17:19
> To: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> abelvesa@kernel.org; Peng Fan <peng.fan@nxp.com>;
> mturquette@baylibre.com; sboyd@kernel.org; shawnguo@kernel.org;
> s.hauer@pengutronix.de; festevam@gmail.com; Hongxing Zhu
> <hongxing.zhu@nxp.com>
> Cc: Hongxing Zhu <hongxing.zhu@nxp.com>; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-clk@vger.kernel.org; imx@lists.linux.dev; kernel@pengutronix.de
> Subject: Re: [PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block
>
> Hi Richard,
>
> Am Dienstag, 15. Oktober 2024, 09:34:04 CEST schrieb Richard Zhu:
> > CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
> > enable/disable.
> >
> > Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF
> > clock out gate.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > Reviewed-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/imx/clk-imx95-blk-ctl.c | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > b/drivers/clk/imx/clk-imx95-blk-ctl.c
> > index 19a62da74be4..25974947ad0c 100644
> > --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> > @@ -277,6 +277,25 @@ static const struct imx95_blk_ctl_dev_data
> netcmix_dev_data = {
> >     .clk_reg_offset = 0,
> >  };
> >
> > +static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] =
> {
> > +   [0] = {
> > +           .name = "hsio_blk_ctl_clk",
> > +           .parent_names = (const char *[]){ "hsio_pll", },
> > +           .num_parents = 1,
> > +           .reg = 0,
>
> According to RM the register LFAST_IO_REG has offset 0xc0. How does the DT
> node look like?
> If this is the HSIO block control I would have expected this to control the whole
> block.
>
Thanks for your comments.
i.MX95 HSIO_BLK_CTL is a mix of kinds of setting registers of HSIO modules.
For example, Wakeup control of USB, AXI master QoS of USB and PCIe, and so on.
Only LFAST_IO_REG(offset 0xc0) register is used as clock out control.
So, only this register is contained in the commit.

Best Regards
Richard Zhu
> Best regards,
> Alexander
>
> > +           .bit_idx = 6,
> > +           .bit_width = 1,
> > +           .type = CLK_GATE,
> > +           .flags = CLK_SET_RATE_PARENT,
> > +   }
> > +};
> > +
> > +static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
> > +   .num_clks = 1,
> > +   .clk_dev_data = hsio_blk_ctl_clk_dev_data,
> > +   .clk_reg_offset = 0,
> > +};
> > +
> >  static int imx95_bc_probe(struct platform_device *pdev)  {
> >     struct device *dev = &pdev->dev;
> > @@ -447,6 +466,7 @@ static const struct of_device_id imx95_bc_of_match[]
> = {
> >     { .compatible = "nxp,imx95-display-master-csr", },
> >     { .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
> >     { .compatible = "nxp,imx95-display-csr", .data =
> > &dispmix_csr_dev_data },
> > +   { .compatible = "nxp,imx95-hsio-blk-ctl", .data =
> > +&hsio_blk_ctl_dev_data },
> >     { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
> >     { .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
> >     { /* Sentinel */ },
> >
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-g/
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>

Re: [PATCH v5 0/2] Add one clock gate for i.MX95 HSIO block

[Abel Vesa]

On Tue, 15 Oct 2024 15:34:02 +0800, Richard Zhu wrote:
> REF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
> enable/disable.
> Add one clock gate for i.MX95 HSIO block to support PCIe REF clock
> out gate.
> 
> v5 changes:
> - Rebase to v6.12-rc3.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL
      commit: 731237359d83bfb4f27eea5b7a8935af5c72a5ac
[2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block
      commit: cf295252f0d88410d5793fa6db56a7192a65d66f

Best regards,
-- 
Abel Vesa <abel.vesa@linaro.org>