* [PATCH 0/3] arm64: dts: imx8ulp-evk: add sound card support
@ 2024-10-16 9:56 Shengjiu Wang
2024-10-16 9:56 ` [PATCH 1/3] arm64: dts: imx8ulp: Add audio device nodes Shengjiu Wang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Shengjiu Wang @ 2024-10-16 9:56 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam,
devicetree, imx, linux-arm-kernel, linux-kernel, shengjiu.wang
add bt-sco and spdif sound card support.
Shengjiu Wang (3):
arm64: dts: imx8ulp: Add audio device nodes
arm64: dts: imx8ulp-evk: Add bt-sco sound card support
arm64: dts: imx8ulp-evk: Add spdif sound card support
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 70 ++++++
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 214 ++++++++++++++++++
2 files changed, 284 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/3] arm64: dts: imx8ulp: Add audio device nodes 2024-10-16 9:56 [PATCH 0/3] arm64: dts: imx8ulp-evk: add sound card support Shengjiu Wang @ 2024-10-16 9:56 ` Shengjiu Wang 2024-10-22 3:18 ` Shawn Guo 2024-10-16 9:56 ` [PATCH 2/3] arm64: dts: imx8ulp-evk: Add bt-sco sound card support Shengjiu Wang 2024-10-16 9:56 ` [PATCH 3/3] arm64: dts: imx8ulp-evk: Add spdif " Shengjiu Wang 2 siblings, 1 reply; 6+ messages in thread From: Shengjiu Wang @ 2024-10-16 9:56 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam, devicetree, imx, linux-arm-kernel, linux-kernel, shengjiu.wang Add edma1, sai4, sai5 device nodes bus of in per_bridge3. Add edma2, sai6, sai7, spdif device nodes in bus of per_bridge5. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 214 +++++++++++++++++++++ 1 file changed, 214 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index e32d5afcf4a9..3223f1ac2051 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -212,6 +212,71 @@ per_bridge3: bus@29000000 { #size-cells = <1>; ranges; + edma1: dma-controller@29010000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x29010000 0x210000>; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, + <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, + <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, + <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, + <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, + <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, + <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, + <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, + <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, + <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, + <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, + <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, + <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, + <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, + <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, + <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; + clock-names = "dma", "ch00","ch01", "ch02", "ch03", + "ch04", "ch05", "ch06", "ch07", + "ch08", "ch09", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24", "ch25", "ch26", "ch27", + "ch28", "ch29", "ch30", "ch31"; + status = "okay"; + }; + mu: mailbox@29220000 { compatible = "fsl,imx8ulp-mu"; reg = <0x29220000 0x10000>; @@ -442,6 +507,36 @@ lpuart7: serial@29870000 { status = "disabled"; }; + sai4: sai@29880000 { + compatible = "fsl,imx8ulp-sai"; + reg = <0x29880000 0x10000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + fsl,dataline = <0 0x03 0x03>; + status = "disabled"; + }; + + sai5: sai@29890000 { + compatible = "fsl,imx8ulp-sai"; + reg = <0x29890000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + fsl,dataline = <0 0x0f 0x0f>; + status = "disabled"; + }; + iomuxc1: pinctrl@298c0000 { compatible = "fsl,imx8ulp-iomuxc1"; reg = <0x298c0000 0x10000>; @@ -614,6 +709,71 @@ per_bridge5: bus@2d800000 { #size-cells = <1>; ranges; + edma2: dma-controller@2d800000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x2d800000 0x210000>; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, + <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, + <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, + <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, + <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, + <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, + <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, + <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, + <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, + <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, + <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, + <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, + <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; + clock-names = "dma", "ch00","ch01", "ch02", "ch03", + "ch04", "ch05", "ch06", "ch07", + "ch08", "ch09", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24", "ch25", "ch26", "ch27", + "ch28", "ch29", "ch30", "ch31"; + status = "okay"; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; @@ -626,6 +786,60 @@ pcc5: clock-controller@2da70000 { #clock-cells = <1>; #reset-cells = <1>; }; + + sai6: sai@2da90000 { + compatible = "fsl,imx8ulp-sai"; + reg = <0x2da90000 0x10000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + fsl,dataline = <0 0x0f 0x0f>; + status = "disabled"; + }; + + sai7: sai@2daa0000 { + compatible = "fsl,imx8ulp-sai"; + reg = <0x2daa0000 0x10000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + fsl,dataline = <0 0x0f 0x0f>; + status = "disabled"; + }; + + spdif: spdif@2dab0000 { + compatible = "fsl,imx8ulp-spdif"; + reg = <0x2dab0000 0x10000>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ + <&sosc>, /* 0, extal */ + <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ + <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ + <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; }; gpiod: gpio@2e200000 { -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] arm64: dts: imx8ulp: Add audio device nodes 2024-10-16 9:56 ` [PATCH 1/3] arm64: dts: imx8ulp: Add audio device nodes Shengjiu Wang @ 2024-10-22 3:18 ` Shawn Guo 2024-10-22 3:33 ` Shengjiu Wang 0 siblings, 1 reply; 6+ messages in thread From: Shawn Guo @ 2024-10-22 3:18 UTC (permalink / raw) To: Shengjiu Wang Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam, devicetree, imx, linux-arm-kernel, linux-kernel, shengjiu.wang On Wed, Oct 16, 2024 at 05:56:29PM +0800, Shengjiu Wang wrote: > Add edma1, sai4, sai5 device nodes bus of in per_bridge3. > Add edma2, sai6, sai7, spdif device nodes in bus of > per_bridge5. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 214 +++++++++++++++++++++ > 1 file changed, 214 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > index e32d5afcf4a9..3223f1ac2051 100644 > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > @@ -212,6 +212,71 @@ per_bridge3: bus@29000000 { > #size-cells = <1>; > ranges; > > + edma1: dma-controller@29010000 { > + compatible = "fsl,imx8ulp-edma"; > + reg = <0x29010000 0x210000>; > + #dma-cells = <3>; > + dma-channels = <32>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, > + <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; > + clock-names = "dma", "ch00","ch01", "ch02", "ch03", > + "ch04", "ch05", "ch06", "ch07", > + "ch08", "ch09", "ch10", "ch11", > + "ch12", "ch13", "ch14", "ch15", > + "ch16", "ch17", "ch18", "ch19", > + "ch20", "ch21", "ch22", "ch23", > + "ch24", "ch25", "ch26", "ch27", > + "ch28", "ch29", "ch30", "ch31"; > + status = "okay"; > + }; > + > mu: mailbox@29220000 { > compatible = "fsl,imx8ulp-mu"; > reg = <0x29220000 0x10000>; > @@ -442,6 +507,36 @@ lpuart7: serial@29870000 { > status = "disabled"; > }; > > + sai4: sai@29880000 { > + compatible = "fsl,imx8ulp-sai"; > + reg = <0x29880000 0x10000>; > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, > + <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, > + <&cgc1 IMX8ULP_CLK_DUMMY>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; > + dma-names = "rx", "tx"; > + #sound-dai-cells = <0>; > + fsl,dataline = <0 0x03 0x03>; > + status = "disabled"; > + }; > + > + sai5: sai@29890000 { > + compatible = "fsl,imx8ulp-sai"; > + reg = <0x29890000 0x10000>; > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, > + <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, > + <&cgc1 IMX8ULP_CLK_DUMMY>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; > + dma-names = "rx", "tx"; > + #sound-dai-cells = <0>; > + fsl,dataline = <0 0x0f 0x0f>; > + status = "disabled"; > + }; > + > iomuxc1: pinctrl@298c0000 { > compatible = "fsl,imx8ulp-iomuxc1"; > reg = <0x298c0000 0x10000>; > @@ -614,6 +709,71 @@ per_bridge5: bus@2d800000 { > #size-cells = <1>; > ranges; > > + edma2: dma-controller@2d800000 { > + compatible = "fsl,imx8ulp-edma"; > + reg = <0x2d800000 0x210000>; > + #dma-cells = <3>; > + dma-channels = <32>; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, > + <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; > + clock-names = "dma", "ch00","ch01", "ch02", "ch03", > + "ch04", "ch05", "ch06", "ch07", > + "ch08", "ch09", "ch10", "ch11", > + "ch12", "ch13", "ch14", "ch15", > + "ch16", "ch17", "ch18", "ch19", > + "ch20", "ch21", "ch22", "ch23", > + "ch24", "ch25", "ch26", "ch27", > + "ch28", "ch29", "ch30", "ch31"; > + status = "okay"; The "okay" status is usually used to flip "disabled". It doesn't seem really needed here? Shawn > + }; > + > cgc2: clock-controller@2da60000 { > compatible = "fsl,imx8ulp-cgc2"; > reg = <0x2da60000 0x10000>; > @@ -626,6 +786,60 @@ pcc5: clock-controller@2da70000 { > #clock-cells = <1>; > #reset-cells = <1>; > }; > + > + sai6: sai@2da90000 { > + compatible = "fsl,imx8ulp-sai"; > + reg = <0x2da90000 0x10000>; > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, > + <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, > + <&cgc1 IMX8ULP_CLK_DUMMY>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; > + dma-names = "rx", "tx"; > + #sound-dai-cells = <0>; > + fsl,dataline = <0 0x0f 0x0f>; > + status = "disabled"; > + }; > + > + sai7: sai@2daa0000 { > + compatible = "fsl,imx8ulp-sai"; > + reg = <0x2daa0000 0x10000>; > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, > + <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, > + <&cgc1 IMX8ULP_CLK_DUMMY>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; > + dma-names = "rx", "tx"; > + #sound-dai-cells = <0>; > + fsl,dataline = <0 0x0f 0x0f>; > + status = "disabled"; > + }; > + > + spdif: spdif@2dab0000 { > + compatible = "fsl,imx8ulp-spdif"; > + reg = <0x2dab0000 0x10000>; > + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ > + <&sosc>, /* 0, extal */ > + <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ > + <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ > + <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ > + clock-names = "core", "rxtx0", > + "rxtx1", "rxtx2", > + "rxtx3", "rxtx4", > + "rxtx5", "rxtx6", > + "rxtx7", "spba"; > + dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > }; > > gpiod: gpio@2e200000 { > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] arm64: dts: imx8ulp: Add audio device nodes 2024-10-22 3:18 ` Shawn Guo @ 2024-10-22 3:33 ` Shengjiu Wang 0 siblings, 0 replies; 6+ messages in thread From: Shengjiu Wang @ 2024-10-22 3:33 UTC (permalink / raw) To: Shawn Guo Cc: Shengjiu Wang, robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam, devicetree, imx, linux-arm-kernel, linux-kernel On Tue, Oct 22, 2024 at 11:19 AM Shawn Guo <shawnguo2@yeah.net> wrote: > > On Wed, Oct 16, 2024 at 05:56:29PM +0800, Shengjiu Wang wrote: > > Add edma1, sai4, sai5 device nodes bus of in per_bridge3. > > Add edma2, sai6, sai7, spdif device nodes in bus of > > per_bridge5. > > > > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 214 +++++++++++++++++++++ > > 1 file changed, 214 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > index e32d5afcf4a9..3223f1ac2051 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > @@ -212,6 +212,71 @@ per_bridge3: bus@29000000 { > > #size-cells = <1>; > > ranges; > > > > + edma1: dma-controller@29010000 { > > + compatible = "fsl,imx8ulp-edma"; > > + reg = <0x29010000 0x210000>; > > + #dma-cells = <3>; > > + dma-channels = <32>; > > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, > > + <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; > > + clock-names = "dma", "ch00","ch01", "ch02", "ch03", > > + "ch04", "ch05", "ch06", "ch07", > > + "ch08", "ch09", "ch10", "ch11", > > + "ch12", "ch13", "ch14", "ch15", > > + "ch16", "ch17", "ch18", "ch19", > > + "ch20", "ch21", "ch22", "ch23", > > + "ch24", "ch25", "ch26", "ch27", > > + "ch28", "ch29", "ch30", "ch31"; > > + status = "okay"; > > + }; > > + > > mu: mailbox@29220000 { > > compatible = "fsl,imx8ulp-mu"; > > reg = <0x29220000 0x10000>; > > @@ -442,6 +507,36 @@ lpuart7: serial@29870000 { > > status = "disabled"; > > }; > > > > + sai4: sai@29880000 { > > + compatible = "fsl,imx8ulp-sai"; > > + reg = <0x29880000 0x10000>; > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, > > + <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, > > + <&cgc1 IMX8ULP_CLK_DUMMY>; > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > + dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; > > + dma-names = "rx", "tx"; > > + #sound-dai-cells = <0>; > > + fsl,dataline = <0 0x03 0x03>; > > + status = "disabled"; > > + }; > > + > > + sai5: sai@29890000 { > > + compatible = "fsl,imx8ulp-sai"; > > + reg = <0x29890000 0x10000>; > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, > > + <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, > > + <&cgc1 IMX8ULP_CLK_DUMMY>; > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > + dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; > > + dma-names = "rx", "tx"; > > + #sound-dai-cells = <0>; > > + fsl,dataline = <0 0x0f 0x0f>; > > + status = "disabled"; > > + }; > > + > > iomuxc1: pinctrl@298c0000 { > > compatible = "fsl,imx8ulp-iomuxc1"; > > reg = <0x298c0000 0x10000>; > > @@ -614,6 +709,71 @@ per_bridge5: bus@2d800000 { > > #size-cells = <1>; > > ranges; > > > > + edma2: dma-controller@2d800000 { > > + compatible = "fsl,imx8ulp-edma"; > > + reg = <0x2d800000 0x210000>; > > + #dma-cells = <3>; > > + dma-channels = <32>; > > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, > > + <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; > > + clock-names = "dma", "ch00","ch01", "ch02", "ch03", > > + "ch04", "ch05", "ch06", "ch07", > > + "ch08", "ch09", "ch10", "ch11", > > + "ch12", "ch13", "ch14", "ch15", > > + "ch16", "ch17", "ch18", "ch19", > > + "ch20", "ch21", "ch22", "ch23", > > + "ch24", "ch25", "ch26", "ch27", > > + "ch28", "ch29", "ch30", "ch31"; > > + status = "okay"; > > The "okay" status is usually used to flip "disabled". It doesn't seem > really needed here? > Ok, will remove it. Best regards Shengjiu Wang > Shawn > > > + }; > > + > > cgc2: clock-controller@2da60000 { > > compatible = "fsl,imx8ulp-cgc2"; > > reg = <0x2da60000 0x10000>; > > @@ -626,6 +786,60 @@ pcc5: clock-controller@2da70000 { > > #clock-cells = <1>; > > #reset-cells = <1>; > > }; > > + > > + sai6: sai@2da90000 { > > + compatible = "fsl,imx8ulp-sai"; > > + reg = <0x2da90000 0x10000>; > > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, > > + <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, > > + <&cgc1 IMX8ULP_CLK_DUMMY>; > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > + dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; > > + dma-names = "rx", "tx"; > > + #sound-dai-cells = <0>; > > + fsl,dataline = <0 0x0f 0x0f>; > > + status = "disabled"; > > + }; > > + > > + sai7: sai@2daa0000 { > > + compatible = "fsl,imx8ulp-sai"; > > + reg = <0x2daa0000 0x10000>; > > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, > > + <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, > > + <&cgc1 IMX8ULP_CLK_DUMMY>; > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > + dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; > > + dma-names = "rx", "tx"; > > + #sound-dai-cells = <0>; > > + fsl,dataline = <0 0x0f 0x0f>; > > + status = "disabled"; > > + }; > > + > > + spdif: spdif@2dab0000 { > > + compatible = "fsl,imx8ulp-spdif"; > > + reg = <0x2dab0000 0x10000>; > > + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ > > + <&sosc>, /* 0, extal */ > > + <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ > > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ > > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ > > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ > > + <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ > > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ > > + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ > > + <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ > > + clock-names = "core", "rxtx0", > > + "rxtx1", "rxtx2", > > + "rxtx3", "rxtx4", > > + "rxtx5", "rxtx6", > > + "rxtx7", "spba"; > > + dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > }; > > > > gpiod: gpio@2e200000 { > > -- > > 2.34.1 > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] arm64: dts: imx8ulp-evk: Add bt-sco sound card support 2024-10-16 9:56 [PATCH 0/3] arm64: dts: imx8ulp-evk: add sound card support Shengjiu Wang 2024-10-16 9:56 ` [PATCH 1/3] arm64: dts: imx8ulp: Add audio device nodes Shengjiu Wang @ 2024-10-16 9:56 ` Shengjiu Wang 2024-10-16 9:56 ` [PATCH 3/3] arm64: dts: imx8ulp-evk: Add spdif " Shengjiu Wang 2 siblings, 0 replies; 6+ messages in thread From: Shengjiu Wang @ 2024-10-16 9:56 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam, devicetree, imx, linux-arm-kernel, linux-kernel, shengjiu.wang Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index e937e5f8fa8b..7d6d332fa779 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -11,6 +11,11 @@ / { model = "NXP i.MX8ULP EVK"; compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; + bt_sco_codec: bt-sco-codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + chosen { stdout-path = &lpuart5; }; @@ -83,6 +88,25 @@ clock_ext_ts: clock-ext-ts { clock-output-names = "ext_ts_clk"; #clock-cells = <0>; }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai5>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; }; &cm33 { @@ -153,6 +177,16 @@ ptn5150_2: typec@3d { }; }; +&sai5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-1 = <&pinctrl_sai5>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI5_SEL>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + fsl,dataline = <1 0x08 0x01>; + status = "okay"; +}; + &usbotg1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; @@ -282,6 +316,15 @@ MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x43 + MX8ULP_PAD_PTF27__I2S5_TX_FS 0x43 + MX8ULP_PAD_PTF28__I2S5_TXD0 0x43 + MX8ULP_PAD_PTF24__I2S5_RXD3 0x43 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8ULP_PAD_PTF3__PTF3 0x3 -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] arm64: dts: imx8ulp-evk: Add spdif sound card support 2024-10-16 9:56 [PATCH 0/3] arm64: dts: imx8ulp-evk: add sound card support Shengjiu Wang 2024-10-16 9:56 ` [PATCH 1/3] arm64: dts: imx8ulp: Add audio device nodes Shengjiu Wang 2024-10-16 9:56 ` [PATCH 2/3] arm64: dts: imx8ulp-evk: Add bt-sco sound card support Shengjiu Wang @ 2024-10-16 9:56 ` Shengjiu Wang 2 siblings, 0 replies; 6+ messages in thread From: Shengjiu Wang @ 2024-10-16 9:56 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam, devicetree, imx, linux-arm-kernel, linux-kernel, shengjiu.wang Add spdif sound card support, configure the pinmux. This sound card supports only playback sound through HDMI interface. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 7d6d332fa779..290a49bea2f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -107,6 +107,18 @@ simple-audio-card,codec { sound-dai = <&bt_sco_codec 1>; }; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + audio-cpu = <&spdif>; + audio-codec = <&spdif_out>; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; }; &cm33 { @@ -187,6 +199,15 @@ &sai5 { status = "okay"; }; +&spdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-1 = <&pinctrl_spdif>; + assigned-clocks = <&cgc2 IMX8ULP_CLK_SPDIF_SEL>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + status = "okay"; +}; + &usbotg1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; @@ -325,6 +346,12 @@ MX8ULP_PAD_PTF24__I2S5_RXD3 0x43 >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX8ULP_PAD_PTF25__SPDIF_OUT1 0x43 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8ULP_PAD_PTF3__PTF3 0x3 -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-10-22 3:33 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-10-16 9:56 [PATCH 0/3] arm64: dts: imx8ulp-evk: add sound card support Shengjiu Wang 2024-10-16 9:56 ` [PATCH 1/3] arm64: dts: imx8ulp: Add audio device nodes Shengjiu Wang 2024-10-22 3:18 ` Shawn Guo 2024-10-22 3:33 ` Shengjiu Wang 2024-10-16 9:56 ` [PATCH 2/3] arm64: dts: imx8ulp-evk: Add bt-sco sound card support Shengjiu Wang 2024-10-16 9:56 ` [PATCH 3/3] arm64: dts: imx8ulp-evk: Add spdif " Shengjiu Wang
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).