[PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Yixun Lan]

SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
1.0 and Zicond evaluation now. Add initial support for it to allow more
people to participate in building drivers to mainline for it.

This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
booted to busybox on initrd with this log[3].

As previous discussion in patch v1[4], maintainer expect more basic drivers
ready before really merging it, which would be fine. For other follow-up patches, 
that are clk, pinctrl/gpio, reset.. My current goal would target at a headless
system including SD card, emmc, and ethernet.

In this series, the uart node has no 'fifo-size', 'tx-threshold' property populated,
will add them once this patch is resolved, see thread [5]

P.S: talked to Yangyu, I will help and take care of this patch series, thanks

---
Changes in v5:
- fix cache-sets in dts
- collect Rob's Ack
- rebase to 6.11-rc1
- Link to v4: https://lore.kernel.org/r/20240709-k1-01-basic-dt-v4-0-ae5bb5e56aaf@gentoo.org

Changes in v4:
 - add i/d-cache, l2-cache info
 - squash uart1 dts node
 - update tags
 - Link to v3: https://lore.kernel.org/r/20240703-k1-01-basic-dt-v3-0-12f73b47461e@gentoo.org

Changes in v3:
 - fix dt_binding_check error
 - fix plic compatible
 - fix uart node name
 - add uart1 dts node
 - collect tags
 - Link to v2: https://lore.kernel.org/r/20240627-k1-01-basic-dt-v2-0-cc06c7555f07@gentoo.org

Changes in v2:
 - fix timebase-frequency according to current setting
 - add other uart dt nodes, fix input frequency
 - introduce new uart compatible for K1 SoC
 - add 'k1' prefix to bananapi-f3.dts
 - fix k1-clint compatible
 - fix some typos
 - Link to v1: https://lore.kernel.org/r/tencent_BC64B7B1876F5D10479BD19112F73F262505@qq.com

Link: https://github.com/BPI-SINOVOIP/armbian-build/tree/v24.04.30 [1]
Link: https://gist.github.com/cyyself/a07096e6e99c949ed13f8fa16d884402 [2]
Link: https://gist.github.com/cyyself/a2201c01f5c8955a119641f97b7d0280 [3]
Link: https://lore.kernel.org/r/20240618-hardwood-footrest-ab5ec5bce3cf@wendy [4]
Link: https://lore.kernel.org/linux-riscv/20240706082928.2238-1-jszhang@kernel.org/ [5]

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Yixun Lan <dlan@gentoo.org>

---
Yangyu Chen (9):
      dt-bindings: vendor-prefixes: add spacemit
      dt-bindings: riscv: Add SpacemiT X60 compatibles
      dt-bindings: riscv: add SpacemiT K1 bindings
      dt-bindings: timer: Add SpacemiT K1 CLINT
      dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
      riscv: add SpacemiT SoC family Kconfig support
      riscv: dts: add initial SpacemiT K1 SoC device tree
      riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
      riscv: defconfig: enable SpacemiT SoC

Yixun Lan (1):
      dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 .../devicetree/bindings/riscv/spacemit.yaml        |  28 ++
 Documentation/devicetree/bindings/serial/8250.yaml |   4 +-
 .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/riscv/Kconfig.socs                            |   5 +
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/spacemit/Makefile              |   2 +
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts    |  19 +
 arch/riscv/boot/dts/spacemit/k1.dtsi               | 459 +++++++++++++++++++++
 arch/riscv/configs/defconfig                       |   1 +
 12 files changed, 523 insertions(+), 1 deletion(-)
---
base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b
change-id: 20240626-k1-01-basic-dt-1aa31eeebcd2

Best regards,
-- 
Yixun Lan <dlan@gentoo.org>

[PATCH v5 01/10] dt-bindings: vendor-prefixes: add spacemit

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Add new vendor strings to dt bindings for SpacemiT K1 SoC.

Link: https://www.spacemit.com/en/spacemit-key-stone-2/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index a70ce43b3dc03..30043488328b8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1382,6 +1382,8 @@ patternProperties:
     description: Sophgo Technology Inc.
   "^sourceparts,.*":
     description: Source Parts Inc.
+  "^spacemit,.*":
+    description: SpacemiT (Hangzhou) Technology Co. Ltd
   "^spansion,.*":
     description: Spansion Inc.
   "^sparkfun,.*":

-- 
2.45.2

[PATCH v5 02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
SoC.

Link: https://www.spacemit.com/en/spacemit-x60-core/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 8edc8261241ad..acb5b9ba6f049 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -46,6 +46,7 @@ properties:
               - sifive,u7
               - sifive,u74
               - sifive,u74-mc
+              - spacemit,x60
               - thead,c906
               - thead,c908
               - thead,c910

-- 
2.45.2

[PATCH v5 03/10] dt-bindings: riscv: add SpacemiT K1 bindings

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Add DT binding documentation for the SpacemiT K1 SoC[1] and the Banana
Pi BPi-F3 board[2] which used it.

Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [1]
Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [2]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Matthias Brugger <matthias.bgg@kernel.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 .../devicetree/bindings/riscv/spacemit.yaml        | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
new file mode 100644
index 0000000000000..52e55077af1ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/spacemit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT SoC-based boards
+
+maintainers:
+  - Yangyu Chen <cyy@cyyself.name>
+  - Yixun Lan <dlan@gentoo.org>
+
+description:
+  SpacemiT SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - bananapi,bpi-f3
+          - const: spacemit,k1
+
+additionalProperties: true
+
+...

-- 
2.45.2

[PATCH v5 04/10] dt-bindings: timer: Add SpacemiT K1 CLINT

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Add compatible string for SpacemiT K1 CLINT.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index b42d43d2de488..76d83aea4e2ba 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -31,6 +31,7 @@ properties:
           - enum:
               - canaan,k210-clint       # Canaan Kendryte K210
               - sifive,fu540-c000-clint # SiFive FU540
+              - spacemit,k1-clint       # SpacemiT K1
               - starfive,jh7100-clint   # StarFive JH7100
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100

-- 
2.45.2

[PATCH v5 05/10] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Add compatible string for SpacemiT K1 PLIC.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml      | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 709b2211276bd..f473ca3479efd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -59,6 +59,7 @@ properties:
           - enum:
               - canaan,k210-plic
               - sifive,fu540-c000-plic
+              - spacemit,k1-plic
               - starfive,jh7100-plic
               - starfive,jh7110-plic
           - const: sifive,plic-1.0.0

-- 
2.45.2

[PATCH v5 06/10] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible

[Yixun Lan]

Found SpacemiT's K1 uart controller is compatible with
Intel's Xscale uart, but it's still worth to introduce a new compatible.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 Documentation/devicetree/bindings/serial/8250.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 692aa05500fd5..0bde2379e8647 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -111,7 +111,9 @@ properties:
               - mediatek,mt7623-btif
           - const: mediatek,mtk-btif
       - items:
-          - const: mrvl,mmp-uart
+          - enum:
+              - mrvl,mmp-uart
+              - spacemit,k1-uart
           - const: intel,xscale-uart
       - items:
           - enum:

-- 
2.45.2

[PATCH v5 07/10] riscv: add SpacemiT SoC family Kconfig support

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

The first SoC in the SpacemiT series is K1, which contains 8 RISC-V
cores with RISC-V Vector v1.0 support.

Link: https://www.spacemit.com/en/spacemit-key-stone-2/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index f51bb24bc84c6..1916cf7ba450e 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -24,6 +24,11 @@ config ARCH_SOPHGO
 	help
 	  This enables support for Sophgo SoC platform hardware.
 
+config ARCH_SPACEMIT
+	bool "SpacemiT SoCs"
+	help
+	  This enables support for SpacemiT SoC platform hardware.
+
 config ARCH_STARFIVE
 	def_bool SOC_STARFIVE
 

-- 
2.45.2

[PATCH v5 08/10] riscv: dts: add initial SpacemiT K1 SoC device tree

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].

Key features:
- 4 cores per cluster, 2 clusters on chip
- UART IP is Intel XScale UART

Some key considerations:
- ISA string is inferred from vendor documentation[2]
- Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
- No coherent DMA on this board
    Inferred by taking vendor ethernet and MMC drivers to the mainline
    kernel. Without dma-noncoherent in soc node, the driver fails.
- Add cache nodes
    K1 SoC has 128 sets of 32KiB L1 I/D Cache for each hart, and 512 sets
    of 512KiB L2 Cache for each cluster.

Currently only support booting into console with only uart, other
features will be added soon later.

Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Yixun Lan <dlan@gentoo.org>

---
Changes in v5:
 - fix cache-sets
 - Link to v4: https://lore.kernel.org/all/20240709-k1-01-basic-dt-v4-8-ae5bb5e56aaf@gentoo.org/

Changes in v4:
 - add i/d-cache, l2-cache info
 - Link to v3: https://lore.kernel.org/all/20240703-k1-01-basic-dt-v3-8-12f73b47461e@gentoo.org/
---
 arch/riscv/boot/dts/spacemit/k1.dtsi | 459 +++++++++++++++++++++++++++++++++++
 1 file changed, 459 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
new file mode 100644
index 0000000000000..0777bf9e01183
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SpacemiT K1";
+	compatible = "spacemit,k1";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		serial4 = &uart5;
+		serial5 = &uart6;
+		serial6 = &uart7;
+		serial7 = &uart8;
+		serial8 = &uart9;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <24000000>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu_0>;
+				};
+				core1 {
+					cpu = <&cpu_1>;
+				};
+				core2 {
+					cpu = <&cpu_2>;
+				};
+				core3 {
+					cpu = <&cpu_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu_4>;
+				};
+				core1 {
+					cpu = <&cpu_5>;
+				};
+				core2 {
+					cpu = <&cpu_6>;
+				};
+				core3 {
+					cpu = <&cpu_7>;
+				};
+			};
+		};
+
+		cpu_0: cpu@0 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_1: cpu@1 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <1>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_2: cpu@2 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <2>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_3: cpu@3 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <3>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_4: cpu@4 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <4>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_5: cpu@5 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <5>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_6: cpu@6 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <6>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_7: cpu@7 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <7>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cluster0_l2_cache: l2-cache0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-sets = <512>;
+			cache-unified;
+		};
+
+		cluster1_l2_cache: l2-cache1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-sets = <512>;
+			cache-unified;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-noncoherent;
+		ranges;
+
+		uart0: serial@d4017000 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017000 0x0 0x100>;
+			interrupts = <42>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@d4017100 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017100 0x0 0x100>;
+			interrupts = <44>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@d4017200 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017200 0x0 0x100>;
+			interrupts = <45>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart4: serial@d4017300 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017300 0x0 0x100>;
+			interrupts = <46>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart5: serial@d4017400 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017400 0x0 0x100>;
+			interrupts = <47>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart6: serial@d4017500 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017500 0x0 0x100>;
+			interrupts = <48>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart7: serial@d4017600 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017600 0x0 0x100>;
+			interrupts = <49>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart8: serial@d4017700 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017700 0x0 0x100>;
+			interrupts = <50>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart9: serial@d4017800 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017800 0x0 0x100>;
+			interrupts = <51>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		plic: interrupt-controller@e0000000 {
+			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0xe0000000 0x0 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>,
+					      <&cpu5_intc 11>, <&cpu5_intc 9>,
+					      <&cpu6_intc 11>, <&cpu6_intc 9>,
+					      <&cpu7_intc 11>, <&cpu7_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			riscv,ndev = <159>;
+		};
+
+		clint: timer@e4000000 {
+			compatible = "spacemit,k1-clint", "sifive,clint0";
+			reg = <0x0 0xe4000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>,
+					      <&cpu5_intc 3>, <&cpu5_intc 7>,
+					      <&cpu6_intc 3>, <&cpu6_intc 7>,
+					      <&cpu7_intc 3>, <&cpu7_intc 7>;
+		};
+
+		sec_uart1: serial@f0612000 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xf0612000 0x0 0x100>;
+			interrupts = <43>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "reserved"; /* for TEE usage */
+		};
+	};
+};

-- 
2.45.2

[PATCH v5 09/10] riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Banana Pi BPI-F3 [1] is a industrial grade RISC-V development board, it
design with SpacemiT K1 8 core RISC-V chip [2].

Currently only support booting into console with only uart enabled,
other features will be added soon later.

Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [1]
Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [2]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/boot/dts/Makefile                    |  1 +
 arch/riscv/boot/dts/spacemit/Makefile           |  2 ++
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 19 +++++++++++++++++++
 3 files changed, 22 insertions(+)

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index fdae05bbf5563..bff887d38abe4 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -5,6 +5,7 @@ subdir-y += microchip
 subdir-y += renesas
 subdir-y += sifive
 subdir-y += sophgo
+subdir-y += spacemit
 subdir-y += starfive
 subdir-y += thead
 
diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
new file mode 100644
index 0000000000000..ac617319a5742
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-f3.dtb
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
new file mode 100644
index 0000000000000..023274189b492
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k1.dtsi"
+
+/ {
+	model = "Banana Pi BPI-F3";
+	compatible = "bananapi,bpi-f3", "spacemit,k1";
+
+	chosen {
+		stdout-path = "serial0";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};

-- 
2.45.2

[PATCH v5 10/10] riscv: defconfig: enable SpacemiT SoC

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Enable SpacemiT SoC config in defconfig to allow the default upstream
kernel booting on Banana Pi BPI-F3 board.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Jesse Taube <jesse@rivosinc.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 0d678325444fc..f9b6ef4da589f 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -30,6 +30,7 @@ CONFIG_ARCH_MICROCHIP=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_SIFIVE=y
 CONFIG_ARCH_SOPHGO=y
+CONFIG_ARCH_SPACEMIT=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_THEAD=y

-- 
2.45.2

Re: [PATCH v5 08/10] riscv: dts: add initial SpacemiT K1 SoC device tree

[Jesse Taube]

On Mon, Jul 29, 2024 at 8:29 PM Yixun Lan <dlan@gentoo.org> wrote:
>
> From: Yangyu Chen <cyy@cyyself.name>
>
> Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
>
> Key features:
> - 4 cores per cluster, 2 clusters on chip
> - UART IP is Intel XScale UART
>
> Some key considerations:
> - ISA string is inferred from vendor documentation[2]
> - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> - No coherent DMA on this board
>     Inferred by taking vendor ethernet and MMC drivers to the mainline
>     kernel. Without dma-noncoherent in soc node, the driver fails.
> - Add cache nodes
>     K1 SoC has 128 sets of 32KiB L1 I/D Cache for each hart, and 512 sets
>     of 512KiB L2 Cache for each cluster.
>
> Currently only support booting into console with only uart, other
> features will be added soon later.
>
> Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>

Acked-by: Jesse Taube <jesse@rivosinc.com>

>
> ---
> Changes in v5:
>  - fix cache-sets
>  - Link to v4: https://lore.kernel.org/all/20240709-k1-01-basic-dt-v4-8-ae5bb5e56aaf@gentoo.org/
>
> Changes in v4:
>  - add i/d-cache, l2-cache info
>  - Link to v3: https://lore.kernel.org/all/20240703-k1-01-basic-dt-v3-8-12f73b47461e@gentoo.org/
> ---
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 459 +++++++++++++++++++++++++++++++++++
>  1 file changed, 459 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> new file mode 100644
> index 0000000000000..0777bf9e01183
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -0,0 +1,459 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +/dts-v1/;
> +/ {
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +       model = "SpacemiT K1";
> +       compatible = "spacemit,k1";
> +
> +       aliases {
> +               serial0 = &uart0;
> +               serial1 = &uart2;
> +               serial2 = &uart3;
> +               serial3 = &uart4;
> +               serial4 = &uart5;
> +               serial5 = &uart6;
> +               serial6 = &uart7;
> +               serial7 = &uart8;
> +               serial8 = &uart9;
> +       };
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               timebase-frequency = <24000000>;
> +
> +               cpu-map {
> +                       cluster0 {
> +                               core0 {
> +                                       cpu = <&cpu_0>;
> +                               };
> +                               core1 {
> +                                       cpu = <&cpu_1>;
> +                               };
> +                               core2 {
> +                                       cpu = <&cpu_2>;
> +                               };
> +                               core3 {
> +                                       cpu = <&cpu_3>;
> +                               };
> +                       };
> +
> +                       cluster1 {
> +                               core0 {
> +                                       cpu = <&cpu_4>;
> +                               };
> +                               core1 {
> +                                       cpu = <&cpu_5>;
> +                               };
> +                               core2 {
> +                                       cpu = <&cpu_6>;
> +                               };
> +                               core3 {
> +                                       cpu = <&cpu_7>;
> +                               };
> +                       };
> +               };
> +
> +               cpu_0: cpu@0 {
> +                       compatible = "spacemit,x60", "riscv";
> +                       device_type = "cpu";
> +                       reg = <0>;
> +                       riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                              "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                              "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                              "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                              "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                       riscv,cbom-block-size = <64>;
> +                       riscv,cbop-block-size = <64>;
> +                       riscv,cboz-block-size = <64>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <32768>;
> +                       i-cache-sets = <128>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <32768>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&cluster0_l2_cache>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu0_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu_1: cpu@1 {
> +                       compatible = "spacemit,x60", "riscv";
> +                       device_type = "cpu";
> +                       reg = <1>;
> +                       riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                              "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                              "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                              "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                              "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                       riscv,cbom-block-size = <64>;
> +                       riscv,cbop-block-size = <64>;
> +                       riscv,cboz-block-size = <64>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <32768>;
> +                       i-cache-sets = <128>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <32768>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&cluster0_l2_cache>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu1_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu_2: cpu@2 {
> +                       compatible = "spacemit,x60", "riscv";
> +                       device_type = "cpu";
> +                       reg = <2>;
> +                       riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                              "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                              "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                              "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                              "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                       riscv,cbom-block-size = <64>;
> +                       riscv,cbop-block-size = <64>;
> +                       riscv,cboz-block-size = <64>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <32768>;
> +                       i-cache-sets = <128>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <32768>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&cluster0_l2_cache>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu2_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu_3: cpu@3 {
> +                       compatible = "spacemit,x60", "riscv";
> +                       device_type = "cpu";
> +                       reg = <3>;
> +                       riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                              "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                              "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                              "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                              "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                       riscv,cbom-block-size = <64>;
> +                       riscv,cbop-block-size = <64>;
> +                       riscv,cboz-block-size = <64>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <32768>;
> +                       i-cache-sets = <128>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <32768>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&cluster0_l2_cache>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu3_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu_4: cpu@4 {
> +                       compatible = "spacemit,x60", "riscv";
> +                       device_type = "cpu";
> +                       reg = <4>;
> +                       riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                              "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                              "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                              "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                              "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                       riscv,cbom-block-size = <64>;
> +                       riscv,cbop-block-size = <64>;
> +                       riscv,cboz-block-size = <64>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <32768>;
> +                       i-cache-sets = <128>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <32768>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&cluster1_l2_cache>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu4_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu_5: cpu@5 {
> +                       compatible = "spacemit,x60", "riscv";
> +                       device_type = "cpu";
> +                       reg = <5>;
> +                       riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                              "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                              "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                              "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                              "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                       riscv,cbom-block-size = <64>;
> +                       riscv,cbop-block-size = <64>;
> +                       riscv,cboz-block-size = <64>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <32768>;
> +                       i-cache-sets = <128>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <32768>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&cluster1_l2_cache>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu5_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu_6: cpu@6 {
> +                       compatible = "spacemit,x60", "riscv";
> +                       device_type = "cpu";
> +                       reg = <6>;
> +                       riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                              "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                              "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                              "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                              "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                       riscv,cbom-block-size = <64>;
> +                       riscv,cbop-block-size = <64>;
> +                       riscv,cboz-block-size = <64>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <32768>;
> +                       i-cache-sets = <128>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <32768>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&cluster1_l2_cache>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu6_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu_7: cpu@7 {
> +                       compatible = "spacemit,x60", "riscv";
> +                       device_type = "cpu";
> +                       reg = <7>;
> +                       riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                              "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                              "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                              "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                              "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                       riscv,cbom-block-size = <64>;
> +                       riscv,cbop-block-size = <64>;
> +                       riscv,cboz-block-size = <64>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <32768>;
> +                       i-cache-sets = <128>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <32768>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&cluster1_l2_cache>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu7_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cluster0_l2_cache: l2-cache0 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <524288>;
> +                       cache-sets = <512>;
> +                       cache-unified;
> +               };
> +
> +               cluster1_l2_cache: l2-cache1 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <524288>;
> +                       cache-sets = <512>;
> +                       cache-unified;
> +               };
> +       };
> +
> +       soc {
> +               compatible = "simple-bus";
> +               interrupt-parent = <&plic>;
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               dma-noncoherent;
> +               ranges;
> +
> +               uart0: serial@d4017000 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017000 0x0 0x100>;
> +                       interrupts = <42>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               uart2: serial@d4017100 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017100 0x0 0x100>;
> +                       interrupts = <44>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               uart3: serial@d4017200 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017200 0x0 0x100>;
> +                       interrupts = <45>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               uart4: serial@d4017300 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017300 0x0 0x100>;
> +                       interrupts = <46>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               uart5: serial@d4017400 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017400 0x0 0x100>;
> +                       interrupts = <47>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               uart6: serial@d4017500 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017500 0x0 0x100>;
> +                       interrupts = <48>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               uart7: serial@d4017600 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017600 0x0 0x100>;
> +                       interrupts = <49>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               uart8: serial@d4017700 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017700 0x0 0x100>;
> +                       interrupts = <50>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               uart9: serial@d4017800 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xd4017800 0x0 0x100>;
> +                       interrupts = <51>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +
> +               plic: interrupt-controller@e0000000 {
> +                       compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> +                       reg = <0x0 0xe0000000 0x0 0x4000000>;
> +                       interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> +                                             <&cpu1_intc 11>, <&cpu1_intc 9>,
> +                                             <&cpu2_intc 11>, <&cpu2_intc 9>,
> +                                             <&cpu3_intc 11>, <&cpu3_intc 9>,
> +                                             <&cpu4_intc 11>, <&cpu4_intc 9>,
> +                                             <&cpu5_intc 11>, <&cpu5_intc 9>,
> +                                             <&cpu6_intc 11>, <&cpu6_intc 9>,
> +                                             <&cpu7_intc 11>, <&cpu7_intc 9>;
> +                       interrupt-controller;
> +                       #address-cells = <0>;
> +                       #interrupt-cells = <1>;
> +                       riscv,ndev = <159>;
> +               };
> +
> +               clint: timer@e4000000 {
> +                       compatible = "spacemit,k1-clint", "sifive,clint0";
> +                       reg = <0x0 0xe4000000 0x0 0x10000>;
> +                       interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> +                                             <&cpu1_intc 3>, <&cpu1_intc 7>,
> +                                             <&cpu2_intc 3>, <&cpu2_intc 7>,
> +                                             <&cpu3_intc 3>, <&cpu3_intc 7>,
> +                                             <&cpu4_intc 3>, <&cpu4_intc 7>,
> +                                             <&cpu5_intc 3>, <&cpu5_intc 7>,
> +                                             <&cpu6_intc 3>, <&cpu6_intc 7>,
> +                                             <&cpu7_intc 3>, <&cpu7_intc 7>;
> +               };
> +
> +               sec_uart1: serial@f0612000 {
> +                       compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                       reg = <0x0 0xf0612000 0x0 0x100>;
> +                       interrupts = <43>;
> +                       clock-frequency = <14857000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "reserved"; /* for TEE usage */
> +               };
> +       };
> +};
>
> --
> 2.45.2
>

Re: [PATCH v5 09/10] riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree

[Jesse Taube]

On Mon, Jul 29, 2024 at 8:29 PM Yixun Lan <dlan@gentoo.org> wrote:
>
> From: Yangyu Chen <cyy@cyyself.name>
>
> Banana Pi BPI-F3 [1] is a industrial grade RISC-V development board, it
> design with SpacemiT K1 8 core RISC-V chip [2].
>
> Currently only support booting into console with only uart enabled,
> other features will be added soon later.
>
> Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [1]
> Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [2]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
Acked-by: Jesse Taube <jesse@rivosinc.com>

> ---
>  arch/riscv/boot/dts/Makefile                    |  1 +
>  arch/riscv/boot/dts/spacemit/Makefile           |  2 ++
>  arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 19 +++++++++++++++++++
>  3 files changed, 22 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index fdae05bbf5563..bff887d38abe4 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -5,6 +5,7 @@ subdir-y += microchip
>  subdir-y += renesas
>  subdir-y += sifive
>  subdir-y += sophgo
> +subdir-y += spacemit
>  subdir-y += starfive
>  subdir-y += thead
>
> diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
> new file mode 100644
> index 0000000000000..ac617319a5742
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-f3.dtb
> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> new file mode 100644
> index 0000000000000..023274189b492
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k1.dtsi"
> +
> +/ {
> +       model = "Banana Pi BPI-F3";
> +       compatible = "bananapi,bpi-f3", "spacemit,k1";
> +
> +       chosen {
> +               stdout-path = "serial0";
> +       };
> +};
> +
> +&uart0 {
> +       status = "okay";
> +};
>
> --
> 2.45.2
>

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Palmer Dabbelt]

On Mon, 29 Jul 2024 17:28:03 PDT (-0700), dlan@gentoo.org wrote:
> SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
> 1.0 and Zicond evaluation now. Add initial support for it to allow more
> people to participate in building drivers to mainline for it.
>
> This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
> bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
> Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
> booted to busybox on initrd with this log[3].
>
> As previous discussion in patch v1[4], maintainer expect more basic drivers
> ready before really merging it, which would be fine. For other follow-up patches,
> that are clk, pinctrl/gpio, reset.. My current goal would target at a headless
> system including SD card, emmc, and ethernet.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

if you guys want to take this through some SOC tree.  I'm not really 
sure what the bar is for SOC support to get merged, but I'd be happy to 
just see this booting at all -- we've got a bunch of them floating 
around and the vendor kernels are pretty crusty, so anything's an 
improvement on my end.

> In this series, the uart node has no 'fifo-size', 'tx-threshold' property populated,
> will add them once this patch is resolved, see thread [5]
>
> P.S: talked to Yangyu, I will help and take care of this patch series, thanks
>
> ---
> Changes in v5:
> - fix cache-sets in dts
> - collect Rob's Ack
> - rebase to 6.11-rc1
> - Link to v4: https://lore.kernel.org/r/20240709-k1-01-basic-dt-v4-0-ae5bb5e56aaf@gentoo.org
>
> Changes in v4:
>  - add i/d-cache, l2-cache info
>  - squash uart1 dts node
>  - update tags
>  - Link to v3: https://lore.kernel.org/r/20240703-k1-01-basic-dt-v3-0-12f73b47461e@gentoo.org
>
> Changes in v3:
>  - fix dt_binding_check error
>  - fix plic compatible
>  - fix uart node name
>  - add uart1 dts node
>  - collect tags
>  - Link to v2: https://lore.kernel.org/r/20240627-k1-01-basic-dt-v2-0-cc06c7555f07@gentoo.org
>
> Changes in v2:
>  - fix timebase-frequency according to current setting
>  - add other uart dt nodes, fix input frequency
>  - introduce new uart compatible for K1 SoC
>  - add 'k1' prefix to bananapi-f3.dts
>  - fix k1-clint compatible
>  - fix some typos
>  - Link to v1: https://lore.kernel.org/r/tencent_BC64B7B1876F5D10479BD19112F73F262505@qq.com
>
> Link: https://github.com/BPI-SINOVOIP/armbian-build/tree/v24.04.30 [1]
> Link: https://gist.github.com/cyyself/a07096e6e99c949ed13f8fa16d884402 [2]
> Link: https://gist.github.com/cyyself/a2201c01f5c8955a119641f97b7d0280 [3]
> Link: https://lore.kernel.org/r/20240618-hardwood-footrest-ab5ec5bce3cf@wendy [4]
> Link: https://lore.kernel.org/linux-riscv/20240706082928.2238-1-jszhang@kernel.org/ [5]
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
>
> ---
> Yangyu Chen (9):
>       dt-bindings: vendor-prefixes: add spacemit
>       dt-bindings: riscv: Add SpacemiT X60 compatibles
>       dt-bindings: riscv: add SpacemiT K1 bindings
>       dt-bindings: timer: Add SpacemiT K1 CLINT
>       dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
>       riscv: add SpacemiT SoC family Kconfig support
>       riscv: dts: add initial SpacemiT K1 SoC device tree
>       riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
>       riscv: defconfig: enable SpacemiT SoC
>
> Yixun Lan (1):
>       dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
>
>  .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
>  Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
>  .../devicetree/bindings/riscv/spacemit.yaml        |  28 ++
>  Documentation/devicetree/bindings/serial/8250.yaml |   4 +-
>  .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
>  .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
>  arch/riscv/Kconfig.socs                            |   5 +
>  arch/riscv/boot/dts/Makefile                       |   1 +
>  arch/riscv/boot/dts/spacemit/Makefile              |   2 +
>  arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts    |  19 +
>  arch/riscv/boot/dts/spacemit/k1.dtsi               | 459 +++++++++++++++++++++
>  arch/riscv/configs/defconfig                       |   1 +
>  12 files changed, 523 insertions(+), 1 deletion(-)
> ---
> base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b
> change-id: 20240626-k1-01-basic-dt-1aa31eeebcd2
>
> Best regards,

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2755 bytes --]

On Tue, Sep 17, 2024 at 06:04:29AM -0700, Palmer Dabbelt wrote:
> On Mon, 29 Jul 2024 17:28:03 PDT (-0700), dlan@gentoo.org wrote:
> > SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
> > 1.0 and Zicond evaluation now. Add initial support for it to allow more
> > people to participate in building drivers to mainline for it.
> > 
> > This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
> > bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
> > Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
> > booted to busybox on initrd with this log[3].
> > 
> > As previous discussion in patch v1[4], maintainer expect more basic drivers
> > ready before really merging it, which would be fine. For other follow-up patches,
> > that are clk, pinctrl/gpio, reset.. My current goal would target at a headless
> > system including SD card, emmc, and ethernet.
> 
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> if you guys want to take this through some SOC tree.  I'm not really sure
> what the bar is for SOC support to get merged, but I'd be happy to just see
> this booting at all -- we've got a bunch of them floating around and the
> vendor kernels are pretty crusty, so anything's an improvement on my end.

I've asked for clock and ideally pinctrl support before merging it. We
had a conversation about the usefulness etc of some of the initial
devicetrees merged for some platforms a few months back, that lead to me
not merging the k230 support I had queued up. I know this isn't exactly
a "fair" barrier to entry, as it is likely that platforms supported by
hobbyists are going to be more affected than companies that usually come
with that basic level, but have to draw a line somewhere.
Both clock and pinctrl are currently in progress for the k1, hopefully
wont take too much longer before this is mergeable.

In other news, nobody has really made an "official" statement about who
is going to maintain this particular platform. People have expressed
interest (including the submitter of the series, IIRC) but there's no
MAINTAINERS entry added here AFAICT. I used to have an entry that
covered arch/riscv/boot/dts/*, with exclusions for sunxi and renesas,
but with Drew taking on thead and sophgo being the resぽonsibility of
Chen Wang and Inochi, I no longer have that wildcard.

I'm happy to apply patches for the platform if noone else is interested
in that side of things, provided there are willing reviewers, but I
would much rather that someone else took up the responsibility of
applying patches and sending PRs - and of course I am happy to help
whoever that is with the process.

Cheers,
Conor.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1923 bytes --]

On Tue, Sep 17, 2024 at 10:08:03PM +0100, Conor Dooley wrote:
> In other news, nobody has really made an "official" statement about who
> is going to maintain this particular platform. People have expressed
> interest (including the submitter of the series, IIRC) but there's no
> MAINTAINERS entry added here AFAICT. I used to have an entry that
> covered arch/riscv/boot/dts/*, with exclusions for sunxi and renesas,
> but with Drew taking on thead and sophgo being the resぽonsibility of
> Chen Wang and Inochi, I no longer have that wildcard.
> 
> I'm happy to apply patches for the platform if noone else is interested
> in that side of things, provided there are willing reviewers, but I
> would much rather that someone else took up the responsibility of
> applying patches and sending PRs - and of course I am happy to help
> whoever that is with the process.

On second thoughts (and on a second opinion) I am not actually willing
to apply patches for this platform, since it isn't sustainable to take
on each and every platform that there's no maintainer for.

+CC a few more people that have been involved in the platform.

Yixun Lan, you're kinda the "prime" person to maintain the platform
since you're the one who took up the core support work etc. Is
maintaining the platform, maybe with the help of one of the other folks
working on it something you can do?

Mostly the responsibilities are just applying patches for fixes/new
content and sending PRs to the soc maintainers - but knowing what's
right or not obviously requires familiarity with the platform which
people that work on it are best placed to do. Myself and the soc
maintainers will help if whoever does this runs into any trouble.
There is some documentation here https://docs.kernel.org/process/maintainer-soc.html
that will assist somewhat with getting up to speed with the process
also.

Cheers,
Conor.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Yixun Lan]

Hi Conor:

On 18:24 Fri 18 Oct     , Conor Dooley wrote:
> On Tue, Sep 17, 2024 at 10:08:03PM +0100, Conor Dooley wrote:
> > In other news, nobody has really made an "official" statement about who
> > is going to maintain this particular platform. People have expressed
> > interest (including the submitter of the series, IIRC) but there's no
> > MAINTAINERS entry added here AFAICT. I used to have an entry that
> > covered arch/riscv/boot/dts/*, with exclusions for sunxi and renesas,
> > but with Drew taking on thead and sophgo being the resぽonsibility of
> > Chen Wang and Inochi, I no longer have that wildcard.
> > 
> > I'm happy to apply patches for the platform if noone else is interested
> > in that side of things, provided there are willing reviewers, but I
> > would much rather that someone else took up the responsibility of
> > applying patches and sending PRs - and of course I am happy to help
> > whoever that is with the process.
> 
> On second thoughts (and on a second opinion) I am not actually willing
> to apply patches for this platform, since it isn't sustainable to take
> on each and every platform that there's no maintainer for.
> 
Ok, I fully understand your concern..

> +CC a few more people that have been involved in the platform.
> 
> Yixun Lan, you're kinda the "prime" person to maintain the platform
> since you're the one who took up the core support work etc. Is
> maintaining the platform, maybe with the help of one of the other folks
> working on it something you can do?
> 
That would be sweet, yes, I can take the maintainer responsibitly for now
but, I'm open if someone else willing to help and co-maintain..

> Mostly the responsibilities are just applying patches for fixes/new
> content and sending PRs to the soc maintainers - but knowing what's
> right or not obviously requires familiarity with the platform which
> people that work on it are best placed to do. Myself and the soc
> maintainers will help if whoever does this runs into any trouble.
> There is some documentation here https://docs.kernel.org/process/maintainer-soc.html
> that will assist somewhat with getting up to speed with the process
> also.
> 
Great, thanks for the info
> Cheers,
> Conor.

last, one question I'd raise:

for this particular patch series, do you want me to send another version v6
which can update the MAINTAINERS file (nothing changed with the code)

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (fixes)
by Conor Dooley <conor.dooley@microchip.com>:

On Tue, 30 Jul 2024 00:28:03 +0000 you wrote:
> SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
> 1.0 and Zicond evaluation now. Add initial support for it to allow more
> people to participate in building drivers to mainline for it.
> 
> This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
> bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
> Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
> booted to busybox on initrd with this log[3].
> 
> [...]

Here is the summary with links:
  - [v5,01/10] dt-bindings: vendor-prefixes: add spacemit
    https://git.kernel.org/riscv/c/7cf3e9bfc63d
  - [v5,02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles
    (no matching commit)
  - [v5,03/10] dt-bindings: riscv: add SpacemiT K1 bindings
    (no matching commit)
  - [v5,04/10] dt-bindings: timer: Add SpacemiT K1 CLINT
    (no matching commit)
  - [v5,05/10] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
    (no matching commit)
  - [v5,06/10] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
    (no matching commit)
  - [v5,07/10] riscv: add SpacemiT SoC family Kconfig support
    (no matching commit)
  - [v5,08/10] riscv: dts: add initial SpacemiT K1 SoC device tree
    (no matching commit)
  - [v5,09/10] riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
    (no matching commit)
  - [v5,10/10] riscv: defconfig: enable SpacemiT SoC
    (no matching commit)

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Yixun Lan]

Hi Conor:

On 22:33 Wed 11 Dec     , patchwork-bot+linux-riscv@kernel.org wrote:
> Hello:
> 
> This series was applied to riscv/linux.git (fixes)
> by Conor Dooley <conor.dooley@microchip.com>:
> 
> On Tue, 30 Jul 2024 00:28:03 +0000 you wrote:
> > SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
> > 1.0 and Zicond evaluation now. Add initial support for it to allow more
> > people to participate in building drivers to mainline for it.
> > 
> > This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
> > bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
> > Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
> > booted to busybox on initrd with this log[3].
> > 
> > [...]
> 
> Here is the summary with links:
>   - [v5,01/10] dt-bindings: vendor-prefixes: add spacemit
>     https://git.kernel.org/riscv/c/7cf3e9bfc63d
If I understand correctly, only patch [01/10] of this series was accepted
to 6.13-rc1

for the rest of patches, they would be expected to go through SpacemiT's
SoC tree? which should I take care of them.. so if no objection, I'd like to
queue them at branch k1/dt-for-next [1] first, we might rebase or revert if
something happens before merging (since the clock driver is still under review)

Let me know what you think..

Link: https://github.com/spacemit-com/linux/tree/k1/dt-for-next [1]
 

>   - [v5,02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles
>     (no matching commit)
>   - [v5,03/10] dt-bindings: riscv: add SpacemiT K1 bindings
>     (no matching commit)
>   - [v5,04/10] dt-bindings: timer: Add SpacemiT K1 CLINT
>     (no matching commit)
>   - [v5,05/10] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
>     (no matching commit)
>   - [v5,06/10] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
>     (no matching commit)
>   - [v5,07/10] riscv: add SpacemiT SoC family Kconfig support
>     (no matching commit)
>   - [v5,08/10] riscv: dts: add initial SpacemiT K1 SoC device tree
>     (no matching commit)
>   - [v5,09/10] riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
>     (no matching commit)
>   - [v5,10/10] riscv: defconfig: enable SpacemiT SoC
>     (no matching commit)
> 
> You are awesome, thank you!
> -- 
> Deet-doot-dot, I am a bot.
> https://korg.docs.kernel.org/patchwork/pwbot.html
> 
> 

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1681 bytes --]

On Thu, Dec 12, 2024 at 06:19:01PM +0800, Yixun Lan wrote:
> Hi Conor:
> 
> On 22:33 Wed 11 Dec     , patchwork-bot+linux-riscv@kernel.org wrote:
> > Hello:
> > 
> > This series was applied to riscv/linux.git (fixes)
> > by Conor Dooley <conor.dooley@microchip.com>:
> > 
> > On Tue, 30 Jul 2024 00:28:03 +0000 you wrote:
> > > SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
> > > 1.0 and Zicond evaluation now. Add initial support for it to allow more
> > > people to participate in building drivers to mainline for it.
> > > 
> > > This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
> > > bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
> > > Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
> > > booted to busybox on initrd with this log[3].
> > > 
> > > [...]
> > 
> > Here is the summary with links:
> >   - [v5,01/10] dt-bindings: vendor-prefixes: add spacemit
> >     https://git.kernel.org/riscv/c/7cf3e9bfc63d
> If I understand correctly, only patch [01/10] of this series was accepted
> to 6.13-rc1
> 
> for the rest of patches, they would be expected to go through SpacemiT's
> SoC tree? which should I take care of them.. so if no objection, I'd like to
> queue them at branch k1/dt-for-next [1] first, we might rebase or revert if
> something happens before merging (since the clock driver is still under review)
> 
> Let me know what you think..

Sure. I had grabbed the first patch because a couple trees needed the
vendor prefix for peripheral drivers. How is the clock driver getting
on? Do you think it is close to being merged?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Yixun Lan]

Hi Conor:

On 15:04 Sun 15 Dec     , Conor Dooley wrote:
> On Thu, Dec 12, 2024 at 06:19:01PM +0800, Yixun Lan wrote:
> > Hi Conor:
> > 
> > On 22:33 Wed 11 Dec     , patchwork-bot+linux-riscv@kernel.org wrote:
> > > Hello:
> > > 
> > > This series was applied to riscv/linux.git (fixes)
> > > by Conor Dooley <conor.dooley@microchip.com>:
> > > 
> > > On Tue, 30 Jul 2024 00:28:03 +0000 you wrote:
> > > > SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
> > > > 1.0 and Zicond evaluation now. Add initial support for it to allow more
> > > > people to participate in building drivers to mainline for it.
> > > > 
> > > > This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
> > > > bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
> > > > Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
> > > > booted to busybox on initrd with this log[3].
> > > > 
> > > > [...]
> > > 
> > > Here is the summary with links:
> > >   - [v5,01/10] dt-bindings: vendor-prefixes: add spacemit
> > >     https://git.kernel.org/riscv/c/7cf3e9bfc63d
> > If I understand correctly, only patch [01/10] of this series was accepted
> > to 6.13-rc1
> > 
> > for the rest of patches, they would be expected to go through SpacemiT's
> > SoC tree? which should I take care of them.. so if no objection, I'd like to
> > queue them at branch k1/dt-for-next [1] first, we might rebase or revert if
> > something happens before merging (since the clock driver is still under review)
> > 
> > Let me know what you think..
> 
> Sure. I had grabbed the first patch because a couple trees needed the

No problem, thanks for helping on this

> vendor prefix for peripheral drivers. How is the clock driver getting
> on? Do you think it is close to being merged?

The clock driver's review is still on-going, the biggest concern is about
the mix clock implementation [1], which isn't decent, and Haylen's working on
to have a better version, I'd hope we can catch this in 6.14's merge window..

But, in the worst case if we have to postpone clock to next merge window,
would you think it's ok to push the basic dts and pinctrl dts first?
IMHO, they have no hard dependency on clock driver, and pushing them
first would simplify the future developement..

http://lore.kernel.org/r/Z2LBsQ7a3T3mElLl@ketchup [1]

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: (subset) [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[Yixun Lan]

On Tue, 30 Jul 2024 00:28:03 +0000, Yixun Lan wrote:
> SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
> 1.0 and Zicond evaluation now. Add initial support for it to allow more
> people to participate in building drivers to mainline for it.
> 
> This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
> bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
> Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
> booted to busybox on initrd with this log[3].
> 
> [...]

Thanks, Applied to SpacemiT's SoC tree:
 https://github.com/spacemit-com/linux/ (for-next)

[02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles
        commit: edc6b9c55460d978dd0225621b8e3a2892bd53b8
[03/10] dt-bindings: riscv: add SpacemiT K1 bindings
        commit: c3eb7abb15c24ddb3b7ffdc60ab5861901245e7f
[04/10] dt-bindings: timer: Add SpacemiT K1 CLINT
        commit: a924f3f93128b5d0b5f8022862a296752284841a
[05/10] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
        commit: ea2190065a7d5cbf8a0f1e9296680e9f8f2fbcd2
[06/10] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
        commit: 85d542534dd283ba61fb89a20fa0f88d1a415f6b
[07/10] riscv: add SpacemiT SoC family Kconfig support
        commit: c50358c6af12812a7c23f8cf581eea4a43b3c8f2
[08/10] riscv: dts: add initial SpacemiT K1 SoC device tree
        commit: 8f4b270c7819440c504d87a13806333555b38bd6
[09/10] riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
        commit: f68191069c0c3c56bb77ece28ff15c09e7a01dfa
[10/10] riscv: defconfig: enable SpacemiT SoC
        commit: 6be78731556d5686eac8e539b6acf0449280e389

The for-next branch will be sent via a formal Pull Request to
the Linux SoC maintainers for inclusion in next merge window.

Best regards,
-- 
Yixun Lan

Re: [PATCH v5 00/10] riscv: add initial support for SpacemiT K1

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (fixes)
by Yixun Lan <dlan@gentoo.org>:

On Tue, 30 Jul 2024 00:28:03 +0000 you wrote:
> SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
> 1.0 and Zicond evaluation now. Add initial support for it to allow more
> people to participate in building drivers to mainline for it.
> 
> This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
> bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
> Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
> booted to busybox on initrd with this log[3].
> 
> [...]

Here is the summary with links:
  - [v5,01/10] dt-bindings: vendor-prefixes: add spacemit
    (no matching commit)
  - [v5,02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles
    https://git.kernel.org/riscv/c/16c9147e6a6c
  - [v5,03/10] dt-bindings: riscv: add SpacemiT K1 bindings
    https://git.kernel.org/riscv/c/244fe889b950
  - [v5,04/10] dt-bindings: timer: Add SpacemiT K1 CLINT
    https://git.kernel.org/riscv/c/e5164af2a2fe
  - [v5,05/10] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
    https://git.kernel.org/riscv/c/562272a287d5
  - [v5,06/10] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
    https://git.kernel.org/riscv/c/dfe6d083edff
  - [v5,07/10] riscv: add SpacemiT SoC family Kconfig support
    https://git.kernel.org/riscv/c/8814aa123adb
  - [v5,08/10] riscv: dts: add initial SpacemiT K1 SoC device tree
    https://git.kernel.org/riscv/c/d8fe64691955
  - [v5,09/10] riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
    https://git.kernel.org/riscv/c/d60d57ab6b2a
  - [v5,10/10] riscv: defconfig: enable SpacemiT SoC
    https://git.kernel.org/riscv/c/21bef40ad121

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html