From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2CA626AA83; Fri, 28 Feb 2025 12:25:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740745512; cv=none; b=LpxhElCC4kjNIFJnmY64HOH+FmB+HEsw1hpdyUGJnuWFy8wnpwHZ04lpYH6FHBEFu4XodANpb0d962cYzFYCzufR6W/T7BYuRE0PzeotPovnQKvR4PNNQq2uRAZ7fkuNWnitN11CiGo3sgF9+V7C5BXjT5jvWDjifLraXAE/+Sw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740745512; c=relaxed/simple; bh=8xUimPw6k9q65+hF485fj/0AqnwZJKhGHir+ktIZLPI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=AcoC2WyqchRCNkOGANFTyTUvKD0XP4n/jn8VvOL1z/32e9nQ9ECOlM/4/bPtyLkL4FqjV/8R1D7NGj0bis/yV6UjkXGf3WMfObJJ65xKfTm2VMXJD2gGzJwgvaTK+i7+lvBvlcuNhnwlIMClzA72FdOgheXlVbIcI3Dk9mUgCwU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f+LfRLrw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f+LfRLrw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1C7A1C4CED6; Fri, 28 Feb 2025 12:25:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740745512; bh=8xUimPw6k9q65+hF485fj/0AqnwZJKhGHir+ktIZLPI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=f+LfRLrw+TXG2vm0sDdtVDrAtD/TQmOeDHr4QC8Whf1R2tJuFBvXnzIycRY2KJF0K z33WOOtp+MXMqPWAm1KMVhF5iQOqQfdtdVft7rT5PsVWQDWTUS88CiIoimBX2Erjdf mZ8AUHJcObU9AdODGCdsOuA0nnli58kvWj/YNM1Q7K8RhECd+BZNgXz1krZzsGnhML 7DbB8Uy7zReNcDgDTZ/rpNDuT1vKVnTePpQ9RMXCGRAPzVM9+VBSaIj3KacGC6TvTI dG4jYsZIyOLj2vv153M0Dfiw/RrH7GM8pmpz3DgOrYpqMced1CKUiOMDXHqAW+oAee zZTDI8Iv8OSPg== Date: Fri, 28 Feb 2025 06:25:10 -0600 From: "Rob Herring (Arm)" To: Marek Vasut Cc: Philipp Zabel , Sascha Hauer , Boris Brezillon , Fabio Estevam , Steven Price , Thomas Zimmermann , Simona Vetter , David Airlie , Pengutronix Kernel Team , imx@lists.linux.dev, Conor Dooley , Maarten Lankhorst , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Liviu Dudau , Maxime Ripard , Sebastian Reichel , Shawn Guo Subject: Re: [PATCH 3/9] dt-bindings: gpu: mali-valhall-csf: Document optional reset Message-ID: <174074550945.2320385.13428412876070691467.robh@kernel.org> References: <20250227170012.124768-1-marex@denx.de> <20250227170012.124768-4-marex@denx.de> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250227170012.124768-4-marex@denx.de> On Thu, 27 Feb 2025 17:58:03 +0100, Marek Vasut wrote: > The instance of the GPU populated in Freescale i.MX95 does require > release from reset by writing into a single GPUMIX block controller > GPURESET register bit 0. Document support for one optional reset. > > Signed-off-by: Marek Vasut > --- > Cc: Boris Brezillon > Cc: Conor Dooley > Cc: David Airlie > Cc: Fabio Estevam > Cc: Krzysztof Kozlowski > Cc: Liviu Dudau > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Pengutronix Kernel Team > Cc: Philipp Zabel > Cc: Rob Herring > Cc: Sascha Hauer > Cc: Sebastian Reichel > Cc: Shawn Guo > Cc: Simona Vetter > Cc: Steven Price > Cc: Thomas Zimmermann > Cc: devicetree@vger.kernel.org > Cc: dri-devel@lists.freedesktop.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 3 +++ > 1 file changed, 3 insertions(+) > Acked-by: Rob Herring (Arm)