From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: matthew.gerlach@linux.intel.com, dinguyen@kernel.org,
robh+dt@kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org
Subject: Re: [PATCH v2 1/3] dt-bindings: misc: add bindings for Intel HPS Copy Engine
Date: Wed, 4 May 2022 17:04:52 +0200 [thread overview]
Message-ID: <17407fe7-b11d-2ba8-acca-3e71cf1a3b2f@linaro.org> (raw)
In-Reply-To: <20220503194546.1287679-2-matthew.gerlach@linux.intel.com>
On 03/05/2022 21:45, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Add device tree bindings documentation for the Intel Hard
> Processor System (HPS) Copy Engine.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
> .../bindings/misc/intel,hps-copy-engine.yaml | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml
>
> diff --git a/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml b/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml
> new file mode 100644
> index 000000000000..74e7da9002f4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml
Please find appropriate directory matching this hardware, not "misc". As
a fallback SoC related bindings end up in "soc".
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2022, Intel Corporation
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/misc/intel,hps-copy-engine.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Intel HPS Copy Engine
> +
> +maintainers:
> + - Matthew Gerlach <matthew.gerlach@linux.intel.com>
> +
> +description: |
> + The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
> + a bootable image from host memory to HPS DDR. Additionally, there is a
> + register the HPS can use to indicate the state of booting the copied image as
> + well as a keep-a-live indication to the host.
> +
> +properties:
> + compatible:
> + items:
No "items", you have just one item.
> + - const: intel,hps-copy-engine
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + agilex_hps_bridges: bus@80000000 {
Unused label...
> + compatible = "simple-bus";
> + reg = <0x80000000 0x60000000>,
> + <0xf9000000 0x00100000>;
> + reg-names = "axi_h2f", "axi_h2f_lw";
> + #address-cells = <0x2>;
$ git grep address-cell
Do not use inconsistent coding. The same applies to your DTS.
> + #size-cells = <0x1>;
> + ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
Why do you even need the simple-bus above and cannot put the device
directly on the bus?
> +
> + hps_cp_eng@0 {
No underscores in node names. Generic node name.
> + compatible = "intel,hps-copy-engine";
> + reg = <0x00000000 0x00000000 0x00001000>;
> + };
> + };
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-05-04 15:05 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-03 19:45 [PATCH v2 0/3] Add device tree for Intel n6000 matthew.gerlach
2022-05-03 19:45 ` [PATCH v2 1/3] dt-bindings: misc: add bindings for Intel HPS Copy Engine matthew.gerlach
2022-05-04 15:04 ` Krzysztof Kozlowski [this message]
2022-05-04 22:41 ` matthew.gerlach
2022-05-05 8:18 ` Krzysztof Kozlowski
2022-05-05 17:18 ` matthew.gerlach
2022-05-03 19:45 ` [PATCH v2 2/3] dt-bindings: intel: add binding for Intel n6000 matthew.gerlach
2022-05-04 14:54 ` Krzysztof Kozlowski
2022-05-04 21:09 ` matthew.gerlach
2022-05-03 19:45 ` [PATCH v2 3/3] arm64: dts: intel: add device tree for n6000 matthew.gerlach
2022-05-04 14:56 ` Krzysztof Kozlowski
2022-05-04 21:14 ` matthew.gerlach
2022-05-04 15:02 ` Krzysztof Kozlowski
2022-05-04 21:22 ` matthew.gerlach
2022-05-05 6:42 ` Krzysztof Kozlowski
2022-05-05 17:16 ` matthew.gerlach
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