[PATCH v3 0/4] dt-bindings: mtd: microchip-nand: convert txt to yaml

[PATCH v3 0/4] dt-bindings: mtd: microchip-nand: convert txt to yaml

[Balamanikandan Gunasundar]

Convert microchip nand controllers from text to yaml

Summary of changes:

Note:
- The changes are made on top of v6.15. 

v2 -> v3:

[PATCH 1/4] dt-bindings: mtd: microchip-nand: convert txt to yaml
- Remove pmecc nodes in example as it has a seperate binding

[PATCH 2/4] dt-bindings: mtd: microchip-nand: add atmel pmecc
- Dropped '|' from description
- Merged the fallback compatibles
- Dropped 'base address and size of' from description
- Dropeed clock source description
- Modifed if/then condition. the clock source is only required for sam9x7
 
[PATCH 3/4] dt-bindings: mtd: atmel-nand: add legacy nand
- Dropped '|' from description
- Fix address-cells and size-cells ranges
- Define each gpio entry. RB, CE and CD
- Move vendor specific properties to last.
- Fix node names in examples.

[PATCH 4/4] MAINTAINERS: add entry for microchip nand controller
- New patch updating myself as maintainer.

v1 -> v2:

https://lore.kernel.org/all/20250311122847.90081-1-balamanikandan.gunasundar@microchip.com/

[PATCH 1/3] dt-bindings: mtd: microchip-nand: convert txt to yaml
- Change the filename to match the compatible string
- Drop items and oneOf in the compatible property as it is just an enum
- Remove the if in the #address-cells and #size-cells
- Remove the unwanted comments that refers to .txt files
- Fix reg property description
- Define the properties in a list and add constraints
- Fix DT coding style and droped unused labels

[PATCH 2/3] dt-bindings: mtd: microchip-nand: add atmel pmecc
- Rename filename to match compatible string
- Add constraints for sam9x7
- Droped unused dt labels 

[PATCH 3/3] dt-bindings: mtd: atmel-nand: add legacy nand
- Filename matching the compatibles
- Remove "bindings" from the subject
- Remove "deprecated" as these are the only bindings available for the devices
- Add missing constraints.
- Add default for nand-ecc-mode
- Add 32 in pmecc-cap for sama5d2
- Add default for sector-size, pmecc-lookup-table-offset, nand-bus-width

Balamanikandan Gunasundar (4):
  dt-bindings: mtd: microchip-nand: convert txt to yaml
  dt-bindings: mtd: microchip-nand: add atmel pmecc
  dt-bindings: mtd: atmel-nand: add legacy nand controllers
  MAINTAINERS: add entry for microchip nand controller

 .../devicetree/bindings/mtd/atmel-nand.txt    | 227 ------------------
 .../devicetree/bindings/mtd/atmel-nand.yaml   | 167 +++++++++++++
 .../mtd/microchip,nand-controller.yaml        | 169 +++++++++++++
 .../bindings/mtd/microchip,pmecc.yaml         |  62 +++++
 MAINTAINERS                                   |   5 +-
 5 files changed, 401 insertions(+), 229 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.yaml
 create mode 100644 Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
 create mode 100644 Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml

-- 
2.34.1

[PATCH v3 1/4] dt-bindings: mtd: microchip-nand: convert txt to yaml

[Balamanikandan Gunasundar]

Convert text to yaml for microchip nand controller

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
---
 .../devicetree/bindings/mtd/atmel-nand.txt    |  50 ------
 .../mtd/microchip,nand-controller.yaml        | 169 ++++++++++++++++++
 2 files changed, 169 insertions(+), 50 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index e36c35b17873..dbbc17a866f2 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -1,53 +1,3 @@
-Atmel NAND flash controller bindings
-
-The NAND flash controller node should be defined under the EBI bus (see
-Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
-One or several NAND devices can be defined under this NAND controller.
-The NAND controller might be connected to an ECC engine.
-
-* NAND controller bindings:
-
-Required properties:
-- compatible: should be one of the following
-	"atmel,at91rm9200-nand-controller"
-	"atmel,at91sam9260-nand-controller"
-	"atmel,at91sam9261-nand-controller"
-	"atmel,at91sam9g45-nand-controller"
-	"atmel,sama5d3-nand-controller"
-	"microchip,sam9x60-nand-controller"
-- ranges: empty ranges property to forward EBI ranges definitions.
-- #address-cells: should be set to 2.
-- #size-cells: should be set to 1.
-- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
-		controllers.
-- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
-		  controllers.
-
-Optional properties:
-- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
-	      a PMECC engine.
-
-* NAND device/chip bindings:
-
-Required properties:
-- reg: describes the CS lines assigned to the NAND device. If the NAND device
-       exposes multiple CS lines (multi-dies chips), your reg property will
-       contain X tuples of 3 entries.
-       1st entry: the CS line this NAND chip is connected to
-       2nd entry: the base offset of the memory region assigned to this
-		  device (always 0)
-       3rd entry: the memory region size (always 0x800000)
-
-Optional properties:
-- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
-- cs-gpios: the GPIO(s) used to control the CS line.
-- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
-- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
-	    on sama5 SoCs.
-
-All generic properties are described in the generic yaml files under
-Documentation/devicetree/bindings/mtd/.
-
 * ECC engine (PMECC) bindings:
 
 Required properties:
diff --git a/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
new file mode 100644
index 000000000000..2b0d03343611
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/microchip,nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip NAND flash controller
+
+maintainers:
+  - Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
+
+description: |
+  The NAND flash controller node should be defined under the EBI bus (see
+  Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
+  One or several NAND devices can be defined under this NAND controller.
+  The NAND controller might be connected to an ECC engine.
+
+properties:
+  compatible:
+    enum:
+      - atmel,at91rm9200-nand-controller
+      - atmel,at91sam9260-nand-controller
+      - atmel,at91sam9261-nand-controller
+      - atmel,at91sam9g45-nand-controller
+      - atmel,sama5d3-nand-controller
+      - microchip,sam9x60-nand-controller
+
+  ranges:
+    description: empty ranges property to forward EBI ranges definitions.
+
+  ecc-engine:
+    description:
+      phandle to the PMECC block. Only meaningful if the SoC embeds a PMECC
+      engine. Refer microchip,pmecc.yaml
+
+  "#address-cells":
+    const: 2
+
+  "#size-cells":
+    const: 1
+
+  atmel,nfc-io:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the NFC IO block. Only applicable for atmel,sama5d3-nand-controller
+
+  atmel,nfc-sram:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the NFC SRAM block. Only applicable for atmel,sama5d3-nand-controller
+
+required:
+  - compatible
+  - ranges
+  - "#address-cells"
+  - "#size-cells"
+
+patternProperties:
+  "^nand@[a-f0-9]$":
+    type: object
+    $ref: raw-nand-chip.yaml#
+    description:
+      NAND chip bindings.
+
+    additionalProperties: false
+
+    properties:
+      reg:
+        items:
+          - items:
+              - description: describes the CS lines assigned to the NAND device.
+              - description: the base offset of the memory region assigned to this device (always 0)
+              - description: the memory region size (always 0x800000)
+      rb-gpios:
+        description:
+          the GPIO(s) used to check the Ready/Busy status of the NAND.
+
+      cs-gpios:
+        description:
+          the GPIO(s) used to control the CS line.
+
+      det-gpios:
+        description:
+          the GPIO used to detect if a Smartmedia Card is present.
+
+      atmel,rb:
+        description: |
+          an integer identifying the native Ready/Busy pin.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      nand-ecc-step-size:
+        const: 512
+
+      nand-ecc-strength:
+        enum: [2, 4, 8]
+
+      nand-ecc-mode:
+        enum: [soft, hw]
+
+      nand-bus-width:
+        const: 8
+
+      nand-on-flash-bbt: true
+
+      partitions:
+        $ref: /schemas/mtd/partitions/partitions.yaml
+
+      label:
+        description: Name or Label of the device
+
+    allOf:
+      - if:
+          properties:
+            compatible:
+              contains:
+                const: atmel,sama5d3-nand-controller
+        then:
+          properties:
+            "atmel,rb":
+              description: an integer identifying the native Ready/Busy pin.
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    nfc_io: nfc-io@70000000 {
+        compatible = "atmel,sama5d3-nfc-io", "syscon";
+        reg = <0x70000000 0x8000000>;
+    };
+
+    nfc_sram: sram@200000 {
+        compatible = "mmio-sram";
+        no-memory-wc;
+        reg = <0x200000 0x2400>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0 0x200000 0x2400>;
+    };
+
+    ebi@10000000 {
+        compatible = "atmel,sama5d3-ebi";
+        #address-cells = <2>;
+        #size-cells = <1>;
+        atmel,smc = <&hsmc>;
+        reg = <0x10000000 0x10000000
+               0x40000000 0x30000000>;
+        ranges = <0x0 0x0 0x10000000 0x10000000
+                  0x1 0x0 0x40000000 0x10000000
+                  0x2 0x0 0x50000000 0x10000000
+                  0x3 0x0 0x60000000 0x10000000>;
+        clocks = <&mck>;
+
+        nand_controller: nand-controller {
+            compatible = "atmel,sama5d3-nand-controller";
+            atmel,nfc-sram = <&nfc_sram>;
+            atmel,nfc-io = <&nfc_io>;
+            ecc-engine = <&pmecc>;
+            #address-cells = <2>;
+            #size-cells = <1>;
+            ranges;
+
+            nand@3 {
+                reg = <0x3 0x0 0x800000>;
+                atmel,rb = <0>;
+                /*
+                 * Put generic NAND/MTD properties and
+                 * subnodes here.
+                 */
+            };
+        };
+    };
-- 
2.34.1

[PATCH v3 2/4] dt-bindings: mtd: microchip-nand: add atmel pmecc

[Balamanikandan Gunasundar]

Add bindings for programmable multibit error correction code controller
(PMECC).

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
---
 .../devicetree/bindings/mtd/atmel-nand.txt    | 61 ------------------
 .../bindings/mtd/microchip,pmecc.yaml         | 62 +++++++++++++++++++
 2 files changed, 62 insertions(+), 61 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index dbbc17a866f2..1934614a9298 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -1,64 +1,3 @@
-* ECC engine (PMECC) bindings:
-
-Required properties:
-- compatible: should be one of the following
-	"atmel,at91sam9g45-pmecc"
-	"atmel,sama5d4-pmecc"
-	"atmel,sama5d2-pmecc"
-	"microchip,sam9x60-pmecc"
-	"microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
-- reg: should contain 2 register ranges. The first one is pointing to the PMECC
-       block, and the second one to the PMECC_ERRLOC block.
-
-Example:
-
-	nfc_io: nfc-io@70000000 {
-		compatible = "atmel,sama5d3-nfc-io", "syscon";
-		reg = <0x70000000 0x8000000>;
-	};
-
-	pmecc: ecc-engine@ffffc070 {
-		compatible = "atmel,at91sam9g45-pmecc";
-                reg = <0xffffc070 0x490>,
-                      <0xffffc500 0x100>;
-	};
-
-	ebi: ebi@10000000 {
-		compatible = "atmel,sama5d3-ebi";
-		#address-cells = <2>;
-		#size-cells = <1>;
-		atmel,smc = <&hsmc>;
-		reg = <0x10000000 0x10000000
-		       0x40000000 0x30000000>;
-		ranges = <0x0 0x0 0x10000000 0x10000000
-			  0x1 0x0 0x40000000 0x10000000
-			  0x2 0x0 0x50000000 0x10000000
-			  0x3 0x0 0x60000000 0x10000000>;
-		clocks = <&mck>;
-
-                nand_controller: nand-controller {
-			compatible = "atmel,sama5d3-nand-controller";
-			atmel,nfc-sram = <&nfc_sram>;
-			atmel,nfc-io = <&nfc_io>;
-			ecc-engine = <&pmecc>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-			ranges;
-
-			nand@3 {
-				reg = <0x3 0x0 0x800000>;
-				atmel,rb = <0>;
-
-				/*
-				 * Put generic NAND/MTD properties and
-				 * subnodes here.
-				 */
-			};
-		};
-	};
-
------------------------------------------------------------------------
-
 Deprecated bindings (should not be used in new device trees):
 
 Required properties:
diff --git a/Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml b/Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml
new file mode 100644
index 000000000000..89680a051981
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/microchip,pmecc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip pmecc controller
+
+maintainers:
+  - Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
+
+description:
+  Bindings for microchip Programmable Multibit Error Correction Code
+  Controller (PMECC). pmecc is a programmable BCH encoder/decoder. This
+  block is passed as the value to the "ecc-engine" property of microchip
+  nand flash controller node.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - atmel,at91sam9g45-pmecc
+          - atmel,sama5d2-pmecc
+          - atmel,sama5d4-pmecc
+      - items:
+          - enum:
+              - microchip,sam9x7-pmecc
+              - microchip,sam9x60-pmecc
+          - const: atmel,at91sam9g45-pmecc
+
+  reg:
+    items:
+      - description: PMECC controller registers
+      - description: PMECC_ERRLOC controller
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: microchip,sam9x7-pmecc
+    then:
+      required:
+        - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    ecc-engine@ffffc070 {
+        compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc";
+        reg = <0xffffe000 0x300>,
+              <0xffffe600 0x100>;
+        clocks = <&pmc 2 48>;
+    };
-- 
2.34.1

[PATCH v3 3/4] dt-bindings: mtd: atmel-nand: add legacy nand controllers

[Balamanikandan Gunasundar]

Add support for atmel legacy nand controllers. These bindings should not be
used with the new device trees.

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
---
 .../devicetree/bindings/mtd/atmel-nand.txt    | 116 ------------
 .../devicetree/bindings/mtd/atmel-nand.yaml   | 167 ++++++++++++++++++
 2 files changed, 167 insertions(+), 116 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.yaml

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
deleted file mode 100644
index 1934614a9298..000000000000
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-Deprecated bindings (should not be used in new device trees):
-
-Required properties:
-- compatible: The possible values are:
-	"atmel,at91rm9200-nand"
-	"atmel,sama5d2-nand"
-	"atmel,sama5d4-nand"
-- reg : should specify localbus address and size used for the chip,
-	and hardware ECC controller if available.
-	If the hardware ECC is PMECC, it should contain address and size for
-	PMECC and PMECC Error Location controller.
-	The PMECC lookup table address and size in ROM is optional. If not
-	specified, driver will build it in runtime.
-- atmel,nand-addr-offset : offset for the address latch.
-- atmel,nand-cmd-offset : offset for the command latch.
-- #address-cells, #size-cells : Must be present if the device has sub-nodes
-  representing partitions.
-
-- gpios : specifies the gpio pins to control the NAND device. detect is an
-  optional gpio and may be set to 0 if not present.
-
-Optional properties:
-- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
-- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
-  Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
-  "soft_bch".
-- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
-  capable of BCH encoding and decoding, on devices where it is present.
-- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
-  Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
-  is "atmel,sama5d2-nand", 32 is also valid.
-- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
-  are: 512, 1024.
-- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
-  for different sector size. First one is for sector size 512, the next is for
-  sector size 1024. If not specified, driver will build the table in runtime.
-- nand-bus-width : 8 or 16 bus width if not present 8
-- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
-
-Nand Flash Controller(NFC) is an optional sub-node
-Required properties:
-- compatible : "atmel,sama5d3-nfc".
-- reg : should specify the address and size used for NFC command registers,
-        NFC registers and NFC SRAM. NFC SRAM address and size can be absent
-        if don't want to use it.
-- clocks: phandle to the peripheral clock
-Optional properties:
-- atmel,write-by-sram: boolean to enable NFC write by SRAM.
-
-Examples:
-nand0: nand@40000000,0 {
-	compatible = "atmel,at91rm9200-nand";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	reg = <0x40000000 0x10000000
-	       0xffffe800 0x200
-	      >;
-	atmel,nand-addr-offset = <21>;	/* ale */
-	atmel,nand-cmd-offset = <22>;	/* cle */
-	nand-on-flash-bbt;
-	nand-ecc-mode = "soft";
-	gpios = <&pioC 13 0	/* rdy */
-		 &pioC 14 0 	/* nce */
-		 0		/* cd */
-		>;
-	partition@0 {
-		...
-	};
-};
-
-/* for PMECC supported chips */
-nand0: nand@40000000 {
-	compatible = "atmel,at91rm9200-nand";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	reg = < 0x40000000 0x10000000	/* bus addr & size */
-		0xffffe000 0x00000600	/* PMECC addr & size */
-		0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */
-		0x00100000 0x00100000	/* ROM addr & size */
-		>;
-	atmel,nand-addr-offset = <21>;	/* ale */
-	atmel,nand-cmd-offset = <22>;	/* cle */
-	nand-on-flash-bbt;
-	nand-ecc-mode = "hw";
-	atmel,has-pmecc;	/* enable PMECC */
-	atmel,pmecc-cap = <2>;
-	atmel,pmecc-sector-size = <512>;
-	atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
-	gpios = <&pioD 5 0	/* rdy */
-		 &pioD 4 0	/* nce */
-		 0		/* cd */
-		>;
-	partition@0 {
-		...
-	};
-};
-
-/* for NFC supported chips */
-nand0: nand@40000000 {
-	compatible = "atmel,at91rm9200-nand";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges;
-        ...
-        nfc@70000000 {
-		compatible = "atmel,sama5d3-nfc";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		clocks = <&hsmc_clk>
-		reg = <
-			0x70000000 0x10000000	/* NFC Command Registers */
-			0xffffc000 0x00000070	/* NFC HSMC regs */
-			0x00200000 0x00100000	/* NFC SRAM banks */
-		>;
-	};
-};
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.yaml b/Documentation/devicetree/bindings/mtd/atmel-nand.yaml
new file mode 100644
index 000000000000..a437d40a523f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/atmel-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel NAND flash controller
+
+maintainers:
+  - Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
+
+description:
+  Atmel nand flash controller. These are legacy bindings and
+  deprecated. Find the latest in microchip,nand-controller.yaml
+
+properties:
+  $nodename:
+    pattern: "^nand(@.*)?"
+
+  compatible:
+    enum:
+      - atmel,at91rm9200-nand
+      - atmel,sama5d2-nand
+      - atmel,sama5d4-nand
+
+  reg:
+    description:
+      The localbus address and size used for the chip, and hardware ECC
+      controller if available. If the hardware ECC is PMECC, it should
+      contain address and size for PMECC and PMECC Error Location
+      controller. The PMECC lookup table address and size in ROM is
+      optional. If not specified, driver will build it in runtime.
+
+  nand-on-flash-bbt:
+    description:
+      enable on flash bbt option if not present false
+    $ref: /schemas/types.yaml#/definitions/flag
+
+  nand-ecc-mode:
+    description:
+      operation mode of the NAND ecc
+    enum:
+      [none, soft, hw, hw_syndrome, hw_oob_first, soft_bch]
+    default: soft
+    $ref: /schemas/types.yaml#/definitions/string
+
+  nand-bus-width:
+    description:
+      nand bus width
+    enum:
+      [8, 16]
+    default: 8
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  gpios:
+    minItems: 2
+    items:
+      - description: Ready/Busy
+      - description: Chip Enable
+      - description: Optional Card detect GPIO; can be 0 if unused
+
+  atmel,nand-addr-offset:
+    description:
+      offset for the address latch.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 31
+
+  atmel,nand-cmd-offset:
+    description:
+      offset for the command latch.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 31
+
+  atmel,nand-has-dma:
+    description:
+      support dma transfer for nand read/write.
+    $ref: /schemas/types.yaml#/definitions/flag
+
+  atmel,has-pmecc:
+    description:
+      enable Programmable Multibit ECC hardware, capable of BCH encoding
+      and decoding, on devices where it is present.
+    $ref: /schemas/types.yaml#/definitions/flag
+
+  atmel,pmecc-cap:
+    description:
+      error correct capability for Programmable Multibit ECC Controller.
+    enum:
+      [2, 4, 8, 12, 24, 32]
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  atmel,pmecc-sector-size:
+    description:
+      sector size for ECC computation.
+    enum:
+      [512, 1024]
+    default: 512
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+
+  atmel,pmecc-lookup-table-offset:
+    description:
+      Two offsets of lookup table in ROM for different sector size. First
+      one is for sector size 512, the next is for sector size 1024. If not
+      specified, driver will build the table in runtime.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    default: 512
+
+required:
+  - compatible
+  - reg
+  - atmel,nand-addr-offset
+  - atmel,nand-cmd-offset
+  - "#address-cells"
+  - "#size-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    nand@40000000 {
+        compatible = "atmel,at91rm9200-nand";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x40000000 0x10000000
+               0xffffe800 0x200>;
+        atmel,nand-addr-offset = <21>;	/* ale */
+        atmel,nand-cmd-offset = <22>;	/* cle */
+        nand-on-flash-bbt;
+        nand-ecc-mode = "soft";
+        gpios = <&pioC 13 0	/* rdy */
+                 &pioC 14 0     /* nce */
+                 0		/* cd */
+                >;
+    };
+  - |
+    /* for PMECC supported chips */
+    nand@40000000 {
+        compatible = "atmel,at91rm9200-nand";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x40000000 0x10000000	/* bus addr & size */
+               0xffffe000 0x00000600	/* PMECC addr & size */
+               0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */
+               0x00100000 0x00100000>;	/* ROM addr & size */
+
+        atmel,nand-addr-offset = <21>;	/* ale */
+        atmel,nand-cmd-offset = <22>;	/* cle */
+        nand-on-flash-bbt;
+        nand-ecc-mode = "hw";
+        atmel,has-pmecc;	/* enable PMECC */
+        atmel,pmecc-cap = <2>;
+        atmel,pmecc-sector-size = <512>;
+        atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
+        gpios = <&pioD 5 0	/* rdy */
+                 &pioD 4 0	/* nce */
+                 0		/* cd */
+                >;
+    };
-- 
2.34.1

[PATCH v3 4/4] MAINTAINERS: add entry for microchip nand controller

[Balamanikandan Gunasundar]

Add myself as maintainer for microchip nand controller driver

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
---
 MAINTAINERS | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index dd844ac8d910..53cc327b8985 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16064,9 +16064,10 @@ S:	Maintained
 F:	drivers/mmc/host/atmel-mci.c
 
 MICROCHIP NAND DRIVER
+M:	Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
 L:	linux-mtd@lists.infradead.org
-S:	Orphan
-F:	Documentation/devicetree/bindings/mtd/atmel-nand.txt
+S:	Maintained
+F:	Documentation/devicetree/bindings/mtd/microchip,*.yaml
 F:	drivers/mtd/nand/raw/atmel/*
 
 MICROCHIP OTPC DRIVER
-- 
2.34.1

Re: [PATCH v3 1/4] dt-bindings: mtd: microchip-nand: convert txt to yaml

[Balamanikandan.Gunasundar]

Hi,

On 02/06/25 11:05 am, Balamanikandan Gunasundar wrote:
> Convert text to yaml for microchip nand controller
> 
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>   .../devicetree/bindings/mtd/atmel-nand.txt    |  50 ------
>   .../mtd/microchip,nand-controller.yaml        | 169 ++++++++++++++++++
>   2 files changed, 169 insertions(+), 50 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index e36c35b17873..dbbc17a866f2 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -1,53 +1,3 @@
> -Atmel NAND flash controller bindings
> -
> -The NAND flash controller node should be defined under the EBI bus (see
> -Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
> -One or several NAND devices can be defined under this NAND controller.
> -The NAND controller might be connected to an ECC engine.
> -
> -* NAND controller bindings:
> -
> -Required properties:
> -- compatible: should be one of the following
> -	"atmel,at91rm9200-nand-controller"
> -	"atmel,at91sam9260-nand-controller"
> -	"atmel,at91sam9261-nand-controller"
> -	"atmel,at91sam9g45-nand-controller"
> -	"atmel,sama5d3-nand-controller"
> -	"microchip,sam9x60-nand-controller"
> -- ranges: empty ranges property to forward EBI ranges definitions.
> -- #address-cells: should be set to 2.
> -- #size-cells: should be set to 1.
> -- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
> -		controllers.
> -- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
> -		  controllers.
> -
> -Optional properties:
> -- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
> -	      a PMECC engine.
> -
> -* NAND device/chip bindings:
> -
> -Required properties:
> -- reg: describes the CS lines assigned to the NAND device. If the NAND device
> -       exposes multiple CS lines (multi-dies chips), your reg property will
> -       contain X tuples of 3 entries.
> -       1st entry: the CS line this NAND chip is connected to
> -       2nd entry: the base offset of the memory region assigned to this
> -		  device (always 0)
> -       3rd entry: the memory region size (always 0x800000)
> -
> -Optional properties:
> -- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
> -- cs-gpios: the GPIO(s) used to control the CS line.
> -- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
> -- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
> -	    on sama5 SoCs.
> -
> -All generic properties are described in the generic yaml files under
> -Documentation/devicetree/bindings/mtd/.
> -
>   * ECC engine (PMECC) bindings:
>   
>   Required properties:
> diff --git a/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
> new file mode 100644
> index 000000000000..2b0d03343611
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/microchip,nand-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip NAND flash controller
> +
> +maintainers:
> +  - Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> +
> +description: |
> +  The NAND flash controller node should be defined under the EBI bus (see
> +  Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
> +  One or several NAND devices can be defined under this NAND controller.
> +  The NAND controller might be connected to an ECC engine.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - atmel,at91rm9200-nand-controller
> +      - atmel,at91sam9260-nand-controller
> +      - atmel,at91sam9261-nand-controller
> +      - atmel,at91sam9g45-nand-controller
> +      - atmel,sama5d3-nand-controller
> +      - microchip,sam9x60-nand-controller
> +
> +  ranges:
> +    description: empty ranges property to forward EBI ranges definitions.
> +
> +  ecc-engine:
> +    description:
> +      phandle to the PMECC block. Only meaningful if the SoC embeds a PMECC
> +      engine. Refer microchip,pmecc.yaml
> +
> +  "#address-cells":
> +    const: 2
> +
> +  "#size-cells":
> +    const: 1
nand-controller.yaml has this values defined as

   "#address-cells":
     const: 1

   "#size-cells":
     const: 0

I am unable to overwrite this as they are const values. Microchip's 
nand_controller is a child node of ebi unlike other nand controllers 
where i need to overwrite this. I didn't inherit nand-controller.yaml to 
has this defined locally.

I upgraded dtschema and ran dt_binding_check and dtb_check again for all 
the bindings in this series as recommended in v2 comments. But I don't 
get the error below

https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250311122847.90081-2-balamanikandan.gunasundar@microchip.com/

I am not sure what else I am missing. Your comments please?

Bala.


> +
> +  atmel,nfc-io:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: phandle to the NFC IO block. Only applicable for atmel,sama5d3-nand-controller
> +
> +  atmel,nfc-sram:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: phandle to the NFC SRAM block. Only applicable for atmel,sama5d3-nand-controller
> +
> +required:
> +  - compatible
> +  - ranges
> +  - "#address-cells"
> +  - "#size-cells"
> +
> +patternProperties:
> +  "^nand@[a-f0-9]$":
> +    type: object
> +    $ref: raw-nand-chip.yaml#
> +    description:
> +      NAND chip bindings.
> +
> +    additionalProperties: false
> +
> +    properties:
> +      reg:
> +        items:
> +          - items:
> +              - description: describes the CS lines assigned to the NAND device.
> +              - description: the base offset of the memory region assigned to this device (always 0)
> +              - description: the memory region size (always 0x800000)
> +      rb-gpios:
> +        description:
> +          the GPIO(s) used to check the Ready/Busy status of the NAND.
> +
> +      cs-gpios:
> +        description:
> +          the GPIO(s) used to control the CS line.
> +
> +      det-gpios:
> +        description:
> +          the GPIO used to detect if a Smartmedia Card is present.
> +
> +      atmel,rb:
> +        description: |
> +          an integer identifying the native Ready/Busy pin.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +
> +      nand-ecc-step-size:
> +        const: 512
> +
> +      nand-ecc-strength:
> +        enum: [2, 4, 8]
> +
> +      nand-ecc-mode:
> +        enum: [soft, hw]
> +
> +      nand-bus-width:
> +        const: 8
> +
> +      nand-on-flash-bbt: true
> +
> +      partitions:
> +        $ref: /schemas/mtd/partitions/partitions.yaml
> +
> +      label:
> +        description: Name or Label of the device
> +
> +    allOf:
> +      - if:
> +          properties:
> +            compatible:
> +              contains:
> +                const: atmel,sama5d3-nand-controller
> +        then:
> +          properties:
> +            "atmel,rb":
> +              description: an integer identifying the native Ready/Busy pin.
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    nfc_io: nfc-io@70000000 {
> +        compatible = "atmel,sama5d3-nfc-io", "syscon";
> +        reg = <0x70000000 0x8000000>;
> +    };
> +
> +    nfc_sram: sram@200000 {
> +        compatible = "mmio-sram";
> +        no-memory-wc;
> +        reg = <0x200000 0x2400>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges = <0 0x200000 0x2400>;
> +    };
> +
> +    ebi@10000000 {
> +        compatible = "atmel,sama5d3-ebi";
> +        #address-cells = <2>;
> +        #size-cells = <1>;
> +        atmel,smc = <&hsmc>;
> +        reg = <0x10000000 0x10000000
> +               0x40000000 0x30000000>;
> +        ranges = <0x0 0x0 0x10000000 0x10000000
> +                  0x1 0x0 0x40000000 0x10000000
> +                  0x2 0x0 0x50000000 0x10000000
> +                  0x3 0x0 0x60000000 0x10000000>;
> +        clocks = <&mck>;
> +
> +        nand_controller: nand-controller {
> +            compatible = "atmel,sama5d3-nand-controller";
> +            atmel,nfc-sram = <&nfc_sram>;
> +            atmel,nfc-io = <&nfc_io>;
> +            ecc-engine = <&pmecc>;
> +            #address-cells = <2>;
> +            #size-cells = <1>;
> +            ranges;
> +
> +            nand@3 {
> +                reg = <0x3 0x0 0x800000>;
> +                atmel,rb = <0>;
> +                /*
> +                 * Put generic NAND/MTD properties and
> +                 * subnodes here.
> +                 */
> +            };
> +        };
> +    };

Re: [PATCH v3 1/4] dt-bindings: mtd: microchip-nand: convert txt to yaml

[Rob Herring (Arm)]

On Mon, 02 Jun 2025 11:05:04 +0530, Balamanikandan Gunasundar wrote:
> Convert text to yaml for microchip nand controller
> 
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt    |  50 ------
>  .../mtd/microchip,nand-controller.yaml        | 169 ++++++++++++++++++
>  2 files changed, 169 insertions(+), 50 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mtd/microchip,nand-controller.example.dtb: /example-0/ebi@10000000: failed to match any schema with compatible: ['atmel,sama5d3-ebi']
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mtd/microchip,nand-controller.example.dtb: nand-controller (atmel,sama5d3-nand-controller): #address-cells: 1 was expected
	from schema $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mtd/microchip,nand-controller.example.dtb: nand-controller (atmel,sama5d3-nand-controller): #size-cells: 0 was expected
	from schema $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250602053507.25864-2-balamanikandan.gunasundar@microchip.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v3 4/4] MAINTAINERS: add entry for microchip nand controller

[Krzysztof Kozlowski]

On 02/06/2025 07:35, Balamanikandan Gunasundar wrote:
> Add myself as maintainer for microchip nand controller driver
> 
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>  MAINTAINERS | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index dd844ac8d910..53cc327b8985 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16064,9 +16064,10 @@ S:	Maintained
>  F:	drivers/mmc/host/atmel-mci.c
>  
>  MICROCHIP NAND DRIVER
> +M:	Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
>  L:	linux-mtd@lists.infradead.org
> -S:	Orphan
> -F:	Documentation/devicetree/bindings/mtd/atmel-nand.txt

Your patchset is not bisectable. This belongs to the patch removing the
file.


Best regards,
Krzysztof

Re: [PATCH v3 3/4] dt-bindings: mtd: atmel-nand: add legacy nand controllers

[Krzysztof Kozlowski]

On 02/06/2025 07:35, Balamanikandan Gunasundar wrote:
> Add support for atmel legacy nand controllers. These bindings should not be

No new support for legacy bindings. Both your commit msg and subject do
not describe what you do here. I see you convert EXISTING bindings
instead of adding support. But if you insist on adding, that would be
NAKed because why would we want to accept new stuff which is already
deprecated?

> used with the new device trees.
> 
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt    | 116 ------------
>  .../devicetree/bindings/mtd/atmel-nand.yaml   | 167 ++++++++++++++++++

Filename matching compatible. Also look at your 4/4 patch and compare
what is here and there.

>  2 files changed, 167 insertions(+), 116 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.txt
>  create mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.yaml
> 


...

> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.yaml b/Documentation/devicetree/bindings/mtd/atmel-nand.yaml
> new file mode 100644
> index 000000000000..a437d40a523f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.yaml
> @@ -0,0 +1,167 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/atmel-nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Atmel NAND flash controller
> +
> +maintainers:
> +  - Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> +
> +description:
> +  Atmel nand flash controller. These are legacy bindings and
> +  deprecated. Find the latest in microchip,nand-controller.yaml
> +

Missing allOf/ref to nand-controller

> +properties:
> +  $nodename:
> +    pattern: "^nand(@.*)?"

Drop

> +
> +  compatible:
> +    enum:
> +      - atmel,at91rm9200-nand
> +      - atmel,sama5d2-nand
> +      - atmel,sama5d4-nand
> +
> +  reg:
> +    description:
> +      The localbus address and size used for the chip, and hardware ECC
> +      controller if available. If the hardware ECC is PMECC, it should
> +      contain address and size for PMECC and PMECC Error Location
> +      controller. The PMECC lookup table address and size in ROM is
> +      optional. If not specified, driver will build it in runtime.
> +
> +  nand-on-flash-bbt:
> +    description:
> +      enable on flash bbt option if not present false
> +    $ref: /schemas/types.yaml#/definitions/flag
> +
> +  nand-ecc-mode:
> +    description:
> +      operation mode of the NAND ecc
> +    enum:
> +      [none, soft, hw, hw_syndrome, hw_oob_first, soft_bch]
> +    default: soft
> +    $ref: /schemas/types.yaml#/definitions/string
> +
> +  nand-bus-width:
> +    description:
> +      nand bus width
> +    enum:
> +      [8, 16]
> +    default: 8
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1

You have several redundant properties. What's more, you are basically
re-definingn them. Drop and keep only constraints. Look at other
bindings and follow how they are doing this.

> +
> +  gpios:
> +    minItems: 2
> +    items:
> +      - description: Ready/Busy
> +      - description: Chip Enable
> +      - description: Optional Card detect GPIO; can be 0 if unused
> +
> +  atmel,nand-addr-offset:
> +    description:
> +      offset for the address latch.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 31
> +
> +  atmel,nand-cmd-offset:
> +    description:
> +      offset for the command latch.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 31
> +
> +  atmel,nand-has-dma:
> +    description:
> +      support dma transfer for nand read/write.
> +    $ref: /schemas/types.yaml#/definitions/flag
> +
> +  atmel,has-pmecc:
> +    description:
> +      enable Programmable Multibit ECC hardware, capable of BCH encoding
> +      and decoding, on devices where it is present.
> +    $ref: /schemas/types.yaml#/definitions/flag
> +
> +  atmel,pmecc-cap:
> +    description:
> +      error correct capability for Programmable Multibit ECC Controller.
> +    enum:
> +      [2, 4, 8, 12, 24, 32]
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +
> +  atmel,pmecc-sector-size:
> +    description:
> +      sector size for ECC computation.
> +    enum:
> +      [512, 1024]
> +    default: 512
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +
> +

Just one blank line

> +  atmel,pmecc-lookup-table-offset:
> +    description:
> +      Two offsets of lookup table in ROM for different sector size. First
> +      one is for sector size 512, the next is for sector size 1024. If not
> +      specified, driver will build the table in runtime.
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    default: 512
> +
> +required:
> +  - compatible
> +  - reg
> +  - atmel,nand-addr-offset
> +  - atmel,nand-cmd-offset
> +  - "#address-cells"
> +  - "#size-cells"

Use consistent quotes, either ' or "

> +
> +unevaluatedProperties: false

Without $ref this makes no sense, so it clearly points you to missing ref.

> +
> +examples:
> +  - |
> +    nand@40000000 {
> +        compatible = "atmel,at91rm9200-nand";
> +        #address-cells = <1>;
> +        #size-cells = <1>;

Follow DTS coding style.

> +        reg = <0x40000000 0x10000000
> +               0xffffe800 0x200>;

These are two entries, not one.


> +        atmel,nand-addr-offset = <21>;	/* ale */
> +        atmel,nand-cmd-offset = <22>;	/* cle */
> +        nand-on-flash-bbt;
> +        nand-ecc-mode = "soft";
> +        gpios = <&pioC 13 0	/* rdy */
> +                 &pioC 14 0     /* nce */
> +                 0		/* cd */

All this is not following standard style. Two entries. Use proper
defines for GPIO flags.

> +                >;
> +    };
> +  - |
> +    /* for PMECC supported chips */
> +    nand@40000000 {
> +        compatible = "atmel,at91rm9200-nand";
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        reg = <0x40000000 0x10000000	/* bus addr & size */
> +               0xffffe000 0x00000600	/* PMECC addr & size */
> +               0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */
> +               0x00100000 0x00100000>;	/* ROM addr & size */

Four entries, not one.

> +
> +        atmel,nand-addr-offset = <21>;	/* ale */
> +        atmel,nand-cmd-offset = <22>;	/* cle */
> +        nand-on-flash-bbt;
> +        nand-ecc-mode = "hw";
> +        atmel,has-pmecc;	/* enable PMECC */
> +        atmel,pmecc-cap = <2>;
> +        atmel,pmecc-sector-size = <512>;
> +        atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
> +        gpios = <&pioD 5 0	/* rdy */
> +                 &pioD 4 0	/* nce */
> +                 0		/* cd */
> +                >;
> +    };


Best regards,
Krzysztof

Re: [PATCH v3 4/4] MAINTAINERS: add entry for microchip nand controller

[Balamanikandan.Gunasundar]

On 02/06/25 12:47 pm, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 02/06/2025 07:35, Balamanikandan Gunasundar wrote:
>> Add myself as maintainer for microchip nand controller driver
>>
>> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
>> ---
>>   MAINTAINERS | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index dd844ac8d910..53cc327b8985 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -16064,9 +16064,10 @@ S:   Maintained
>>   F:   drivers/mmc/host/atmel-mci.c
>>
>>   MICROCHIP NAND DRIVER
>> +M:   Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
>>   L:   linux-mtd@lists.infradead.org
>> -S:   Orphan
>> -F:   Documentation/devicetree/bindings/mtd/atmel-nand.txt
> 
> Your patchset is not bisectable. This belongs to the patch removing the
> file.
> 

Yes. I will squash it appropriately and resend this.

> 
> Best regards,
> Krzysztof

Re: [PATCH v3 3/4] dt-bindings: mtd: atmel-nand: add legacy nand controllers

[Balamanikandan.Gunasundar]

On 02/06/25 12:53 pm, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 02/06/2025 07:35, Balamanikandan Gunasundar wrote:
>> Add support for atmel legacy nand controllers. These bindings should not be
> 
> No new support for legacy bindings. Both your commit msg and subject do
> not describe what you do here. I see you convert EXISTING bindings
> instead of adding support. But if you insist on adding, that would be
> NAKed because why would we want to accept new stuff which is already
> deprecated?

Yes. I am just converting the exiting bindings. Hope rephrasing the 
commit message is sufficient enough.

> 
>> used with the new device trees.
>>
>> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
>> ---
>>   .../devicetree/bindings/mtd/atmel-nand.txt    | 116 ------------
>>   .../devicetree/bindings/mtd/atmel-nand.yaml   | 167 ++++++++++++++++++
> 
> Filename matching compatible. Also look at your 4/4 patch and compare
> what is here and there.
> 
>>   2 files changed, 167 insertions(+), 116 deletions(-)
>>   delete mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.txt
>>   create mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.yaml
>>
> 
> 
> ...
> 
>> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.yaml b/Documentation/devicetree/bindings/mtd/atmel-nand.yaml
>> new file mode 100644
>> index 000000000000..a437d40a523f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.yaml
>> @@ -0,0 +1,167 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mtd/atmel-nand.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Atmel NAND flash controller
>> +
>> +maintainers:
>> +  - Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
>> +
>> +description:
>> +  Atmel nand flash controller. These are legacy bindings and
>> +  deprecated. Find the latest in microchip,nand-controller.yaml
>> +
> 
> Missing allOf/ref to nand-controller
> 
>> +properties:
>> +  $nodename:
>> +    pattern: "^nand(@.*)?"
> 
> Drop
> 
>> +
>> +  compatible:
>> +    enum:
>> +      - atmel,at91rm9200-nand
>> +      - atmel,sama5d2-nand
>> +      - atmel,sama5d4-nand
>> +
>> +  reg:
>> +    description:
>> +      The localbus address and size used for the chip, and hardware ECC
>> +      controller if available. If the hardware ECC is PMECC, it should
>> +      contain address and size for PMECC and PMECC Error Location
>> +      controller. The PMECC lookup table address and size in ROM is
>> +      optional. If not specified, driver will build it in runtime.
>> +
>> +  nand-on-flash-bbt:
>> +    description:
>> +      enable on flash bbt option if not present false
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +
>> +  nand-ecc-mode:
>> +    description:
>> +      operation mode of the NAND ecc
>> +    enum:
>> +      [none, soft, hw, hw_syndrome, hw_oob_first, soft_bch]
>> +    default: soft
>> +    $ref: /schemas/types.yaml#/definitions/string
>> +
>> +  nand-bus-width:
>> +    description:
>> +      nand bus width
>> +    enum:
>> +      [8, 16]
>> +    default: 8
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +
>> +  '#address-cells':
>> +    const: 1
>> +
>> +  '#size-cells':
>> +    const: 1
> 
> You have several redundant properties. What's more, you are basically
> re-definingn them. Drop and keep only constraints. Look at other
> bindings and follow how they are doing this.
> 
>> +
>> +  gpios:
>> +    minItems: 2
>> +    items:
>> +      - description: Ready/Busy
>> +      - description: Chip Enable
>> +      - description: Optional Card detect GPIO; can be 0 if unused
>> +
>> +  atmel,nand-addr-offset:
>> +    description:
>> +      offset for the address latch.
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    minimum: 0
>> +    maximum: 31
>> +
>> +  atmel,nand-cmd-offset:
>> +    description:
>> +      offset for the command latch.
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    minimum: 0
>> +    maximum: 31
>> +
>> +  atmel,nand-has-dma:
>> +    description:
>> +      support dma transfer for nand read/write.
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +
>> +  atmel,has-pmecc:
>> +    description:
>> +      enable Programmable Multibit ECC hardware, capable of BCH encoding
>> +      and decoding, on devices where it is present.
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +
>> +  atmel,pmecc-cap:
>> +    description:
>> +      error correct capability for Programmable Multibit ECC Controller.
>> +    enum:
>> +      [2, 4, 8, 12, 24, 32]
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +
>> +  atmel,pmecc-sector-size:
>> +    description:
>> +      sector size for ECC computation.
>> +    enum:
>> +      [512, 1024]
>> +    default: 512
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +
>> +
> 
> Just one blank line
> 
>> +  atmel,pmecc-lookup-table-offset:
>> +    description:
>> +      Two offsets of lookup table in ROM for different sector size. First
>> +      one is for sector size 512, the next is for sector size 1024. If not
>> +      specified, driver will build the table in runtime.
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>> +    default: 512
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - atmel,nand-addr-offset
>> +  - atmel,nand-cmd-offset
>> +  - "#address-cells"
>> +  - "#size-cells"
> 
> Use consistent quotes, either ' or "
> 
>> +
>> +unevaluatedProperties: false
> 
> Without $ref this makes no sense, so it clearly points you to missing ref.
> 
>> +
>> +examples:
>> +  - |
>> +    nand@40000000 {
>> +        compatible = "atmel,at91rm9200-nand";
>> +        #address-cells = <1>;
>> +        #size-cells = <1>;
> 
> Follow DTS coding style.
> 
>> +        reg = <0x40000000 0x10000000
>> +               0xffffe800 0x200>;
> 
> These are two entries, not one.
> 
> 
>> +        atmel,nand-addr-offset = <21>;       /* ale */
>> +        atmel,nand-cmd-offset = <22>;        /* cle */
>> +        nand-on-flash-bbt;
>> +        nand-ecc-mode = "soft";
>> +        gpios = <&pioC 13 0  /* rdy */
>> +                 &pioC 14 0     /* nce */
>> +                 0           /* cd */
> 
> All this is not following standard style. Two entries. Use proper
> defines for GPIO flags.
> 
>> +                >;
>> +    };
>> +  - |
>> +    /* for PMECC supported chips */
>> +    nand@40000000 {
>> +        compatible = "atmel,at91rm9200-nand";
>> +        #address-cells = <1>;
>> +        #size-cells = <1>;
>> +        reg = <0x40000000 0x10000000 /* bus addr & size */
>> +               0xffffe000 0x00000600 /* PMECC addr & size */
>> +               0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
>> +               0x00100000 0x00100000>;       /* ROM addr & size */
> 
> Four entries, not one.
> 
>> +
>> +        atmel,nand-addr-offset = <21>;       /* ale */
>> +        atmel,nand-cmd-offset = <22>;        /* cle */
>> +        nand-on-flash-bbt;
>> +        nand-ecc-mode = "hw";
>> +        atmel,has-pmecc;     /* enable PMECC */
>> +        atmel,pmecc-cap = <2>;
>> +        atmel,pmecc-sector-size = <512>;
>> +        atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
>> +        gpios = <&pioD 5 0   /* rdy */
>> +                 &pioD 4 0   /* nce */
>> +                 0           /* cd */
>> +                >;
>> +    };
> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 3/4] dt-bindings: mtd: atmel-nand: add legacy nand controllers

[Krzysztof Kozlowski]

On 02/06/2025 10:59, Balamanikandan.Gunasundar@microchip.com wrote:
> On 02/06/25 12:53 pm, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 02/06/2025 07:35, Balamanikandan Gunasundar wrote:
>>> Add support for atmel legacy nand controllers. These bindings should not be
>>
>> No new support for legacy bindings. Both your commit msg and subject do
>> not describe what you do here. I see you convert EXISTING bindings
>> instead of adding support. But if you insist on adding, that would be
>> NAKed because why would we want to accept new stuff which is already
>> deprecated?
> 
> Yes. I am just converting the exiting bindings. Hope rephrasing the 
> commit message is sufficient enough.
And you just ignored everything else? Please kindly trim the replies
from unnecessary context. It makes it much easier to find new content.

Best regards,
Krzysztof

Re: [PATCH v3 3/4] dt-bindings: mtd: atmel-nand: add legacy nand controllers

[Balamanikandan.Gunasundar]

On 02/06/25 2:47 pm, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 02/06/2025 10:59, Balamanikandan.Gunasundar@microchip.com wrote:
>> On 02/06/25 12:53 pm, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 02/06/2025 07:35, Balamanikandan Gunasundar wrote:
>>>> Add support for atmel legacy nand controllers. These bindings should not be
>>>
>>> No new support for legacy bindings. Both your commit msg and subject do
>>> not describe what you do here. I see you convert EXISTING bindings
>>> instead of adding support. But if you insist on adding, that would be
>>> NAKed because why would we want to accept new stuff which is already
>>> deprecated?
>>
>> Yes. I am just converting the exiting bindings. Hope rephrasing the
>> commit message is sufficient enough.
> And you just ignored everything else? Please kindly trim the replies
> from unnecessary context. It makes it much easier to find new content.
> 

Sorry. I missed noticing the remaining part of the email. Not sure if it 
is a problem with my email client. I will address the remaining 
comments. Thanks for reviewing.

> Best regards,
> Krzysztof

Re: [PATCH v3 1/4] dt-bindings: mtd: microchip-nand: convert txt to yaml

[Rob Herring]

On Mon, Jun 02, 2025 at 06:58:52AM +0000, Balamanikandan.Gunasundar@microchip.com wrote:
> Hi,
> 
> On 02/06/25 11:05 am, Balamanikandan Gunasundar wrote:
> > Convert text to yaml for microchip nand controller
> > 
> > Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> > ---
> >   .../devicetree/bindings/mtd/atmel-nand.txt    |  50 ------
> >   .../mtd/microchip,nand-controller.yaml        | 169 ++++++++++++++++++
> >   2 files changed, 169 insertions(+), 50 deletions(-)
> >   create mode 100644 Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> > index e36c35b17873..dbbc17a866f2 100644
> > --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> > +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> > @@ -1,53 +1,3 @@
> > -Atmel NAND flash controller bindings
> > -
> > -The NAND flash controller node should be defined under the EBI bus (see
> > -Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
> > -One or several NAND devices can be defined under this NAND controller.
> > -The NAND controller might be connected to an ECC engine.
> > -
> > -* NAND controller bindings:
> > -
> > -Required properties:
> > -- compatible: should be one of the following
> > -	"atmel,at91rm9200-nand-controller"
> > -	"atmel,at91sam9260-nand-controller"
> > -	"atmel,at91sam9261-nand-controller"
> > -	"atmel,at91sam9g45-nand-controller"
> > -	"atmel,sama5d3-nand-controller"
> > -	"microchip,sam9x60-nand-controller"
> > -- ranges: empty ranges property to forward EBI ranges definitions.
> > -- #address-cells: should be set to 2.
> > -- #size-cells: should be set to 1.
> > -- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
> > -		controllers.
> > -- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
> > -		  controllers.
> > -
> > -Optional properties:
> > -- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
> > -	      a PMECC engine.
> > -
> > -* NAND device/chip bindings:
> > -
> > -Required properties:
> > -- reg: describes the CS lines assigned to the NAND device. If the NAND device
> > -       exposes multiple CS lines (multi-dies chips), your reg property will
> > -       contain X tuples of 3 entries.
> > -       1st entry: the CS line this NAND chip is connected to
> > -       2nd entry: the base offset of the memory region assigned to this
> > -		  device (always 0)
> > -       3rd entry: the memory region size (always 0x800000)
> > -
> > -Optional properties:
> > -- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
> > -- cs-gpios: the GPIO(s) used to control the CS line.
> > -- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
> > -- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
> > -	    on sama5 SoCs.
> > -
> > -All generic properties are described in the generic yaml files under
> > -Documentation/devicetree/bindings/mtd/.
> > -
> >   * ECC engine (PMECC) bindings:
> >   
> >   Required properties:
> > diff --git a/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
> > new file mode 100644
> > index 000000000000..2b0d03343611
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/microchip,nand-controller.yaml
> > @@ -0,0 +1,169 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mtd/microchip,nand-controller.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Microchip NAND flash controller
> > +
> > +maintainers:
> > +  - Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> > +
> > +description: |

Don't need '|'

> > +  The NAND flash controller node should be defined under the EBI bus (see
> > +  Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).

Please don't keep references to old bindings. Really, you should convert 
this binding first.

> > +  One or several NAND devices can be defined under this NAND controller.
> > +  The NAND controller might be connected to an ECC engine.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - atmel,at91rm9200-nand-controller
> > +      - atmel,at91sam9260-nand-controller
> > +      - atmel,at91sam9261-nand-controller
> > +      - atmel,at91sam9g45-nand-controller
> > +      - atmel,sama5d3-nand-controller
> > +      - microchip,sam9x60-nand-controller
> > +
> > +  ranges:
> > +    description: empty ranges property to forward EBI ranges definitions.
> > +
> > +  ecc-engine:
> > +    description:
> > +      phandle to the PMECC block. Only meaningful if the SoC embeds a PMECC
> > +      engine. Refer microchip,pmecc.yaml
> > +
> > +  "#address-cells":
> > +    const: 2
> > +
> > +  "#size-cells":
> > +    const: 1
> nand-controller.yaml has this values defined as
> 
>    "#address-cells":
>      const: 1
> 
>    "#size-cells":
>      const: 0
> 
> I am unable to overwrite this as they are const values. Microchip's 
> nand_controller is a child node of ebi unlike other nand controllers 
> where i need to overwrite this. I didn't inherit nand-controller.yaml to 
> has this defined locally.

It is matching on the node name. More below...

> 
> I upgraded dtschema and ran dt_binding_check and dtb_check again for all 
> the bindings in this series as recommended in v2 comments. But I don't 
> get the error below
> 
> https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250311122847.90081-2-balamanikandan.gunasundar@microchip.com/
> 
> I am not sure what else I am missing. Your comments please?
> 
> Bala.
> 
> 
> > +
> > +  atmel,nfc-io:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: phandle to the NFC IO block. Only applicable for atmel,sama5d3-nand-controller
> > +
> > +  atmel,nfc-sram:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: phandle to the NFC SRAM block. Only applicable for atmel,sama5d3-nand-controller
> > +
> > +required:
> > +  - compatible
> > +  - ranges
> > +  - "#address-cells"
> > +  - "#size-cells"
> > +
> > +patternProperties:
> > +  "^nand@[a-f0-9]$":
> > +    type: object
> > +    $ref: raw-nand-chip.yaml#
> > +    description:
> > +      NAND chip bindings.
> > +
> > +    additionalProperties: false
> > +
> > +    properties:
> > +      reg:
> > +        items:
> > +          - items:
> > +              - description: describes the CS lines assigned to the NAND device.
> > +              - description: the base offset of the memory region assigned to this device (always 0)
> > +              - description: the memory region size (always 0x800000)
> > +      rb-gpios:
> > +        description:
> > +          the GPIO(s) used to check the Ready/Busy status of the NAND.
> > +
> > +      cs-gpios:
> > +        description:
> > +          the GPIO(s) used to control the CS line.
> > +
> > +      det-gpios:
> > +        description:
> > +          the GPIO used to detect if a Smartmedia Card is present.
> > +
> > +      atmel,rb:
> > +        description: |

Don't need '|'.

> > +          an integer identifying the native Ready/Busy pin.
> > +        $ref: /schemas/types.yaml#/definitions/uint32

Constraints? I'd assume there's a limit much lower than 2^32.

> > +
> > +      nand-ecc-step-size:
> > +        const: 512
> > +
> > +      nand-ecc-strength:
> > +        enum: [2, 4, 8]
> > +
> > +      nand-ecc-mode:
> > +        enum: [soft, hw]
> > +
> > +      nand-bus-width:
> > +        const: 8
> > +
> > +      nand-on-flash-bbt: true
> > +
> > +      partitions:
> > +        $ref: /schemas/mtd/partitions/partitions.yaml
> > +
> > +      label:
> > +        description: Name or Label of the device
> > +
> > +    allOf:
> > +      - if:
> > +          properties:
> > +            compatible:
> > +              contains:
> > +                const: atmel,sama5d3-nand-controller
> > +        then:
> > +          properties:
> > +            "atmel,rb":
> > +              description: an integer identifying the native Ready/Busy pin.

This is wrong. This sub-schema applies to the 'nand' nodes, but 
compatible is in the parent node for which the sub-schema has no 
visibility. The 'if' is always true because 'compatible' is not present. 
The 'then' is also always true. I would just drop the constraint.

> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +    nfc_io: nfc-io@70000000 {
> > +        compatible = "atmel,sama5d3-nfc-io", "syscon";
> > +        reg = <0x70000000 0x8000000>;
> > +    };
> > +
> > +    nfc_sram: sram@200000 {
> > +        compatible = "mmio-sram";
> > +        no-memory-wc;
> > +        reg = <0x200000 0x2400>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +        ranges = <0 0x200000 0x2400>;
> > +    };
> > +
> > +    ebi@10000000 {
> > +        compatible = "atmel,sama5d3-ebi";
> > +        #address-cells = <2>;
> > +        #size-cells = <1>;
> > +        atmel,smc = <&hsmc>;
> > +        reg = <0x10000000 0x10000000
> > +               0x40000000 0x30000000>;
> > +        ranges = <0x0 0x0 0x10000000 0x10000000
> > +                  0x1 0x0 0x40000000 0x10000000
> > +                  0x2 0x0 0x50000000 0x10000000
> > +                  0x3 0x0 0x60000000 0x10000000>;
> > +        clocks = <&mck>;
> > +
> > +        nand_controller: nand-controller {
> > +            compatible = "atmel,sama5d3-nand-controller";
> > +            atmel,nfc-sram = <&nfc_sram>;
> > +            atmel,nfc-io = <&nfc_io>;
> > +            ecc-engine = <&pmecc>;
> > +            #address-cells = <2>;
> > +            #size-cells = <1>;
> > +            ranges;

I think this should be '<0x3 0x3 0x0>' to translate this from a EBI 
chipselect to the nand chip chipselect.

> > +
> > +            nand@3 {
> > +                reg = <0x3 0x0 0x800000>;

And then just 'reg = <3>;' here.

That assumes changing this would work with the existing driver.

Otherwise, we might need to add 'select: false' to nand-controller.yaml 
and make sure all the controller schemas reference it (except this one).

Rob

Re: [PATCH v3 2/4] dt-bindings: mtd: microchip-nand: add atmel pmecc

[Rob Herring (Arm)]

On Mon, 02 Jun 2025 11:05:05 +0530, Balamanikandan Gunasundar wrote:
> Add bindings for programmable multibit error correction code controller
> (PMECC).
> 
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt    | 61 ------------------
>  .../bindings/mtd/microchip,pmecc.yaml         | 62 +++++++++++++++++++
>  2 files changed, 62 insertions(+), 61 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>