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From: "Irving-CH Lin (林建弘)" <Irving-CH.Lin@mediatek.com>
To: "sboyd@kernel.org" <sboyd@kernel.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"ulf.hansson@linaro.org" <ulf.hansson@linaro.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"richardcochran@gmail.com" <richardcochran@gmail.com>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>
Cc: "Qiqi Wang (王琦琦)" <Qiqi.Wang@mediatek.com>,
	"Jh Hsu (許希孜)" <Jh.Hsu@mediatek.com>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"Vince-WL Liu (劉文龍)" <Vince-WL.Liu@mediatek.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Sirius Wang (王皓昱)" <Sirius.Wang@mediatek.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"Hanchien Lin (林翰謙)" <Hanchien.Lin@mediatek.com>
Subject: Re: [PATCH v3 20/21] pmdomain: mediatek: Add bus protect control flow for MT8189
Date: Wed, 10 Dec 2025 10:30:23 +0000	[thread overview]
Message-ID: <174a8f4ec6e04ec06f4ec77345615bd3e0f7671c.camel@mediatek.com> (raw)
In-Reply-To: <6f1bbbc7-ca54-43f9-953d-725902af7b10@collabora.com>

Hi Angelo,

On Fri, 2025-11-07 at 11:36 +0100, AngeloGioacchino Del Regno wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 06/11/25 13:42, irving.ch.lin ha scritto:
> > From: Irving-CH Lin <irving-ch.lin@mediatek.com>
> > 
> > In MT8189 mminfra power domain, the bus protect policy separates
> > into two parts, one is set before subsys clocks enabled, and
> > another
> > need to enable after subsys clocks enable.
> > 
> > Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
> > ---
> >   drivers/pmdomain/mediatek/mtk-pm-domains.c | 31
> > ++++++++++++++++++----
> >   drivers/pmdomain/mediatek/mtk-pm-domains.h |  5 ++++
> >   2 files changed, 31 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c
> > b/drivers/pmdomain/mediatek/mtk-pm-domains.c
> > index 164c6b519af3..222846e52daf 100644
> > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
> > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
> > @@ -250,7 +250,7 @@ static int scpsys_bus_protect_set(struct
> > scpsys_domain *pd,
> >                                       MTK_POLL_DELAY_US,
> > MTK_POLL_TIMEOUT);
> >   }
> > 
> > -static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
> > +static int scpsys_bus_protect_enable(struct scpsys_domain *pd, u8
> > flags)
> >   {
> >       for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
> >               const struct scpsys_bus_prot_data *bpd = &pd->data-
> > >bp_cfg[i];
> > @@ -259,6 +259,10 @@ static int scpsys_bus_protect_enable(struct
> > scpsys_domain *pd)
> >               if (!bpd->bus_prot_set_clr_mask)
> >                       break;
> > 
> > +             if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
> > +                 (flags & BUS_PROT_IGNORE_SUBCLK))
> > +                     continue;
> > +
> >               if (bpd->flags & BUS_PROT_INVERTED)
> >                       ret = scpsys_bus_protect_clear(pd, bpd);
> >               else
> > @@ -270,7 +274,7 @@ static int scpsys_bus_protect_enable(struct
> > scpsys_domain *pd)
> >       return 0;
> >   }
> > 
> > -static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
> > +static int scpsys_bus_protect_disable(struct scpsys_domain *pd, u8
> > flags)
> >   {
> >       for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
> >               const struct scpsys_bus_prot_data *bpd = &pd->data-
> > >bp_cfg[i];
> > @@ -279,6 +283,10 @@ static int scpsys_bus_protect_disable(struct
> > scpsys_domain *pd)
> >               if (!bpd->bus_prot_set_clr_mask)
> >                       continue;
> > 
> > +             if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
> 
> Is that the right name for this flag?
> 
> As far as I understand, you have to set bus protection in two steps,
> right?
> So in the first step you're setting bus protection for the MM_INFRA
> and for
> MM_INFRA_2ND - and in the second step you're setting MM_INFRA_IGN and
> 2_IGN.
> 
> So the first step (the prots with BUS_PROT_IGNORE_SUBCLK) unlocks
> SUBSYS clks
> and SRAM ISO access, the second one does the rest.
> 
> I think that a better name for this, at this point would be...
> 
> if ((bpd->flags & local_flags) & BUS_PROT_SRAM_PROTECTION)
>         continue;
> 
> What do you think?
> 
> Regards,
> Angelo
> 
Yes, the purpose is to set bus with two steps:
In general case, bus protection needs to control after subsys clock
enabled. But on MT8189 MM_INFRA subsys, some bus protection set before
subsys clock enabled.

So here i name bus protection setting w/o subsys clock as
IGNORE_SUBCLK.

thanks

BR,
irving

> > +                 (flags & BUS_PROT_IGNORE_SUBCLK))
> > +                     continue;
> > +
> >               if (bpd->flags & BUS_PROT_INVERTED)
> >                       ret = scpsys_bus_protect_set(pd, bpd);
> >               else
> > @@ -632,6 +640,15 @@ static int scpsys_power_on(struct
> > generic_pm_domain *genpd)
> >       if (ret)
> >               goto err_pwr_ack;
> > 
> > +     /*
> > +      * In MT8189 mminfra power domain, the bus protect policy
> > separates
> > +      * into two parts, one is set before subsys clocks enabled,
> > and another
> > +      * need to enable after subsys clocks enable.
> > +      */
> > +     ret = scpsys_bus_protect_disable(pd, BUS_PROT_IGNORE_SUBCLK);
> > +     if (ret < 0)
> > +             goto err_pwr_ack;
> > +
> >       /*
> >        * In few Mediatek platforms(e.g. MT6779), the bus protect
> > policy is
> >        * stricter, which leads to bus protect release must be prior
> > to bus
> > @@ -648,7 +665,7 @@ static int scpsys_power_on(struct
> > generic_pm_domain *genpd)
> >       if (ret < 0)
> >               goto err_disable_subsys_clks;
> > 
> > -     ret = scpsys_bus_protect_disable(pd);
> > +     ret = scpsys_bus_protect_disable(pd, 0);
> >       if (ret < 0)
> >               goto err_disable_sram;
> > 
> > @@ -662,7 +679,7 @@ static int scpsys_power_on(struct
> > generic_pm_domain *genpd)
> >       return 0;
> > 
> >   err_enable_bus_protect:
> > -     scpsys_bus_protect_enable(pd);
> > +     scpsys_bus_protect_enable(pd, 0);
> >   err_disable_sram:
> >       scpsys_sram_disable(pd);
> >   err_disable_subsys_clks:
> > @@ -683,7 +700,7 @@ static int scpsys_power_off(struct
> > generic_pm_domain *genpd)
> >       bool tmp;
> >       int ret;
> > 
> > -     ret = scpsys_bus_protect_enable(pd);
> > +     ret = scpsys_bus_protect_enable(pd, 0);
> >       if (ret < 0)
> >               return ret;
> > 
> > @@ -697,6 +714,10 @@ static int scpsys_power_off(struct
> > generic_pm_domain *genpd)
> > 
> >       clk_bulk_disable_unprepare(pd->num_subsys_clks, pd-
> > >subsys_clks);
> > 
> > +     ret = scpsys_bus_protect_enable(pd, BUS_PROT_IGNORE_SUBCLK);
> > +     if (ret < 0)
> > +             return ret;
> > +
> >       if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
> >               scpsys_modem_pwrseq_off(pd);
> >       else
> > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h
> > b/drivers/pmdomain/mediatek/mtk-pm-domains.h
> > index f608e6ec4744..a5dca24cbc2f 100644
> > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h
> > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h
> > @@ -56,6 +56,7 @@ enum scpsys_bus_prot_flags {
> >       BUS_PROT_REG_UPDATE = BIT(1),
> >       BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> >       BUS_PROT_INVERTED = BIT(3),
> > +     BUS_PROT_IGNORE_SUBCLK = BIT(4),
> >   };
> > 
> >   enum scpsys_bus_prot_block {
> > @@ -95,6 +96,10 @@ enum scpsys_bus_prot_block {
> >               _BUS_PROT(_hwip, _mask, _set, _clr, _mask,
> > _sta,        \
> >                         BUS_PROT_REG_UPDATE)
> > 
> > +#define BUS_PROT_WR_IGN_SUBCLK(_hwip, _mask, _set, _clr,
> > _sta)               \
> > +             _BUS_PROT(_hwip, _mask, _set, _clr, _mask,
> > _sta,        \
> > +                       BUS_PROT_IGNORE_CLR_ACK |
> > BUS_PROT_IGNORE_SUBCLK)
> > +
> >   #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask)                 \
> >               BUS_PROT_UPDATE(INFRA, _mask,                   \
> >                               INFRA_TOPAXI_PROTECTEN,         \
> 
> 


  reply	other threads:[~2025-12-10 10:45 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-06 12:41 [PATCH v3 00/21] Add support for MT8189 clock/power controller irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 01/21] dt-bindings: clock: mediatek: Add MT8189 clock definitions irving.ch.lin
2025-11-06 17:19   ` Conor Dooley
2025-12-10 10:01     ` Irving-CH Lin (林建弘)
2025-12-10 16:33       ` Conor Dooley
2025-11-07  7:27   ` Krzysztof Kozlowski
2025-11-27 10:30   ` Louis-Alexis Eyraud
2025-11-06 12:41 ` [PATCH v3 02/21] dt-bindings: power: mediatek: Add MT8189 power domain definitions irving.ch.lin
2025-11-06 13:34   ` Rob Herring (Arm)
2025-11-06 17:17     ` Conor Dooley
2025-11-07  7:26       ` Krzysztof Kozlowski
2025-11-07 16:58         ` Conor Dooley
2025-11-06 12:41 ` [PATCH v3 03/21] clk: mediatek: fix mfg mux issue irving.ch.lin
2025-11-07  9:34   ` AngeloGioacchino Del Regno
2025-11-06 12:41 ` [PATCH v3 04/21] clk: mediatek: Add MT8189 apmixedsys clock support irving.ch.lin
2025-11-27 12:04   ` Louis-Alexis Eyraud
2025-11-06 12:41 ` [PATCH v3 05/21] clk: mediatek: Add MT8189 topckgen " irving.ch.lin
2025-11-27 13:46   ` Louis-Alexis Eyraud
2025-12-10 10:41     ` Irving-CH Lin (林建弘)
2025-11-06 12:41 ` [PATCH v3 06/21] clk: mediatek: Add MT8189 vlpckgen " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 07/21] clk: mediatek: Add MT8189 vlpcfg " irving.ch.lin
2025-11-27 16:03   ` Louis-Alexis Eyraud
2025-11-06 12:41 ` [PATCH v3 08/21] clk: mediatek: Add MT8189 bus " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 09/21] clk: mediatek: Add MT8189 cam " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 10/21] clk: mediatek: Add MT8189 dbgao " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 11/21] clk: mediatek: Add MT8189 dvfsrc " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 12/21] clk: mediatek: Add MT8189 i2c " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 13/21] clk: mediatek: Add MT8189 img " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 14/21] clk: mediatek: Add MT8189 mdp " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 15/21] clk: mediatek: Add MT8189 mfg " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 16/21] clk: mediatek: Add MT8189 mmsys " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 17/21] clk: mediatek: Add MT8189 scp " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 18/21] clk: mediatek: Add MT8189 ufs " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 19/21] clk: mediatek: Add MT8189 vcodec " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 20/21] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin
2025-11-07 10:36   ` AngeloGioacchino Del Regno
2025-12-10 10:30     ` Irving-CH Lin (林建弘) [this message]
2025-11-06 12:42 ` [PATCH v3 21/21] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin

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