From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CFB83085C7; Wed, 18 Jun 2025 18:52:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750272764; cv=none; b=qP7N569x8TxGkQeanHTXZLJ7BYsZ0C8oyJ2Jbyasn/mMHYBcB3IzsqWqeG6bK4CeCZn8MAPm1PbV8+DLzqC+L1KODe8P+C9w6EAcO9O/J6qS6+IQlEAeGSKV3zq8Mlu+mAAxZ4ZgA3fdY+k9oxlJOiePAYzkzLl//4iTWlzGvPs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750272764; c=relaxed/simple; bh=eT+6E7j8MKpA8+JuN8R6/MizW9cXPn/MID8D+godm0c=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=icAGdCk6IVsNicjVpbu76OefC0SPwOVhpRjaCAGKN3ExZE4xtRzAlzgU0AyfOrP7kqtWEEQP5weIq2A2KyNibYUZ7HxJH1D472wB75vXfLI/q8Mb/haBB1bHNA/0xkfnFmC93kkpV0sjZr/LEm7YlxcTtPHvt6hRU6BB6UKGLOM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e14iU62k; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e14iU62k" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7EA7DC4CEE7; Wed, 18 Jun 2025 18:52:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750272763; bh=eT+6E7j8MKpA8+JuN8R6/MizW9cXPn/MID8D+godm0c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=e14iU62kh532Ydae2EKi/eDJxL/gMzuUZYstiZIrzXP54BHZd0y5VwL1wkYK+QDGX F3AFZ9wL4NL1dpyvtxuFRG8tirtdcv315QCN8nNaayXQXDWYUyzqnhQx9w2sPsgYz0 +EZHmF0n9J0RrasBf89OH6yxWdjGdhsac+QmfqB4RqEMJsAsfx3SoNIrA4oiCUWhNh lEciGngaQJLAKAyhA+I2rTf6P4Pm9vd46BRUIOhNa5MEXCrLkd2ut4VD/znDZIuRiC 2fALmk4jeJCzNOFm680tjXnOsfC6J/rxsQsXwb6KJRFXYPSBYteOVWqNrGQbgDGqWX AE6VYyVduXLwQ== Date: Wed, 18 Jun 2025 13:52:41 -0500 From: "Rob Herring (Arm)" To: Lorenzo Pieralisi Cc: Thomas Gleixner , Jonathan Cameron , Catalin Marinas , Sascha Bischoff , Bjorn Helgaas , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Peter Maydell , Timothy Hayes , Jiri Slaby , Marc Zyngier , Conor Dooley , linux-pci@vger.kernel.org, "Liam R. Howlett" , linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Will Deacon , Mark Rutland , Arnd Bergmann Subject: Re: [PATCH v5 01/27] dt-bindings: interrupt-controller: Add Arm GICv5 Message-ID: <175027275990.2508078.7812820935724706534.robh@kernel.org> References: <20250618-gicv5-host-v5-0-d9e622ac5539@kernel.org> <20250618-gicv5-host-v5-1-d9e622ac5539@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250618-gicv5-host-v5-1-d9e622ac5539@kernel.org> On Wed, 18 Jun 2025 12:17:16 +0200, Lorenzo Pieralisi wrote: > The GICv5 interrupt controller architecture is composed of: > > - one or more Interrupt Routing Service (IRS) > - zero or more Interrupt Translation Service (ITS) > - zero or more Interrupt Wire Bridge (IWB) > > Describe a GICv5 implementation by specifying a top level node > corresponding to the GICv5 system component. > > IRS nodes are added as GICv5 system component children. > > An ITS is associated with an IRS so ITS nodes are described > as IRS children - use the hierarchy explicitly in the device > tree to define the association. > > IWB nodes are described as a separate schema. > > An IWB is connected to a single ITS, the connection is made explicit > through the msi-parent property and therefore is not required to be > explicit through a parent-child relationship in the device tree. > > Signed-off-by: Lorenzo Pieralisi > Cc: Conor Dooley > Cc: Rob Herring > Cc: Krzysztof Kozlowski > Cc: Marc Zyngier > --- > .../interrupt-controller/arm,gic-v5-iwb.yaml | 78 ++++++ > .../bindings/interrupt-controller/arm,gic-v5.yaml | 267 +++++++++++++++++++++ > MAINTAINERS | 7 + > 3 files changed, 352 insertions(+) > Reviewed-by: Rob Herring (Arm)