* [PATCH v3 00/10] Add support for the Axis ARTPEC-8 SoC [not found] <CGME20250825120654epcas5p17bdbd92679d2b4c0f0c9bbb348163c0b@epcas5p1.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel [not found] ` <CGME20250825120659epcas5p47ea3377840efb9ce3d5901a27c85e4ed@epcas5p4.samsung.com> ` (10 more replies) 0 siblings, 11 replies; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc Add basic support for the Axis ARTPEC-8 SoC which contains quad-core Cortex-A53 CPU and other several IPs. This SoC is an Axis-designed chipset used in surveillance camera products such as the AXIS Q1656-LE and AXIS Q3538-LVE. This ARTPEC-8 SoC has a variety of Samsung-specific IP blocks and Axis-specific IP blocks and SoC is manufactured by Samsung Foundry. List of Samsung-provided IPs: - UART - Ethernet (Vendor: Synopsys) - SDIO - SPI - HSI2C - I2S - CMU (Clock Management Unit) - Pinctrl (GPIO) - PCIe (Vendor: Synopsys) - USB (Vendor: Synopsys) List of Axis-provided IPs: - VIP (Image Sensor Processing IP) - VPP (Video Post Processing) - GPU - CDC (Video Encoder) This patch series includes below changes: - CMU (Clock Management Unit) driver and its bindings - GPIO pinctrl configuration and its bindings - Basic Device Tree for ARTPEC-8 SoC and boards The patch series has been tested on the ARTPEC-8 EVB with Linux v6.15-rc5 and intended to be merged via the `arm-soc` tree. --- Changes in v3: - Rebased patchset on linux-samsung-soc "for-next" branch which includes round_rate() drop - Add CPU mask in dtsi patch #8 Link to v2: https://lore.kernel.org/all/20250821123310.94089-1-ravi.patel@samsung.com/ --- Changes in v2: - Update SoB sections in all patches - Update the copyright year to 2025 - Add CMU abbreviation description - Merge dt-bindings patch 01 and 02 into single patch - Modify yaml file to fit coding style in CMU - Modify clock-names - Reorder config macros to fit coding style - Remove the unused macro in clock driver code - Squash all clock driver patches (4 to 10) into single patch - Split yaml conversion patch translation and add ARTPEC-8 SoC - Remove "clock-frequency" property from cpu node in dtsi - Remove the "status" property in dts and dtsi - Reorder the DTS and pin nodes to follow the alphabetical and DTS coding style - Change items property in axis.yaml - Move dts files to exynos folder - Removed ARCH_ARTPEC8 from platform Kconfig - Add pattern in MAINTAINER file - Merge dtsi and pinctrl dtsi file - Split board dts file Link to v1: https://lore.kernel.org/all/20250710002047.1573841-1-ksk4725@coasia.com/ NOTE: The first version has been sent by Coasia. After that, it has been agreed between Coasia and Samsung that Samsung will take ownership of upstreaming ARTPEC-8 and ARTPEC-9 platforms. --- Hakyeong Kim (3): dt-bindings: clock: Add ARTPEC-8 clock controller clk: samsung: Add clock PLL support for ARTPEC-8 SoC clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC Ravi Patel (1): dt-bindings: arm: Convert Axis board/soc bindings to json-schema SeonGu Kang (3): dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC pinctrl: samsung: Add ARTPEC-8 SoC specific configuration arm64: dts: axis: Add ARTPEC-8 Grizzly dts support SungMin Park (3): dt-bindings: arm: axis: Add ARTPEC-8 grizzly board arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support arm64: defconfig: Enable Axis ARTPEC SoC .../devicetree/bindings/arm/axis.txt | 13 - .../devicetree/bindings/arm/axis.yaml | 36 + .../bindings/clock/axis,artpec8-clock.yaml | 213 ++++ .../bindings/pinctrl/samsung,pinctrl.yaml | 1 + MAINTAINERS | 12 + arch/arm64/Kconfig.platforms | 7 + arch/arm64/boot/dts/exynos/Makefile | 1 + arch/arm64/boot/dts/exynos/axis/Makefile | 4 + .../boot/dts/exynos/axis/artpec-pinctrl.h | 36 + .../boot/dts/exynos/axis/artpec8-grizzly.dts | 35 + .../boot/dts/exynos/axis/artpec8-pinctrl.dtsi | 120 ++ arch/arm64/boot/dts/exynos/axis/artpec8.dtsi | 244 ++++ arch/arm64/configs/defconfig | 1 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-artpec8.c | 1044 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 128 +- drivers/clk/samsung/clk-pll.h | 2 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 50 + drivers/pinctrl/samsung/pinctrl-exynos.h | 10 + drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + include/dt-bindings/clock/axis,artpec8-clk.h | 169 +++ 22 files changed, 2116 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml create mode 100644 arch/arm64/boot/dts/exynos/axis/Makefile create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8.dtsi create mode 100644 drivers/clk/samsung/clk-artpec8.c create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h -- 2.49.0 ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <CGME20250825120659epcas5p47ea3377840efb9ce3d5901a27c85e4ed@epcas5p4.samsung.com>]
* [PATCH v3 01/10] dt-bindings: clock: Add ARTPEC-8 clock controller [not found] ` <CGME20250825120659epcas5p47ea3377840efb9ce3d5901a27c85e4ed@epcas5p4.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 2025-08-31 13:28 ` (subset) " Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc From: Hakyeong Kim <hgkim05@coasia.com> Add dt-schema for Axis ARTPEC-8 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS - CMU_IMEM - CMU_PERI Signed-off-by: Hakyeong Kim <hgkim05@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- .../bindings/clock/axis,artpec8-clock.yaml | 213 ++++++++++++++++++ include/dt-bindings/clock/axis,artpec8-clk.h | 169 ++++++++++++++ 2 files changed, 382 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml new file mode 100644 index 000000000000..277af48ac841 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC-8 SoC clock controller + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +description: | + ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit) + units, generating clocks for different domains. Those CMU units are modeled + as separate device tree nodes, and might depend on each other. + The root clock in that root tree is an external clock: OSCCLK (25 MHz). + This external clock must be defined as a fixed-rate clock in dts. + + CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_CMU. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/axis,artpec8-clk.h' header. + +properties: + compatible: + enum: + - axis,artpec8-cmu-cmu + - axis,artpec8-cmu-bus + - axis,artpec8-cmu-core + - axis,artpec8-cmu-cpucl + - axis,artpec8-cmu-fsys + - axis,artpec8-cmu-imem + - axis,artpec8-cmu-peri + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + const: axis,artpec8-cmu-cmu + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + const: axis,artpec8-cmu-bus + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_BUS BUS clock (from CMU_CMU) + - description: CMU_BUS DLP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: bus + - const: dlp + + - if: + properties: + compatible: + const: axis,artpec8-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CORE main clock (from CMU_CMU) + - description: CMU_CORE DLP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: main + - const: dlp + + - if: + properties: + compatible: + const: axis,artpec8-cmu-cpucl + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CPUCL switch clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: switch + + - if: + properties: + compatible: + const: axis,artpec8-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_FSYS SCAN0 clock (from CMU_CMU) + - description: CMU_FSYS SCAN1 clock (from CMU_CMU) + - description: CMU_FSYS BUS clock (from CMU_CMU) + - description: CMU_FSYS IP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: scan0 + - const: scan1 + - const: bus + - const: ip + + - if: + properties: + compatible: + const: axis,artpec8-cmu-imem + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_IMEM ACLK clock (from CMU_CMU) + - description: CMU_IMEM JPEG clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: aclk + - const: jpeg + + - if: + properties: + compatible: + const: axis,artpec8-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_PERI IP clock (from CMU_CMU) + - description: CMU_PERI AUDIO clock (from CMU_CMU) + - description: CMU_PERI DISP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: ip + - const: audio + - const: disp + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS + - | + #include <dt-bindings/clock/axis,artpec8-clk.h> + + cmu_fsys: clock-controller@16c10000 { + compatible = "axis,artpec8-cmu-fsys"; + reg = <0x16c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; + clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; + }; + +... diff --git a/include/dt-bindings/clock/axis,artpec8-clk.h b/include/dt-bindings/clock/axis,artpec8-clk.h new file mode 100644 index 000000000000..1e6e1409dd94 --- /dev/null +++ b/include/dt-bindings/clock/axis,artpec8-clk.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + * + * Device Tree binding constants for ARTPEC-8 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H +#define _DT_BINDINGS_CLOCK_ARTPEC8_H + +/* CMU_CMU */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_DOUT_SHARED0_DIV2 2 +#define CLK_DOUT_SHARED0_DIV3 3 +#define CLK_DOUT_SHARED0_DIV4 4 +#define CLK_FOUT_SHARED1_PLL 5 +#define CLK_DOUT_SHARED1_DIV2 6 +#define CLK_DOUT_SHARED1_DIV3 7 +#define CLK_DOUT_SHARED1_DIV4 8 +#define CLK_FOUT_AUDIO_PLL 9 +#define CLK_DOUT_CMU_BUS 10 +#define CLK_DOUT_CMU_BUS_DLP 11 +#define CLK_DOUT_CMU_CDC_CORE 12 +#define CLK_DOUT_CMU_OTP 13 +#define CLK_DOUT_CMU_CORE_MAIN 14 +#define CLK_DOUT_CMU_CORE_DLP 15 +#define CLK_DOUT_CMU_CPUCL_SWITCH 16 +#define CLK_DOUT_CMU_DLP_CORE 17 +#define CLK_DOUT_CMU_FSYS_BUS 18 +#define CLK_DOUT_CMU_FSYS_IP 19 +#define CLK_DOUT_CMU_FSYS_SCAN0 20 +#define CLK_DOUT_CMU_FSYS_SCAN1 21 +#define CLK_DOUT_CMU_GPU_3D 22 +#define CLK_DOUT_CMU_GPU_2D 23 +#define CLK_DOUT_CMU_IMEM_ACLK 24 +#define CLK_DOUT_CMU_IMEM_JPEG 25 +#define CLK_DOUT_CMU_MIF_SWITCH 26 +#define CLK_DOUT_CMU_MIF_BUSP 27 +#define CLK_DOUT_CMU_PERI_DISP 28 +#define CLK_DOUT_CMU_PERI_IP 29 +#define CLK_DOUT_CMU_PERI_AUDIO 30 +#define CLK_DOUT_CMU_RSP_CORE 31 +#define CLK_DOUT_CMU_TRFM_CORE 32 +#define CLK_DOUT_CMU_VCA_ACE 33 +#define CLK_DOUT_CMU_VCA_OD 34 +#define CLK_DOUT_CMU_VIO_CORE 35 +#define CLK_DOUT_CMU_VIO_AUDIO 36 +#define CLK_DOUT_CMU_VIP0_CORE 37 +#define CLK_DOUT_CMU_VIP1_CORE 38 +#define CLK_DOUT_CMU_VPP_CORE 39 + +/* CMU_BUS */ +#define CLK_MOUT_BUS_ACLK_USER 1 +#define CLK_MOUT_BUS_DLP_USER 2 +#define CLK_DOUT_BUS_PCLK 3 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_ACLK_USER 1 +#define CLK_MOUT_CORE_DLP_USER 2 +#define CLK_DOUT_CORE_PCLK 3 + +/* CMU_CPUCL */ +#define CLK_FOUT_CPUCL_PLL 1 +#define CLK_MOUT_CPUCL_PLL 2 +#define CLK_MOUT_CPUCL_SWITCH_USER 3 +#define CLK_DOUT_CPUCL_CPU 4 +#define CLK_DOUT_CPUCL_CLUSTER_ACLK 5 +#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG 6 +#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK 7 +#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 8 +#define CLK_DOUT_CPUCL_PCLK 9 +#define CLK_DOUT_CPUCL_CMUREF 10 +#define CLK_DOUT_CPUCL_DBG 11 +#define CLK_DOUT_CPUCL_PCLKDBG 12 +#define CLK_GOUT_CPUCL_CLUSTER_CPU 13 +#define CLK_GOUT_CPUCL_SHORTSTOP 14 +#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 15 +#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 16 + +/* CMU_FSYS */ +#define CLK_FOUT_FSYS_PLL 1 +#define CLK_MOUT_FSYS_SCAN0_USER 2 +#define CLK_MOUT_FSYS_SCAN1_USER 3 +#define CLK_MOUT_FSYS_BUS_USER 4 +#define CLK_MOUT_FSYS_MMC_USER 5 +#define CLK_DOUT_FSYS_PCIE_PIPE 6 +#define CLK_DOUT_FSYS_ADC 7 +#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL 8 +#define CLK_DOUT_FSYS_EQOS_INT125 9 +#define CLK_DOUT_FSYS_OTP_MEM 10 +#define CLK_DOUT_FSYS_SCLK_UART 11 +#define CLK_DOUT_FSYS_EQOS_25 12 +#define CLK_DOUT_FSYS_EQOS_2p5 13 +#define CLK_DOUT_FSYS_BUS300 14 +#define CLK_DOUT_FSYS_BUS_QSPI 15 +#define CLK_DOUT_FSYS_MMC_CARD0 16 +#define CLK_DOUT_FSYS_MMC_CARD1 17 +#define CLK_DOUT_SCAN_CLK_FSYS_125 18 +#define CLK_DOUT_FSYS_QSPI 19 +#define CLK_DOUT_FSYS_SFMC_NAND 20 +#define CLK_DOUT_FSYS_SCAN_CLK_MMC 21 +#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 22 +#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 23 +#define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK 24 +#define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK 25 +#define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK 26 +#define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK 27 +#define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0 28 +#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 29 +#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG 30 +#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 31 +#define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK 32 +#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I 33 +#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I 34 +#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5 35 +#define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND 36 +#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN 37 +#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK 38 +#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN 39 +#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK 40 +#define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN 41 +#define CLK_GOUT_FSYS_UART0_PCLK 42 +#define CLK_GOUT_FSYS_UART0_SCLK_UART 43 +#define CLK_GOUT_FSYS_BUS_QSPI 44 +#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK 45 +#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK 46 + +/* CMU_IMEM */ +#define CLK_MOUT_IMEM_ACLK_USER 1 +#define CLK_MOUT_IMEM_GIC_CA53 2 +#define CLK_MOUT_IMEM_GIC_CA5 3 +#define CLK_MOUT_IMEM_JPEG_USER 4 +#define CLK_GOUT_IMEM_MCT_PCLK 5 +#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 6 + +/* CMU_PERI */ +#define CLK_MOUT_PERI_IP_USER 1 +#define CLK_MOUT_PERI_AUDIO_USER 2 +#define CLK_MOUT_PERI_I2S0 3 +#define CLK_MOUT_PERI_I2S1 4 +#define CLK_MOUT_PERI_DISP_USER 5 +#define CLK_DOUT_PERI_SPI 6 +#define CLK_DOUT_PERI_UART1 7 +#define CLK_DOUT_PERI_UART2 8 +#define CLK_DOUT_PERI_PCLK 9 +#define CLK_DOUT_PERI_I2S0 10 +#define CLK_DOUT_PERI_I2S1 11 +#define CLK_DOUT_PERI_DSIM 12 +#define CLK_GOUT_PERI_UART1_PCLK 13 +#define CLK_GOUT_PERI_UART1_SCLK_UART 14 +#define CLK_GOUT_PERI_UART2_PCLK 15 +#define CLK_GOUT_PERI_UART2_SCLK_UART 16 +#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 17 +#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 18 +#define CLK_GOUT_PERI_SPI0_PCLK 19 +#define CLK_GOUT_PERI_SPI0_SCLK_SPI 20 +#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 21 +#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST 22 +#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST 23 +#define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK 24 +#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK 25 +#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK 26 +#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 27 +#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 28 + +#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */ -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: (subset) [PATCH v3 01/10] dt-bindings: clock: Add ARTPEC-8 clock controller 2025-08-25 11:44 ` [PATCH v3 01/10] dt-bindings: clock: Add ARTPEC-8 clock controller Ravi Patel @ 2025-08-31 13:28 ` Krzysztof Kozlowski 0 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-31 13:28 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd, Ravi Patel Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On Mon, 25 Aug 2025 17:14:27 +0530, Ravi Patel wrote: > Add dt-schema for Axis ARTPEC-8 SoC clock controller. > > The Clock Management Unit (CMU) has a top-level block CMU_CMU > which generates clocks for other blocks. > > Add device-tree binding definitions for following CMU blocks: > - CMU_CMU > - CMU_BUS > - CMU_CORE > - CMU_CPUCL > - CMU_FSYS > - CMU_IMEM > - CMU_PERI > > [...] Applied, thanks! [01/10] dt-bindings: clock: Add ARTPEC-8 clock controller https://git.kernel.org/krzk/linux/c/91f98de42310c70f9a23595b3b20aa305717d955 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <CGME20250825120704epcas5p37385c913027d74d221012c4ae1550c73@epcas5p3.samsung.com>]
* [PATCH v3 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC [not found] ` <CGME20250825120704epcas5p37385c913027d74d221012c4ae1550c73@epcas5p3.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 2025-08-31 13:28 ` (subset) " Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc From: Hakyeong Kim <hgkim05@coasia.com> Add below clock PLL support for Axis ARTPEC-8 SoC platform: - pll_1017x: Integer PLL with mid frequency FVCO (950 to 2400 MHz) This is used in ARTPEC-8 SoC for shared PLL - pll_1031x: Integer/Fractional PLL with mid frequency FVCO (600 to 1200 MHz) This is used in ARTPEC-8 SoC for Audio PLL FOUT calculation for pll_1017x and pll_1031x: FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL FOUT = (((MDIV + KDIV)/65536) x FIN)/(PDIV x 2^SDIV) for fractional PLL Signed-off-by: Hakyeong Kim <hgkim05@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- drivers/clk/samsung/clk-pll.c | 128 +++++++++++++++++++++++++++++++++- drivers/clk/samsung/clk-pll.h | 2 + 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 3c04a0388ff9..7bea7be1d7e4 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -278,7 +278,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, } /* Set PLL lock time. */ - if (pll->type == pll_142xx) + if (pll->type == pll_142xx || pll->type == pll_1017x) writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, pll->lock_reg); else @@ -1330,6 +1330,125 @@ static const struct clk_ops samsung_pll531x_clk_ops = { .recalc_rate = samsung_pll531x_recalc_rate, }; +/* + * PLL1031x Clock Type + */ +#define PLL1031X_LOCK_FACTOR (500) + +#define PLL1031X_MDIV_MASK (0x3ff) +#define PLL1031X_PDIV_MASK (0x3f) +#define PLL1031X_SDIV_MASK (0x7) +#define PLL1031X_MDIV_SHIFT (16) +#define PLL1031X_PDIV_SHIFT (8) +#define PLL1031X_SDIV_SHIFT (0) + +#define PLL1031X_KDIV_MASK (0xffff) +#define PLL1031X_KDIV_SHIFT (0) +#define PLL1031X_MFR_MASK (0x3f) +#define PLL1031X_MRR_MASK (0x1f) +#define PLL1031X_MFR_SHIFT (16) +#define PLL1031X_MRR_SHIFT (24) + +static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3; + u64 fvco = parent_rate; + + pll_con0 = readl_relaxed(pll->con_reg); + pll_con3 = readl_relaxed(pll->con_reg + 0xc); + mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK; + pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK; + sdiv = (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK; + kdiv = (pll_con3 & PLL1031X_KDIV_MASK); + + fvco *= (mdiv << PLL1031X_MDIV_SHIFT) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>= PLL1031X_MDIV_SHIFT; + + return (unsigned long)fvco; +} + +static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3, + const struct samsung_pll_rate_table *rate) +{ + u32 old_mdiv, old_pdiv, old_kdiv; + + old_mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK; + old_pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK; + old_kdiv = (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK; + + return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv || + old_kdiv != rate->kdiv); +} + +static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 con0, con3; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + con0 = readl_relaxed(pll->con_reg); + con3 = readl_relaxed(pll->con_reg + 0xc); + + if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) { + /* If only s change, change just s value only */ + con0 &= ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT); + con0 |= rate->sdiv << PLL1031X_SDIV_SHIFT; + writel_relaxed(con0, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg); + + /* Set PLL M, P, and S values. */ + con0 &= ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) | + (PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) | + (PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT)); + + con0 |= (rate->mdiv << PLL1031X_MDIV_SHIFT) | + (rate->pdiv << PLL1031X_PDIV_SHIFT) | + (rate->sdiv << PLL1031X_SDIV_SHIFT); + + /* Set PLL K, MFR and MRR values. */ + con3 = readl_relaxed(pll->con_reg + 0xc); + con3 &= ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) | + (PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) | + (PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT)); + con3 |= (rate->kdiv << PLL1031X_KDIV_SHIFT) | + (rate->mfr << PLL1031X_MFR_SHIFT) | + (rate->mrr << PLL1031X_MRR_SHIFT); + + /* Write configuration to PLL */ + writel_relaxed(con0, pll->con_reg); + writel_relaxed(con3, pll->con_reg + 0xc); + + /* Wait for PLL lock if the PLL is enabled */ + return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); +} + +static const struct clk_ops samsung_pll1031x_clk_ops = { + .recalc_rate = samsung_pll1031x_recalc_rate, + .determine_rate = samsung_pll_determine_rate, + .set_rate = samsung_pll1031x_set_rate, +}; + +static const struct clk_ops samsung_pll1031x_clk_min_ops = { + .recalc_rate = samsung_pll1031x_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, const struct samsung_pll_clock *pll_clk) { @@ -1378,6 +1497,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1451x: case pll_1452x: case pll_142xx: + case pll_1017x: pll->enable_offs = PLL35XX_ENABLE_SHIFT; pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) @@ -1473,6 +1593,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_4311: init.ops = &samsung_pll531x_clk_ops; break; + case pll_1031x: + if (!pll->rate_table) + init.ops = &samsung_pll1031x_clk_min_ops; + else + init.ops = &samsung_pll1031x_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index e9a5f8e0e0a3..6c8bb7f26da5 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -49,6 +49,8 @@ enum samsung_pll_type { pll_0718x, pll_0732x, pll_4311, + pll_1017x, + pll_1031x, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: (subset) [PATCH v3 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC 2025-08-25 11:44 ` [PATCH v3 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC Ravi Patel @ 2025-08-31 13:28 ` Krzysztof Kozlowski 0 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-31 13:28 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd, Ravi Patel Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On Mon, 25 Aug 2025 17:14:28 +0530, Ravi Patel wrote: > Add below clock PLL support for Axis ARTPEC-8 SoC platform: > - pll_1017x: Integer PLL with mid frequency FVCO (950 to 2400 MHz) > This is used in ARTPEC-8 SoC for shared PLL > > - pll_1031x: Integer/Fractional PLL with mid frequency FVCO > (600 to 1200 MHz) > This is used in ARTPEC-8 SoC for Audio PLL > > [...] Applied, thanks! [02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC https://git.kernel.org/krzk/linux/c/80770fccb7f60b0bc795852c154273e511f296a0 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <CGME20250825120710epcas5p421c3c8169019599e76f782bb7086e0e1@epcas5p4.samsung.com>]
* [PATCH v3 03/10] clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC [not found] ` <CGME20250825120710epcas5p421c3c8169019599e76f782bb7086e0e1@epcas5p4.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 2025-08-31 13:28 ` (subset) " Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc, Varada Pavani From: Hakyeong Kim <hgkim05@coasia.com> Add initial clock support for Axis ARTPEC-8 SoC which is required for enabling basic clock management. Add clock support for below CMU (Clock Management Unit) blocks in ARTPEC-8 SoC: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS - CMU_IMEM - CMU_PERI Signed-off-by: Hakyeong Kim <hgkim05@coasia.com> Signed-off-by: Varada Pavani <v.pavani@samsung.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-artpec8.c | 1044 +++++++++++++++++++++++++++++ 2 files changed, 1045 insertions(+) create mode 100644 drivers/clk/samsung/clk-artpec8.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b77fe288e4bb..ef464f434740 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5420.o obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-artpec8.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c new file mode 100644 index 000000000000..0ea7c8b58674 --- /dev/null +++ b/drivers/clk/samsung/clk-artpec8.c @@ -0,0 +1,1044 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + * + * Common Clock Framework support for ARTPEC-8 SoC. + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include <dt-bindings/clock/axis,artpec8-clk.h> + +#include "clk.h" +#include "clk-exynos-arm64.h" + +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CMU_CMU_NR_CLK (CLK_DOUT_CMU_VPP_CORE + 1) +#define CMU_BUS_NR_CLK (CLK_DOUT_BUS_PCLK + 1) +#define CMU_CORE_NR_CLK (CLK_DOUT_CORE_PCLK + 1) +#define CMU_CPUCL_NR_CLK (CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK + 1) +#define CMU_FSYS_NR_CLK (CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK + 1) +#define CMU_IMEM_NR_CLK (CLK_GOUT_IMEM_PCLK_TMU0_APBIF + 1) +#define CMU_PERI_NR_CLK (CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK + 1) + +/* Register Offset definitions for CMU_CMU (0x12400000) */ +#define PLL_LOCKTIME_PLL_AUDIO 0x0000 +#define PLL_LOCKTIME_PLL_SHARED0 0x0004 +#define PLL_LOCKTIME_PLL_SHARED1 0x0008 +#define PLL_CON0_PLL_AUDIO 0x0100 +#define PLL_CON0_PLL_SHARED0 0x0120 +#define PLL_CON0_PLL_SHARED1 0x0140 +#define CLK_CON_MUX_CLKCMU_2D 0x1000 +#define CLK_CON_MUX_CLKCMU_3D 0x1004 +#define CLK_CON_MUX_CLKCMU_BUS 0x1008 +#define CLK_CON_MUX_CLKCMU_BUS_DLP 0x100c +#define CLK_CON_MUX_CLKCMU_CDC_CORE 0x1010 +#define CLK_CON_MUX_CLKCMU_FSYS_SCAN0 0x1014 +#define CLK_CON_MUX_CLKCMU_FSYS_SCAN1 0x1018 +#define CLK_CON_MUX_CLKCMU_IMEM_JPEG 0x101c +#define CLK_CON_MUX_CLKCMU_PERI_DISP 0x1020 +#define CLK_CON_MUX_CLKCMU_CORE_BUS 0x1024 +#define CLK_CON_MUX_CLKCMU_CORE_DLP 0x1028 +#define CLK_CON_MUX_CLKCMU_CPUCL_SWITCH 0x1030 +#define CLK_CON_MUX_CLKCMU_DLP_CORE 0x1034 +#define CLK_CON_MUX_CLKCMU_FSYS_BUS 0x1038 +#define CLK_CON_MUX_CLKCMU_FSYS_IP 0x103c +#define CLK_CON_MUX_CLKCMU_IMEM_ACLK 0x1054 +#define CLK_CON_MUX_CLKCMU_MIF_BUSP 0x1080 +#define CLK_CON_MUX_CLKCMU_MIF_SWITCH 0x1084 +#define CLK_CON_MUX_CLKCMU_PERI_IP 0x1088 +#define CLK_CON_MUX_CLKCMU_RSP_CORE 0x108c +#define CLK_CON_MUX_CLKCMU_TRFM_CORE 0x1090 +#define CLK_CON_MUX_CLKCMU_VCA_ACE 0x1094 +#define CLK_CON_MUX_CLKCMU_VCA_OD 0x1098 +#define CLK_CON_MUX_CLKCMU_VIO_CORE 0x109c +#define CLK_CON_MUX_CLKCMU_VIP0_CORE 0x10a0 +#define CLK_CON_MUX_CLKCMU_VIP1_CORE 0x10a4 +#define CLK_CON_MUX_CLKCMU_VPP_CORE 0x10a8 + +#define CLK_CON_DIV_CLKCMU_BUS 0x1800 +#define CLK_CON_DIV_CLKCMU_BUS_DLP 0x1804 +#define CLK_CON_DIV_CLKCMU_CDC_CORE 0x1808 +#define CLK_CON_DIV_CLKCMU_FSYS_SCAN0 0x180c +#define CLK_CON_DIV_CLKCMU_FSYS_SCAN1 0x1810 +#define CLK_CON_DIV_CLKCMU_IMEM_JPEG 0x1814 +#define CLK_CON_DIV_CLKCMU_MIF_SWITCH 0x1818 +#define CLK_CON_DIV_CLKCMU_CORE_DLP 0x181c +#define CLK_CON_DIV_CLKCMU_CORE_MAIN 0x1820 +#define CLK_CON_DIV_CLKCMU_PERI_DISP 0x1824 +#define CLK_CON_DIV_CLKCMU_CPUCL_SWITCH 0x1828 +#define CLK_CON_DIV_CLKCMU_DLP_CORE 0x182c +#define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1830 +#define CLK_CON_DIV_CLKCMU_FSYS_IP 0x1834 +#define CLK_CON_DIV_CLKCMU_VIO_AUDIO 0x1838 +#define CLK_CON_DIV_CLKCMU_GPU_2D 0x1848 +#define CLK_CON_DIV_CLKCMU_GPU_3D 0x184c +#define CLK_CON_DIV_CLKCMU_IMEM_ACLK 0x1854 +#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1884 +#define CLK_CON_DIV_CLKCMU_PERI_AUDIO 0x1890 +#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1894 +#define CLK_CON_DIV_CLKCMU_RSP_CORE 0x1898 +#define CLK_CON_DIV_CLKCMU_TRFM_CORE 0x189c +#define CLK_CON_DIV_CLKCMU_VCA_ACE 0x18a0 +#define CLK_CON_DIV_CLKCMU_VCA_OD 0x18a4 +#define CLK_CON_DIV_CLKCMU_VIO_CORE 0x18ac +#define CLK_CON_DIV_CLKCMU_VIP0_CORE 0x18b0 +#define CLK_CON_DIV_CLKCMU_VIP1_CORE 0x18b4 +#define CLK_CON_DIV_CLKCMU_VPP_CORE 0x18b8 +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18bc +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18c0 +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18c4 +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c8 +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18cc +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18d0 + +static const unsigned long cmu_cmu_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_AUDIO, + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_CON0_PLL_AUDIO, + PLL_CON0_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + CLK_CON_MUX_CLKCMU_2D, + CLK_CON_MUX_CLKCMU_3D, + CLK_CON_MUX_CLKCMU_BUS, + CLK_CON_MUX_CLKCMU_BUS_DLP, + CLK_CON_MUX_CLKCMU_CDC_CORE, + CLK_CON_MUX_CLKCMU_FSYS_SCAN0, + CLK_CON_MUX_CLKCMU_FSYS_SCAN1, + CLK_CON_MUX_CLKCMU_IMEM_JPEG, + CLK_CON_MUX_CLKCMU_PERI_DISP, + CLK_CON_MUX_CLKCMU_CORE_BUS, + CLK_CON_MUX_CLKCMU_CORE_DLP, + CLK_CON_MUX_CLKCMU_CPUCL_SWITCH, + CLK_CON_MUX_CLKCMU_DLP_CORE, + CLK_CON_MUX_CLKCMU_FSYS_BUS, + CLK_CON_MUX_CLKCMU_FSYS_IP, + CLK_CON_MUX_CLKCMU_IMEM_ACLK, + CLK_CON_MUX_CLKCMU_MIF_BUSP, + CLK_CON_MUX_CLKCMU_MIF_SWITCH, + CLK_CON_MUX_CLKCMU_PERI_IP, + CLK_CON_MUX_CLKCMU_RSP_CORE, + CLK_CON_MUX_CLKCMU_TRFM_CORE, + CLK_CON_MUX_CLKCMU_VCA_ACE, + CLK_CON_MUX_CLKCMU_VCA_OD, + CLK_CON_MUX_CLKCMU_VIO_CORE, + CLK_CON_MUX_CLKCMU_VIP0_CORE, + CLK_CON_MUX_CLKCMU_VIP1_CORE, + CLK_CON_MUX_CLKCMU_VPP_CORE, + CLK_CON_DIV_CLKCMU_BUS, + CLK_CON_DIV_CLKCMU_BUS_DLP, + CLK_CON_DIV_CLKCMU_CDC_CORE, + CLK_CON_DIV_CLKCMU_FSYS_SCAN0, + CLK_CON_DIV_CLKCMU_FSYS_SCAN1, + CLK_CON_DIV_CLKCMU_IMEM_JPEG, + CLK_CON_DIV_CLKCMU_MIF_SWITCH, + CLK_CON_DIV_CLKCMU_CORE_DLP, + CLK_CON_DIV_CLKCMU_CORE_MAIN, + CLK_CON_DIV_CLKCMU_PERI_DISP, + CLK_CON_DIV_CLKCMU_CPUCL_SWITCH, + CLK_CON_DIV_CLKCMU_DLP_CORE, + CLK_CON_DIV_CLKCMU_FSYS_BUS, + CLK_CON_DIV_CLKCMU_FSYS_IP, + CLK_CON_DIV_CLKCMU_VIO_AUDIO, + CLK_CON_DIV_CLKCMU_GPU_2D, + CLK_CON_DIV_CLKCMU_GPU_3D, + CLK_CON_DIV_CLKCMU_IMEM_ACLK, + CLK_CON_DIV_CLKCMU_MIF_BUSP, + CLK_CON_DIV_CLKCMU_PERI_AUDIO, + CLK_CON_DIV_CLKCMU_PERI_IP, + CLK_CON_DIV_CLKCMU_RSP_CORE, + CLK_CON_DIV_CLKCMU_TRFM_CORE, + CLK_CON_DIV_CLKCMU_VCA_ACE, + CLK_CON_DIV_CLKCMU_VCA_OD, + CLK_CON_DIV_CLKCMU_VIO_CORE, + CLK_CON_DIV_CLKCMU_VIP0_CORE, + CLK_CON_DIV_CLKCMU_VIP1_CORE, + CLK_CON_DIV_CLKCMU_VPP_CORE, + CLK_CON_DIV_PLL_SHARED0_DIV2, + CLK_CON_DIV_PLL_SHARED0_DIV3, + CLK_CON_DIV_PLL_SHARED0_DIV4, + CLK_CON_DIV_PLL_SHARED1_DIV2, + CLK_CON_DIV_PLL_SHARED1_DIV3, + CLK_CON_DIV_PLL_SHARED1_DIV4, +}; + +static const struct samsung_pll_rate_table artpec8_pll_audio_rates[] __initconst = { + PLL_36XX_RATE(25 * MHZ, 589823913U, 47, 1, 1, 12184), + PLL_36XX_RATE(25 * MHZ, 393215942U, 47, 3, 0, 12184), + PLL_36XX_RATE(25 * MHZ, 294911956U, 47, 1, 2, 12184), + PLL_36XX_RATE(25 * MHZ, 100000000U, 32, 2, 2, 0), + PLL_36XX_RATE(25 * MHZ, 98303985U, 47, 3, 2, 12184), + PLL_36XX_RATE(25 * MHZ, 49151992U, 47, 3, 3, 12184), +}; + +static const struct samsung_pll_clock cmu_cmu_pll_clks[] __initconst = { + PLL(pll_1017x, CLK_FOUT_SHARED0_PLL, "fout_pll_shared0", "fin_pll", + PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL), + PLL(pll_1017x, CLK_FOUT_SHARED1_PLL, "fout_pll_shared1", "fin_pll", + PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, NULL), + PLL(pll_1031x, CLK_FOUT_AUDIO_PLL, "fout_pll_audio", "fin_pll", + PLL_LOCKTIME_PLL_AUDIO, PLL_CON0_PLL_AUDIO, artpec8_pll_audio_rates), +}; + +PNAME(mout_clkcmu_bus_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_bus_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div4", + "dout_pll_shared1_div2", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_core_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared0_div4", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_core_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_cpucl_switch_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_fsys_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2", + "dout_pll_shared1_div4", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_fsys_ip_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3", + "dout_pll_shared1_div2", "dout_pll_shared0_div3" }; +PNAME(mout_clkcmu_fsys_scan0_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_fsys_scan1_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_imem_imem_p) = { "dout_pll_shared1_div4", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div2" }; +PNAME(mout_clkcmu_imem_jpeg_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div2", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_cdc_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_dlp_core_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_3d_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_2d_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_mif_switch_p) = { "dout_pll_shared0", "dout_pll_shared1", + "dout_pll_shared0_div2", "dout_pll_shared0_div3" }; +PNAME(mout_clkcmu_mif_busp_p) = { "dout_pll_shared0_div3", "dout_pll_shared1_div4", + "dout_pll_shared0_div4", "dout_pll_shared0_div2" }; +PNAME(mout_clkcmu_peri_disp_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2", + "dout_pll_shared1_div4", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_peri_ip_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div4", + "dout_pll_shared1_div4", "dout_pll_shared0_div2" }; +PNAME(mout_clkcmu_rsp_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_trfm_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vca_ace_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vca_od_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vio_core_p) = { "dout_pll_shared0_div3", "dout_pll_shared0_div2", + "dout_pll_shared1_div2", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_vip0_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vip1_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vpp_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_pll_shared0_p) = { "fin_pll", "fout_pll_shared0" }; +PNAME(mout_clkcmu_pll_shared1_p) = { "fin_pll", "fout_pll_shared1" }; +PNAME(mout_clkcmu_pll_audio_p) = { "fin_pll", "fout_pll_audio" }; + +static const struct samsung_fixed_factor_clock cmu_fixed_factor_clks[] __initconst = { + FFACTOR(CLK_DOUT_CMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0), +}; + +static const struct samsung_mux_clock cmu_cmu_mux_clks[] __initconst = { + MUX(0, "mout_clkcmu_pll_shared0", mout_clkcmu_pll_shared0_p, PLL_CON0_PLL_SHARED0, 4, 1), + MUX(0, "mout_clkcmu_pll_shared1", mout_clkcmu_pll_shared1_p, PLL_CON0_PLL_SHARED1, 4, 1), + MUX(0, "mout_clkcmu_pll_audio", mout_clkcmu_pll_audio_p, PLL_CON0_PLL_AUDIO, 4, 1), + MUX(0, "mout_clkcmu_bus_bus", mout_clkcmu_bus_bus_p, CLK_CON_MUX_CLKCMU_BUS, 0, 2), + MUX(0, "mout_clkcmu_bus_dlp", mout_clkcmu_bus_dlp_p, CLK_CON_MUX_CLKCMU_BUS_DLP, 0, 2), + MUX(0, "mout_clkcmu_core_bus", mout_clkcmu_core_bus_p, CLK_CON_MUX_CLKCMU_CORE_BUS, 0, 2), + MUX(0, "mout_clkcmu_core_dlp", mout_clkcmu_core_dlp_p, CLK_CON_MUX_CLKCMU_CORE_DLP, 0, 2), + MUX(0, "mout_clkcmu_cpucl_switch", mout_clkcmu_cpucl_switch_p, + CLK_CON_MUX_CLKCMU_CPUCL_SWITCH, 0, 3), + MUX(0, "mout_clkcmu_fsys_bus", mout_clkcmu_fsys_bus_p, CLK_CON_MUX_CLKCMU_FSYS_BUS, 0, 2), + MUX(0, "mout_clkcmu_fsys_ip", mout_clkcmu_fsys_ip_p, CLK_CON_MUX_CLKCMU_FSYS_IP, 0, 2), + MUX(0, "mout_clkcmu_fsys_scan0", mout_clkcmu_fsys_scan0_p, + CLK_CON_MUX_CLKCMU_FSYS_SCAN0, 0, 1), + MUX(0, "mout_clkcmu_fsys_scan1", mout_clkcmu_fsys_scan1_p, + CLK_CON_MUX_CLKCMU_FSYS_SCAN1, 0, 1), + MUX(0, "mout_clkcmu_imem_imem", mout_clkcmu_imem_imem_p, + CLK_CON_MUX_CLKCMU_IMEM_ACLK, 0, 2), + MUX(0, "mout_clkcmu_imem_jpeg", mout_clkcmu_imem_jpeg_p, + CLK_CON_MUX_CLKCMU_IMEM_JPEG, 0, 2), + nMUX(0, "mout_clkcmu_cdc_core", mout_clkcmu_cdc_core_p, CLK_CON_MUX_CLKCMU_CDC_CORE, 0, 2), + nMUX(0, "mout_clkcmu_dlp_core", mout_clkcmu_dlp_core_p, CLK_CON_MUX_CLKCMU_DLP_CORE, 0, 2), + MUX(0, "mout_clkcmu_3d", mout_clkcmu_3d_p, CLK_CON_MUX_CLKCMU_3D, 0, 2), + MUX(0, "mout_clkcmu_2d", mout_clkcmu_2d_p, CLK_CON_MUX_CLKCMU_2D, 0, 2), + MUX(0, "mout_clkcmu_mif_switch", mout_clkcmu_mif_switch_p, + CLK_CON_MUX_CLKCMU_MIF_SWITCH, 0, 2), + MUX(0, "mout_clkcmu_mif_busp", mout_clkcmu_mif_busp_p, CLK_CON_MUX_CLKCMU_MIF_BUSP, 0, 2), + MUX(0, "mout_clkcmu_peri_disp", mout_clkcmu_peri_disp_p, + CLK_CON_MUX_CLKCMU_PERI_DISP, 0, 2), + MUX(0, "mout_clkcmu_peri_ip", mout_clkcmu_peri_ip_p, CLK_CON_MUX_CLKCMU_PERI_IP, 0, 2), + MUX(0, "mout_clkcmu_rsp_core", mout_clkcmu_rsp_core_p, CLK_CON_MUX_CLKCMU_RSP_CORE, 0, 2), + nMUX(0, "mout_clkcmu_trfm_core", mout_clkcmu_trfm_core_p, + CLK_CON_MUX_CLKCMU_TRFM_CORE, 0, 2), + MUX(0, "mout_clkcmu_vca_ace", mout_clkcmu_vca_ace_p, CLK_CON_MUX_CLKCMU_VCA_ACE, 0, 2), + MUX(0, "mout_clkcmu_vca_od", mout_clkcmu_vca_od_p, CLK_CON_MUX_CLKCMU_VCA_OD, 0, 2), + MUX(0, "mout_clkcmu_vio_core", mout_clkcmu_vio_core_p, CLK_CON_MUX_CLKCMU_VIO_CORE, 0, 2), + nMUX(0, "mout_clkcmu_vip0_core", mout_clkcmu_vip0_core_p, + CLK_CON_MUX_CLKCMU_VIP0_CORE, 0, 2), + nMUX(0, "mout_clkcmu_vip1_core", mout_clkcmu_vip1_core_p, + CLK_CON_MUX_CLKCMU_VIP1_CORE, 0, 2), + nMUX(0, "mout_clkcmu_vpp_core", mout_clkcmu_vpp_core_p, CLK_CON_MUX_CLKCMU_VPP_CORE, 0, 2), +}; + +static const struct samsung_div_clock cmu_cmu_div_clks[] __initconst = { + DIV(CLK_DOUT_SHARED0_DIV2, "dout_pll_shared0_div2", + "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_SHARED0_DIV3, "dout_pll_shared0_div3", + "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_SHARED0_DIV4, "dout_pll_shared0_div4", + "dout_pll_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + DIV(CLK_DOUT_SHARED1_DIV2, "dout_pll_shared1_div2", + "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_SHARED1_DIV3, "dout_pll_shared1_div3", + "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_SHARED1_DIV4, "dout_pll_shared1_div4", + "dout_pll_shared1_div2", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), + DIV(CLK_DOUT_CMU_BUS, "dout_clkcmu_bus", + "mout_clkcmu_bus_bus", CLK_CON_DIV_CLKCMU_BUS, 0, 4), + DIV(CLK_DOUT_CMU_BUS_DLP, "dout_clkcmu_bus_dlp", + "mout_clkcmu_bus_dlp", CLK_CON_DIV_CLKCMU_BUS_DLP, 0, 4), + DIV(CLK_DOUT_CMU_CORE_MAIN, "dout_clkcmu_core_main", + "mout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_MAIN, 0, 4), + DIV(CLK_DOUT_CMU_CORE_DLP, "dout_clkcmu_core_dlp", + "mout_clkcmu_core_dlp", CLK_CON_DIV_CLKCMU_CORE_DLP, 0, 4), + DIV(CLK_DOUT_CMU_CPUCL_SWITCH, "dout_clkcmu_cpucl_switch", + "mout_clkcmu_cpucl_switch", CLK_CON_DIV_CLKCMU_CPUCL_SWITCH, 0, 3), + DIV(CLK_DOUT_CMU_FSYS_BUS, "dout_clkcmu_fsys_bus", + "mout_clkcmu_fsys_bus", CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4), + DIV(CLK_DOUT_CMU_FSYS_IP, "dout_clkcmu_fsys_ip", + "mout_clkcmu_fsys_ip", CLK_CON_DIV_CLKCMU_FSYS_IP, 0, 9), + DIV(CLK_DOUT_CMU_FSYS_SCAN0, "dout_clkcmu_fsys_scan0", + "mout_clkcmu_fsys_scan0", CLK_CON_DIV_CLKCMU_FSYS_SCAN0, 0, 4), + DIV(CLK_DOUT_CMU_FSYS_SCAN1, "dout_clkcmu_fsys_scan1", + "mout_clkcmu_fsys_scan1", CLK_CON_DIV_CLKCMU_FSYS_SCAN1, 0, 4), + DIV(CLK_DOUT_CMU_IMEM_ACLK, "dout_clkcmu_imem_aclk", + "mout_clkcmu_imem_imem", CLK_CON_DIV_CLKCMU_IMEM_ACLK, 0, 4), + DIV(CLK_DOUT_CMU_IMEM_JPEG, "dout_clkcmu_imem_jpeg", + "mout_clkcmu_imem_jpeg", CLK_CON_DIV_CLKCMU_IMEM_JPEG, 0, 4), + DIV_F(CLK_DOUT_CMU_CDC_CORE, "dout_clkcmu_cdc_core", + "mout_clkcmu_cdc_core", CLK_CON_DIV_CLKCMU_CDC_CORE, 0, 4, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_CMU_DLP_CORE, "dout_clkcmu_dlp_core", + "mout_clkcmu_dlp_core", CLK_CON_DIV_CLKCMU_DLP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0), + DIV(CLK_DOUT_CMU_GPU_3D, "dout_clkcmu_gpu_3d", + "mout_clkcmu_3d", CLK_CON_DIV_CLKCMU_GPU_3D, 0, 3), + DIV(CLK_DOUT_CMU_GPU_2D, "dout_clkcmu_gpu_2d", + "mout_clkcmu_2d", CLK_CON_DIV_CLKCMU_GPU_2D, 0, 4), + DIV(CLK_DOUT_CMU_MIF_SWITCH, "dout_clkcmu_mif_switch", + "mout_clkcmu_mif_switch", CLK_CON_DIV_CLKCMU_MIF_SWITCH, 0, 4), + DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_clkcmu_mif_busp", + "mout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 3), + DIV(CLK_DOUT_CMU_PERI_DISP, "dout_clkcmu_peri_disp", + "mout_clkcmu_peri_disp", CLK_CON_DIV_CLKCMU_PERI_DISP, 0, 4), + DIV(CLK_DOUT_CMU_PERI_IP, "dout_clkcmu_peri_ip", + "mout_clkcmu_peri_ip", CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), + DIV(CLK_DOUT_CMU_PERI_AUDIO, "dout_clkcmu_peri_audio", + "mout_clkcmu_pll_audio", CLK_CON_DIV_CLKCMU_PERI_AUDIO, 0, 4), + DIV(CLK_DOUT_CMU_RSP_CORE, "dout_clkcmu_rsp_core", + "mout_clkcmu_rsp_core", CLK_CON_DIV_CLKCMU_RSP_CORE, 0, 4), + DIV_F(CLK_DOUT_CMU_TRFM_CORE, "dout_clkcmu_trfm_core", + "mout_clkcmu_trfm_core", CLK_CON_DIV_CLKCMU_TRFM_CORE, 0, 4, CLK_SET_RATE_PARENT, 0), + DIV(CLK_DOUT_CMU_VCA_ACE, "dout_clkcmu_vca_ace", + "mout_clkcmu_vca_ace", CLK_CON_DIV_CLKCMU_VCA_ACE, 0, 4), + DIV(CLK_DOUT_CMU_VCA_OD, "dout_clkcmu_vca_od", + "mout_clkcmu_vca_od", CLK_CON_DIV_CLKCMU_VCA_OD, 0, 4), + DIV(CLK_DOUT_CMU_VIO_CORE, "dout_clkcmu_vio_core", + "mout_clkcmu_vio_core", CLK_CON_DIV_CLKCMU_VIO_CORE, 0, 4), + DIV(CLK_DOUT_CMU_VIO_AUDIO, "dout_clkcmu_vio_audio", + "mout_clkcmu_pll_audio", CLK_CON_DIV_CLKCMU_VIO_AUDIO, 0, 4), + DIV_F(CLK_DOUT_CMU_VIP0_CORE, "dout_clkcmu_vip0_core", + "mout_clkcmu_vip0_core", CLK_CON_DIV_CLKCMU_VIP0_CORE, 0, 4, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_CMU_VIP1_CORE, "dout_clkcmu_vip1_core", + "mout_clkcmu_vip1_core", CLK_CON_DIV_CLKCMU_VIP1_CORE, 0, 4, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_CMU_VPP_CORE, "dout_clkcmu_vpp_core", + "mout_clkcmu_vpp_core", CLK_CON_DIV_CLKCMU_VPP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info cmu_cmu_info __initconst = { + .pll_clks = cmu_cmu_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cmu_cmu_pll_clks), + .fixed_factor_clks = cmu_fixed_factor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(cmu_fixed_factor_clks), + .mux_clks = cmu_cmu_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_cmu_mux_clks), + .div_clks = cmu_cmu_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_cmu_div_clks), + .nr_clk_ids = CMU_CMU_NR_CLK, + .clk_regs = cmu_cmu_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_cmu_clk_regs), +}; + +/* Register Offset definitions for CMU_BUS (0x12c10000) */ +#define PLL_CON0_MUX_CLK_BUS_ACLK_USER 0x0100 +#define PLL_CON0_MUX_CLK_BUS_DLP_USER 0x0120 +#define CLK_CON_DIV_CLK_BUS_PCLK 0x1800 + +static const unsigned long cmu_bus_clk_regs[] __initconst = { + PLL_CON0_MUX_CLK_BUS_ACLK_USER, + PLL_CON0_MUX_CLK_BUS_DLP_USER, + CLK_CON_DIV_CLK_BUS_PCLK, +}; + +PNAME(mout_clk_bus_aclk_user_p) = { "fin_pll", "dout_clkcmu_bus" }; +PNAME(mout_clk_bus_dlp_user_p) = { "fin_pll", "dout_clkcmu_bus_dlp" }; + +static const struct samsung_mux_clock cmu_bus_mux_clks[] __initconst = { + MUX(CLK_MOUT_BUS_ACLK_USER, "mout_clk_bus_aclk_user", + mout_clk_bus_aclk_user_p, PLL_CON0_MUX_CLK_BUS_ACLK_USER, 4, 1), + MUX(CLK_MOUT_BUS_DLP_USER, "mout_clk_bus_dlp_user", + mout_clk_bus_dlp_user_p, PLL_CON0_MUX_CLK_BUS_DLP_USER, 4, 1), +}; + +static const struct samsung_div_clock cmu_bus_div_clks[] __initconst = { + DIV(CLK_DOUT_BUS_PCLK, "dout_clk_bus_pclk", "mout_clk_bus_aclk_user", + CLK_CON_DIV_CLK_BUS_PCLK, 0, 4), +}; + +static const struct samsung_cmu_info cmu_bus_info __initconst = { + .mux_clks = cmu_bus_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_bus_mux_clks), + .div_clks = cmu_bus_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_bus_div_clks), + .nr_clk_ids = CMU_BUS_NR_CLK, + .clk_regs = cmu_bus_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_bus_clk_regs), +}; + +/* Register Offset definitions for CMU_CORE (0x12410000) */ +#define PLL_CON0_MUX_CLK_CORE_ACLK_USER 0x0100 +#define PLL_CON0_MUX_CLK_CORE_DLP_USER 0x0120 +#define CLK_CON_DIV_CLK_CORE_PCLK 0x1800 + +static const unsigned long cmu_core_clk_regs[] __initconst = { + PLL_CON0_MUX_CLK_CORE_ACLK_USER, + PLL_CON0_MUX_CLK_CORE_DLP_USER, + CLK_CON_DIV_CLK_CORE_PCLK, +}; + +PNAME(mout_clk_core_aclk_user_p) = { "fin_pll", "dout_clkcmu_core_main" }; +PNAME(mout_clk_core_dlp_user_p) = { "fin_pll", "dout_clkcmu_core_dlp" }; + +static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst = { + MUX(CLK_MOUT_CORE_ACLK_USER, "mout_clk_core_aclk_user", + mout_clk_core_aclk_user_p, PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1), + MUX(CLK_MOUT_CORE_DLP_USER, "mout_clk_core_dlp_user", + mout_clk_core_dlp_user_p, PLL_CON0_MUX_CLK_CORE_DLP_USER, 4, 1), +}; + +static const struct samsung_div_clock cmu_core_div_clks[] __initconst = { + DIV(CLK_DOUT_CORE_PCLK, "dout_clk_core_pclk", + "mout_clk_core_aclk_user", CLK_CON_DIV_CLK_CORE_PCLK, 0, 4), +}; + +static const struct samsung_cmu_info cmu_core_info __initconst = { + .mux_clks = cmu_core_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_core_mux_clks), + .div_clks = cmu_core_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_core_div_clks), + .nr_clk_ids = CMU_CORE_NR_CLK, + .clk_regs = cmu_core_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_core_clk_regs), +}; + +/* Register Offset definitions for CMU_CPUCL (0x11410000) */ +#define PLL_LOCKTIME_PLL_CPUCL 0x0000 +#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER 0x0120 +#define PLL_CON0_PLL_CPUCL 0x0140 +#define CLK_CON_MUX_CLK_CPUCL_PLL 0x1000 +#define CLK_CON_DIV_CLK_CLUSTER_ACLK 0x1800 +#define CLK_CON_DIV_CLK_CLUSTER_CNTCLK 0x1804 +#define CLK_CON_DIV_CLK_CLUSTER_PCLKDBG 0x1808 +#define CLK_CON_DIV_CLK_CPUCL_CMUREF 0x180c +#define CLK_CON_DIV_CLK_CPUCL_PCLK 0x1814 +#define CLK_CON_DIV_CLK_CLUSTER_ATCLK 0x1818 +#define CLK_CON_DIV_CLK_CPUCL_DBG 0x181c +#define CLK_CON_DIV_CLK_CPUCL_PCLKDBG 0x1820 +#define CLK_CON_GAT_CLK_CLUSTER_CPU 0x2008 +#define CLK_CON_GAT_CLK_CPUCL_SHORTSTOP 0x200c +#define CLK_CON_DMYQCH_CON_CSSYS_QCH 0x3008 + +static const unsigned long cmu_cpucl_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_CPUCL, + PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, + PLL_CON0_PLL_CPUCL, + CLK_CON_MUX_CLK_CPUCL_PLL, + CLK_CON_DIV_CLK_CLUSTER_ACLK, + CLK_CON_DIV_CLK_CLUSTER_CNTCLK, + CLK_CON_DIV_CLK_CLUSTER_PCLKDBG, + CLK_CON_DIV_CLK_CPUCL_CMUREF, + CLK_CON_DIV_CLK_CPUCL_PCLK, + CLK_CON_DIV_CLK_CLUSTER_ATCLK, + CLK_CON_DIV_CLK_CPUCL_DBG, + CLK_CON_DIV_CLK_CPUCL_PCLKDBG, + CLK_CON_GAT_CLK_CLUSTER_CPU, + CLK_CON_GAT_CLK_CPUCL_SHORTSTOP, + CLK_CON_DMYQCH_CON_CSSYS_QCH, +}; + +static const struct samsung_pll_clock cmu_cpucl_pll_clks[] __initconst = { + PLL(pll_1017x, CLK_FOUT_CPUCL_PLL, "fout_pll_cpucl", "fin_pll", + PLL_LOCKTIME_PLL_CPUCL, PLL_CON0_PLL_CPUCL, NULL), +}; + +PNAME(mout_clkcmu_cpucl_switch_user_p) = { "fin_pll", "dout_clkcmu_cpucl_switch" }; +PNAME(mout_pll_cpucl_p) = { "fin_pll", "fout_pll_cpucl" }; +PNAME(mout_clk_cpucl_pll_p) = { "mout_pll_cpucl", "mout_clkcmu_cpucl_switch_user" }; + +static const struct samsung_mux_clock cmu_cpucl_mux_clks[] __initconst = { + MUX_F(0, "mout_pll_cpucl", mout_pll_cpucl_p, PLL_CON0_PLL_CPUCL, 4, 1, + CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), + MUX(CLK_MOUT_CPUCL_SWITCH_USER, "mout_clkcmu_cpucl_switch_user", + mout_clkcmu_cpucl_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, 4, 1), + MUX_F(CLK_MOUT_CPUCL_PLL, "mout_clk_cpucl_pll", mout_clk_cpucl_pll_p, + CLK_CON_MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_fixed_factor_clock cpucl_ffactor_clks[] __initconst = { + FFACTOR(CLK_DOUT_CPUCL_CPU, "dout_clk_cpucl_cpu", + "mout_clk_cpucl_pll", 1, 1, CLK_SET_RATE_PARENT), +}; + +static const struct samsung_div_clock cmu_cpucl_div_clks[] __initconst = { + DIV(CLK_DOUT_CPUCL_CLUSTER_ACLK, "dout_clk_cluster_aclk", + "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_ACLK, 0, 4), + DIV(CLK_DOUT_CPUCL_CLUSTER_PCLKDBG, "dout_clk_cluster_pclkdbg", + "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_PCLKDBG, 0, 4), + DIV(CLK_DOUT_CPUCL_CLUSTER_CNTCLK, "dout_clk_cluster_cntclk", + "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_CNTCLK, 0, 4), + DIV(CLK_DOUT_CPUCL_CLUSTER_ATCLK, "dout_clk_cluster_atclk", + "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_ATCLK, 0, 4), + DIV(CLK_DOUT_CPUCL_PCLK, "dout_clk_cpucl_pclk", + "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_PCLK, 0, 4), + DIV(CLK_DOUT_CPUCL_CMUREF, "dout_clk_cpucl_cmuref", + "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_CMUREF, 0, 3), + DIV(CLK_DOUT_CPUCL_DBG, "dout_clk_cpucl_dbg", + "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_DBG, 0, 4), + DIV(CLK_DOUT_CPUCL_PCLKDBG, "dout_clk_cpucl_pclkdbg", + "dout_clk_cpucl_dbg", CLK_CON_DIV_CLK_CPUCL_PCLKDBG, 0, 4), +}; + +static const struct samsung_gate_clock cmu_cpucl_gate_clks[] __initconst = { + GATE(CLK_GOUT_CPUCL_CLUSTER_CPU, "clk_con_gat_clk_cluster_cpu", + "clk_con_gat_clk_cpucl_shortstop", CLK_CON_GAT_CLK_CLUSTER_CPU, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_CPUCL_SHORTSTOP, "clk_con_gat_clk_cpucl_shortstop", + "dout_clk_cpucl_cpu", CLK_CON_GAT_CLK_CPUCL_SHORTSTOP, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG, "cssys_ipclkport_pclkdbg", + "dout_clk_cpucl_pclkdbg", CLK_CON_DMYQCH_CON_CSSYS_QCH, 1, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK, "cssys_ipclkport_atclk", + "dout_clk_cpucl_dbg", CLK_CON_DMYQCH_CON_CSSYS_QCH, 1, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), +}; + +static const struct samsung_cmu_info cmu_cpucl_info __initconst = { + .pll_clks = cmu_cpucl_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cmu_cpucl_pll_clks), + .fixed_factor_clks = cpucl_ffactor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(cpucl_ffactor_clks), + .mux_clks = cmu_cpucl_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_cpucl_mux_clks), + .div_clks = cmu_cpucl_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_cpucl_div_clks), + .gate_clks = cmu_cpucl_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cmu_cpucl_gate_clks), + .nr_clk_ids = CMU_CPUCL_NR_CLK, + .clk_regs = cmu_cpucl_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_cpucl_clk_regs), +}; + +/* Register Offset definitions for CMU_FSYS (0x16c10000) */ +#define PLL_LOCKTIME_PLL_FSYS 0x0004 +#define PLL_CON0_MUX_CLK_FSYS_BUS_USER 0x0120 +#define PLL_CON0_MUX_CLK_FSYS_MMC_USER 0x0140 +#define PLL_CON0_MUX_CLK_FSYS_SCAN0_USER 0x0160 +#define PLL_CON0_MUX_CLK_FSYS_SCAN1_USER 0x0180 +#define PLL_CON0_PLL_FSYS 0x01c0 +#define CLK_CON_DIV_CLK_FSYS_ADC 0x1804 +#define CLK_CON_DIV_CLK_FSYS_BUS300 0x1808 +#define CLK_CON_DIV_CLK_FSYS_BUS_QSPI 0x180c +#define CLK_CON_DIV_CLK_FSYS_EQOS_25 0x1810 +#define CLK_CON_DIV_CLK_FSYS_EQOS_2P5 0x1814 +#define CLK_CON_DIV_CLK_FSYS_EQOS_500 0x1818 +#define CLK_CON_DIV_CLK_FSYS_EQOS_INT125 0x181c +#define CLK_CON_DIV_CLK_FSYS_MMC_CARD0 0x1820 +#define CLK_CON_DIV_CLK_FSYS_MMC_CARD1 0x1824 +#define CLK_CON_DIV_CLK_FSYS_OTP_MEM 0x1828 +#define CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL 0x182c +#define CLK_CON_DIV_CLK_FSYS_QSPI 0x1830 +#define CLK_CON_DIV_CLK_FSYS_SCLK_UART 0x1834 +#define CLK_CON_DIV_CLK_FSYS_SFMC_NAND 0x1838 +#define CLK_CON_DIV_SCAN_CLK_FSYS_125 0x183c +#define CLK_CON_DIV_SCAN_CLK_FSYS_MMC 0x1840 +#define CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE 0x1844 +#define CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK 0x2044 +#define CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK 0x2048 +#define CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK 0x204c +#define CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART 0x2050 +#define CLK_CON_MMC0_IPCLKPORT_I_ACLK 0x2070 +#define CLK_CON_MMC1_IPCLKPORT_I_ACLK 0x2078 +#define CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x208c +#define CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2090 +#define CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2094 +#define CLK_CON_PWM_IPCLKPORT_I_PCLK_S0 0x20a0 +#define CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 0x20bc +#define CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 0x20c0 +#define CLK_CON_XHB_AHBBR_IPCLKPORT_CLK 0x20c4 +#define CLK_CON_XHB_USB_IPCLKPORT_CLK 0x20cc +#define CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK 0x201c +#define CLK_CON_DMYQCH_CON_EQOS_TOP_QCH 0x3008 +#define CLK_CON_DMYQCH_CON_MMC0_QCH 0x300c +#define CLK_CON_DMYQCH_CON_MMC1_QCH 0x3010 +#define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH 0x3018 +#define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF 0x301c +#define CLK_CON_DMYQCH_CON_QSPI_QCH 0x3020 +#define CLK_CON_DMYQCH_CON_SFMC_QCH 0x3024 + +static const unsigned long cmu_fsys_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_FSYS, + PLL_CON0_MUX_CLK_FSYS_BUS_USER, + PLL_CON0_MUX_CLK_FSYS_MMC_USER, + PLL_CON0_MUX_CLK_FSYS_SCAN0_USER, + PLL_CON0_MUX_CLK_FSYS_SCAN1_USER, + PLL_CON0_PLL_FSYS, + CLK_CON_DIV_CLK_FSYS_ADC, + CLK_CON_DIV_CLK_FSYS_BUS300, + CLK_CON_DIV_CLK_FSYS_BUS_QSPI, + CLK_CON_DIV_CLK_FSYS_EQOS_25, + CLK_CON_DIV_CLK_FSYS_EQOS_2P5, + CLK_CON_DIV_CLK_FSYS_EQOS_500, + CLK_CON_DIV_CLK_FSYS_EQOS_INT125, + CLK_CON_DIV_CLK_FSYS_MMC_CARD0, + CLK_CON_DIV_CLK_FSYS_MMC_CARD1, + CLK_CON_DIV_CLK_FSYS_OTP_MEM, + CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, + CLK_CON_DIV_CLK_FSYS_QSPI, + CLK_CON_DIV_CLK_FSYS_SCLK_UART, + CLK_CON_DIV_CLK_FSYS_SFMC_NAND, + CLK_CON_DIV_SCAN_CLK_FSYS_125, + CLK_CON_DIV_SCAN_CLK_FSYS_MMC, + CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE, + CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK, + CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK, + CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK, + CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART, + CLK_CON_MMC0_IPCLKPORT_I_ACLK, + CLK_CON_MMC1_IPCLKPORT_I_ACLK, + CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + CLK_CON_PWM_IPCLKPORT_I_PCLK_S0, + CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, + CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, + CLK_CON_XHB_AHBBR_IPCLKPORT_CLK, + CLK_CON_XHB_USB_IPCLKPORT_CLK, + CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK, + CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, + CLK_CON_DMYQCH_CON_MMC0_QCH, + CLK_CON_DMYQCH_CON_MMC1_QCH, + CLK_CON_DMYQCH_CON_PCIE_TOP_QCH, + CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF, + CLK_CON_DMYQCH_CON_QSPI_QCH, + CLK_CON_DMYQCH_CON_SFMC_QCH, +}; + +static const struct samsung_pll_clock cmu_fsys_pll_clks[] __initconst = { + PLL(pll_1017x, CLK_FOUT_FSYS_PLL, "fout_pll_fsys", "fin_pll", + PLL_LOCKTIME_PLL_FSYS, PLL_CON0_PLL_FSYS, NULL), +}; + +PNAME(mout_fsys_scan0_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan0" }; +PNAME(mout_fsys_scan1_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan1" }; +PNAME(mout_fsys_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys_bus" }; +PNAME(mout_fsys_mmc_user_p) = { "fin_pll", "dout_clkcmu_fsys_ip" }; +PNAME(mout_fsys_pll_fsys_p) = { "fin_pll", "fout_pll_fsys" }; + +static const struct samsung_mux_clock cmu_fsys_mux_clks[] __initconst = { + MUX(0, "mout_clk_pll_fsys", mout_fsys_pll_fsys_p, PLL_CON0_PLL_FSYS, 4, 1), + MUX(CLK_MOUT_FSYS_SCAN0_USER, "mout_fsys_scan0_user", + mout_fsys_scan0_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN0_USER, 4, 1), + MUX(CLK_MOUT_FSYS_SCAN1_USER, "mout_fsys_scan1_user", + mout_fsys_scan1_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN1_USER, 4, 1), + MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", + mout_fsys_bus_user_p, PLL_CON0_MUX_CLK_FSYS_BUS_USER, 4, 1), + MUX(CLK_MOUT_FSYS_MMC_USER, "mout_fsys_mmc_user", + mout_fsys_mmc_user_p, PLL_CON0_MUX_CLK_FSYS_MMC_USER, 4, 1), +}; + +static const struct samsung_div_clock cmu_fsys_div_clks[] __initconst = { + DIV(CLK_DOUT_FSYS_PCIE_PIPE, "dout_fsys_pcie_pipe", "mout_clk_pll_fsys", + CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE, 0, 4), + DIV(CLK_DOUT_FSYS_ADC, "dout_fsys_adc", "mout_clk_pll_fsys", + CLK_CON_DIV_CLK_FSYS_ADC, 0, 7), + DIV(CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL, "dout_fsys_pcie_phy_refclk_syspll", + "mout_clk_pll_fsys", CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, 0, 8), + DIV(CLK_DOUT_FSYS_QSPI, "dout_fsys_qspi", "mout_fsys_mmc_user", + CLK_CON_DIV_CLK_FSYS_QSPI, 0, 4), + DIV(CLK_DOUT_FSYS_EQOS_INT125, "dout_fsys_eqos_int125", "mout_clk_pll_fsys", + CLK_CON_DIV_CLK_FSYS_EQOS_INT125, 0, 4), + DIV(CLK_DOUT_FSYS_OTP_MEM, "dout_fsys_otp_mem", "fin_pll", + CLK_CON_DIV_CLK_FSYS_OTP_MEM, 0, 9), + DIV(CLK_DOUT_FSYS_SCLK_UART, "dout_fsys_sclk_uart", "mout_clk_pll_fsys", + CLK_CON_DIV_CLK_FSYS_SCLK_UART, 0, 10), + DIV(CLK_DOUT_FSYS_SFMC_NAND, "dout_fsys_sfmc_nand", "mout_fsys_mmc_user", + CLK_CON_DIV_CLK_FSYS_SFMC_NAND, 0, 4), + DIV(CLK_DOUT_SCAN_CLK_FSYS_125, "dout_scan_clk_fsys_125", "mout_clk_pll_fsys", + CLK_CON_DIV_SCAN_CLK_FSYS_125, 0, 4), + DIV(CLK_DOUT_FSYS_SCAN_CLK_MMC, "dout_scan_clk_fsys_mmc", "fout_pll_fsys", + CLK_CON_DIV_SCAN_CLK_FSYS_MMC, 0, 4), + DIV(CLK_DOUT_FSYS_EQOS_25, "dout_fsys_eqos_25", "dout_fsys_eqos_int125", + CLK_CON_DIV_CLK_FSYS_EQOS_25, 0, 4), + DIV_F(CLK_DOUT_FSYS_EQOS_2p5, "dout_fsys_eqos_2p5", "dout_fsys_eqos_25", + CLK_CON_DIV_CLK_FSYS_EQOS_2P5, 0, 4, CLK_SET_RATE_PARENT, 0), + DIV(0, "dout_fsys_eqos_500", "mout_clk_pll_fsys", + CLK_CON_DIV_CLK_FSYS_EQOS_500, 0, 4), + DIV(CLK_DOUT_FSYS_BUS300, "dout_fsys_bus300", "mout_fsys_bus_user", + CLK_CON_DIV_CLK_FSYS_BUS300, 0, 4), + DIV(CLK_DOUT_FSYS_BUS_QSPI, "dout_fsys_bus_qspi", "mout_fsys_mmc_user", + CLK_CON_DIV_CLK_FSYS_BUS_QSPI, 0, 4), + DIV(CLK_DOUT_FSYS_MMC_CARD0, "dout_fsys_mmc_card0", "mout_fsys_mmc_user", + CLK_CON_DIV_CLK_FSYS_MMC_CARD0, 0, 10), + DIV(CLK_DOUT_FSYS_MMC_CARD1, "dout_fsys_mmc_card1", "mout_fsys_mmc_user", + CLK_CON_DIV_CLK_FSYS_MMC_CARD1, 0, 10), +}; + +static const struct samsung_gate_clock cmu_fsys_gate_clks[] __initconst = { + GATE(CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN, "pcie_sub_ctrl_inst_0_phy_refclk_in", + "dout_fsys_pcie_phy_refclk_syspll", CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF, 1, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5, + "eqos_top_ipclkport_i_rgmii_txclk_2p5", + "dout_fsys_eqos_2p5", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I, "eqos_top_ipclkport_aclk_i", + "dout_fsys_bus300", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I, "eqos_top_ipclkport_clk_csr_i", + "dout_fsys_bus300", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK, "pipe_pal_inst_0_i_apb_pclk", + "dout_fsys_bus300", CLK_CON_DMYQCH_CON_PCIE_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK, "qspi_ipclkport_hclk", + "dout_fsys_bus_qspi", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK, "qspi_ipclkport_ssi_clk", + "dout_fsys_qspi", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN, "mmc0_ipclkport_sdclkin", + "dout_fsys_mmc_card0", CLK_CON_DMYQCH_CON_MMC0_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN, "mmc1_ipclkport_sdclkin", + "dout_fsys_mmc_card1", CLK_CON_DMYQCH_CON_MMC1_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND, "sfmc_ipclkport_i_aclk_nand", + "dout_fsys_sfmc_nand", CLK_CON_DMYQCH_CON_SFMC_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_UART0_SCLK_UART, "uart0_sclk", "dout_fsys_sclk_uart", + CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, "dwc_pcie_ctl_inst_0_mstr_aclk_ug", + "mout_fsys_bus_user", CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG, "dwc_pcie_ctl_inst_0_slv_aclk_ug", + "mout_fsys_bus_user", CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK, "fsys_i2c0_ipclkport_i_pclk", "dout_fsys_bus300", + CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK, "fsys_i2c1_ipclkport_i_pclk", "dout_fsys_bus300", + CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_UART0_PCLK, "uart0_pclk", "dout_fsys_bus300", + CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK, "mmc0_ipclkport_i_aclk", "dout_fsys_bus300", + CLK_CON_MMC0_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK, "mmc1_ipclkport_i_aclk", "dout_fsys_bus300", + CLK_CON_MMC1_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, "dwc_pcie_ctl_inst_0_dbi_aclk_ug", + "dout_fsys_bus300", CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0, "pwm_ipclkport_i_pclk_s0", "dout_fsys_bus300", + CLK_CON_PWM_IPCLKPORT_I_PCLK_S0, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, "usb20drd_ipclkport_aclk_phyctrl_20", + "dout_fsys_bus300", CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, "usb20drd_ipclkport_bus_clk_early", + "dout_fsys_bus300", CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK, "xhb_ahbbr_ipclkport_clk", "dout_fsys_bus300", + CLK_CON_XHB_AHBBR_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK, "xhb_usb_ipclkport_clk", "dout_fsys_bus300", + CLK_CON_XHB_USB_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_FSYS_BUS_QSPI, "bus_p_fsys_ipclkport_qspiclk", "dout_fsys_bus_qspi", + CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), +}; + +static const struct samsung_cmu_info cmu_fsys_info __initconst = { + .pll_clks = cmu_fsys_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cmu_fsys_pll_clks), + .mux_clks = cmu_fsys_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_fsys_mux_clks), + .div_clks = cmu_fsys_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_fsys_div_clks), + .gate_clks = cmu_fsys_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cmu_fsys_gate_clks), + .nr_clk_ids = CMU_FSYS_NR_CLK, + .clk_regs = cmu_fsys_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_fsys_clk_regs), +}; + +/* Register Offset definitions for CMU_IMEM (0x10010000) */ +#define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 +#define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 +#define CLK_CON_MUX_CLK_IMEM_GIC_CA53 0x1000 +#define CLK_CON_MUX_CLK_IMEM_GIC_CA5 0x1008 +#define CLK_CON_MCT_IPCLKPORT_PCLK 0x2038 +#define CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK 0x2044 + +static const unsigned long cmu_imem_clk_regs[] __initconst = { + PLL_CON0_MUX_CLK_IMEM_ACLK_USER, + PLL_CON0_MUX_CLK_IMEM_JPEG_USER, + CLK_CON_MUX_CLK_IMEM_GIC_CA53, + CLK_CON_MUX_CLK_IMEM_GIC_CA5, + CLK_CON_MCT_IPCLKPORT_PCLK, + CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK, +}; + +PNAME(mout_imem_aclk_user_p) = { "fin_pll", "dout_clkcmu_imem_aclk" }; +PNAME(mout_imem_gic_ca53_p) = { "mout_imem_aclk_user", "fin_pll" }; +PNAME(mout_imem_gic_ca5_p) = { "mout_imem_aclk_user", "fin_pll" }; +PNAME(mout_imem_jpeg_user_p) = { "fin_pll", "dout_clkcmu_imem_jpeg" }; + +static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst = { + MUX(CLK_MOUT_IMEM_ACLK_USER, "mout_imem_aclk_user", + mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1), + MUX(CLK_MOUT_IMEM_GIC_CA53, "mout_imem_gic_ca53", + mout_imem_gic_ca53_p, CLK_CON_MUX_CLK_IMEM_GIC_CA53, 0, 1), + MUX(CLK_MOUT_IMEM_GIC_CA5, "mout_imem_gic_ca5", + mout_imem_gic_ca5_p, CLK_CON_MUX_CLK_IMEM_GIC_CA5, 0, 1), + MUX(CLK_MOUT_IMEM_JPEG_USER, "mout_imem_jpeg_user", + mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1), +}; + +static const struct samsung_gate_clock cmu_imem_gate_clks[] __initconst = { + GATE(CLK_GOUT_IMEM_MCT_PCLK, "mct_pclk", "mout_imem_aclk_user", + CLK_CON_MCT_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_IMEM_PCLK_TMU0_APBIF, "sfrif_tmu_imem_ipclkport_pclk", "mout_imem_aclk_user", + CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), +}; + +static const struct samsung_cmu_info cmu_imem_info __initconst = { + .mux_clks = cmu_imem_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_imem_mux_clks), + .gate_clks = cmu_imem_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cmu_imem_gate_clks), + .nr_clk_ids = CMU_IMEM_NR_CLK, + .clk_regs = cmu_imem_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_imem_clk_regs), +}; + +static void __init artpec8_clk_cmu_imem_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_imem_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init); + +/* Register Offset definitions for CMU_PERI (0x16410000) */ +#define PLL_CON0_MUX_CLK_PERI_AUDIO_USER 0x0100 +#define PLL_CON0_MUX_CLK_PERI_DISP_USER 0x0120 +#define PLL_CON0_MUX_CLK_PERI_IP_USER 0x0140 +#define CLK_CON_MUX_CLK_PERI_I2S0 0x1000 +#define CLK_CON_MUX_CLK_PERI_I2S1 0x1004 +#define CLK_CON_DIV_CLK_PERI_DSIM 0x1800 +#define CLK_CON_DIV_CLK_PERI_I2S0 0x1804 +#define CLK_CON_DIV_CLK_PERI_I2S1 0x1808 +#define CLK_CON_DIV_CLK_PERI_PCLK 0x180c +#define CLK_CON_DIV_CLK_PERI_SPI 0x1810 +#define CLK_CON_DIV_CLK_PERI_UART1 0x1814 +#define CLK_CON_DIV_CLK_PERI_UART2 0x1818 +#define CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 0x2004 +#define CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK 0x2030 +#define CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK 0x2034 +#define CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK 0x2048 +#define CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI 0x204c +#define CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK 0x2050 +#define CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART 0x2054 +#define CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK 0x2058 +#define CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART 0x205c +#define CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH 0x3000 +#define CLK_CON_DMYQCH_CON_DMA4DSIM_QCH 0x3004 +#define CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH 0x3008 +#define CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH 0x300c + +static const unsigned long cmu_peri_clk_regs[] __initconst = { + PLL_CON0_MUX_CLK_PERI_AUDIO_USER, + PLL_CON0_MUX_CLK_PERI_DISP_USER, + PLL_CON0_MUX_CLK_PERI_IP_USER, + CLK_CON_MUX_CLK_PERI_I2S0, + CLK_CON_MUX_CLK_PERI_I2S1, + CLK_CON_DIV_CLK_PERI_DSIM, + CLK_CON_DIV_CLK_PERI_I2S0, + CLK_CON_DIV_CLK_PERI_I2S1, + CLK_CON_DIV_CLK_PERI_PCLK, + CLK_CON_DIV_CLK_PERI_SPI, + CLK_CON_DIV_CLK_PERI_UART1, + CLK_CON_DIV_CLK_PERI_UART2, + CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, + CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK, + CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK, + CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK, + CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI, + CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK, + CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART, + CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK, + CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART, + CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH, + CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, + CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, + CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, +}; + +static const struct samsung_fixed_rate_clock peri_fixed_clks[] __initconst = { + FRATE(0, "clk_peri_audio", NULL, 0, 100000000), +}; + +PNAME(mout_peri_ip_user_p) = { "fin_pll", "dout_clkcmu_peri_ip" }; +PNAME(mout_peri_audio_user_p) = { "fin_pll", "dout_clkcmu_peri_audio" }; +PNAME(mout_peri_disp_user_p) = { "fin_pll", "dout_clkcmu_peri_disp" }; +PNAME(mout_peri_i2s0_p) = { "dout_peri_i2s0", "clk_peri_audio" }; +PNAME(mout_peri_i2s1_p) = { "dout_peri_i2s1", "clk_peri_audio" }; + +static const struct samsung_mux_clock cmu_peri_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERI_IP_USER, "mout_peri_ip_user", mout_peri_ip_user_p, + PLL_CON0_MUX_CLK_PERI_IP_USER, 4, 1), + MUX(CLK_MOUT_PERI_AUDIO_USER, "mout_peri_audio_user", + mout_peri_audio_user_p, PLL_CON0_MUX_CLK_PERI_AUDIO_USER, 4, 1), + MUX(CLK_MOUT_PERI_DISP_USER, "mout_peri_disp_user", mout_peri_disp_user_p, + PLL_CON0_MUX_CLK_PERI_DISP_USER, 4, 1), + MUX(CLK_MOUT_PERI_I2S0, "mout_peri_i2s0", mout_peri_i2s0_p, + CLK_CON_MUX_CLK_PERI_I2S0, 0, 1), + MUX(CLK_MOUT_PERI_I2S1, "mout_peri_i2s1", mout_peri_i2s1_p, + CLK_CON_MUX_CLK_PERI_I2S1, 0, 1), +}; + +static const struct samsung_div_clock cmu_peri_div_clks[] __initconst = { + DIV(CLK_DOUT_PERI_SPI, "dout_peri_spi", "mout_peri_ip_user", + CLK_CON_DIV_CLK_PERI_SPI, 0, 10), + DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "mout_peri_ip_user", + CLK_CON_DIV_CLK_PERI_UART1, 0, 10), + DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "mout_peri_ip_user", + CLK_CON_DIV_CLK_PERI_UART2, 0, 10), + DIV(CLK_DOUT_PERI_PCLK, "dout_peri_pclk", "mout_peri_ip_user", + CLK_CON_DIV_CLK_PERI_PCLK, 0, 4), + DIV(CLK_DOUT_PERI_I2S0, "dout_peri_i2s0", "mout_peri_audio_user", + CLK_CON_DIV_CLK_PERI_I2S0, 0, 4), + DIV(CLK_DOUT_PERI_I2S1, "dout_peri_i2s1", "mout_peri_audio_user", + CLK_CON_DIV_CLK_PERI_I2S1, 0, 4), + DIV(CLK_DOUT_PERI_DSIM, "dout_peri_dsim", "mout_peri_disp_user", + CLK_CON_DIV_CLK_PERI_DSIM, 0, 4), +}; + +static const struct samsung_gate_clock cmu_peri_gate_clks[] __initconst = { + GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK, "dma4dsim_ipclkport_clk_apb_clk", + "dout_peri_pclk", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST, "i2ssc0_ipclkport_clk_hst", "dout_peri_pclk", + CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST, "i2ssc1_ipclkport_clk_hst", "dout_peri_pclk", + CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK, "audio_out_ipclkport_clk", + "mout_peri_audio_user", CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK, "peri_i2ssc0_ipclkport_clk", "mout_peri_i2s0", + CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK, "peri_i2ssc1_ipclkport_clk", "mout_peri_i2s1", + CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK, "dma4dsim_ipclkport_clk_axi_clk", + "mout_peri_disp_user", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI0_SCLK_SPI, "peri_spi0_ipclkport_i_sclk_spi", "dout_peri_spi", + CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERI_UART1_SCLK_UART, "uart1_sclk", "dout_peri_uart1", + CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERI_UART2_SCLK_UART, "uart2_sclk", "dout_peri_uart2", + CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, "apb_async_dsim_ipclkport_pclks", + "dout_peri_pclk", CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, 21, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK, "peri_i2c2_ipclkport_i_pclk", "dout_peri_pclk", + CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK, "peri_i2c3_ipclkport_i_pclk", "dout_peri_pclk", + CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERI_SPI0_PCLK, "peri_spi0_ipclkport_i_pclk", "dout_peri_pclk", + CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERI_UART1_PCLK, "uart1_pclk", "dout_peri_pclk", + CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERI_UART2_PCLK, "uart2_pclk", "dout_peri_pclk", + CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), +}; + +static const struct samsung_cmu_info cmu_peri_info __initconst = { + .mux_clks = cmu_peri_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_peri_mux_clks), + .div_clks = cmu_peri_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_peri_div_clks), + .gate_clks = cmu_peri_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cmu_peri_gate_clks), + .fixed_clks = peri_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(peri_fixed_clks), + .nr_clk_ids = CMU_PERI_NR_CLK, + .clk_regs = cmu_peri_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_peri_clk_regs), +}; + +/** + * artpec8_cmu_probe - Probe function for ARTPEC platform clocks + * @pdev: Pointer to platform device + * + * Configure clock hierarchy for clock domains of ARTPEC platform + */ +static int __init artpec8_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + + info = of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +static const struct of_device_id artpec8_cmu_of_match[] = { + { + .compatible = "axis,artpec8-cmu-cmu", + .data = &cmu_cmu_info, + }, { + .compatible = "axis,artpec8-cmu-bus", + .data = &cmu_bus_info, + }, { + .compatible = "axis,artpec8-cmu-core", + .data = &cmu_core_info, + }, { + .compatible = "axis,artpec8-cmu-cpucl", + .data = &cmu_cpucl_info, + }, { + .compatible = "axis,artpec8-cmu-fsys", + .data = &cmu_fsys_info, + }, { + .compatible = "axis,artpec8-cmu-peri", + .data = &cmu_peri_info, + }, { + }, +}; + +static struct platform_driver artpec8_cmu_driver __refdata = { + .driver = { + .name = "artpec8-cmu", + .of_match_table = artpec8_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = artpec8_cmu_probe, +}; + +static int __init artpec8_cmu_init(void) +{ + return platform_driver_register(&artpec8_cmu_driver); +} +core_initcall(artpec8_cmu_init); -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: (subset) [PATCH v3 03/10] clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC 2025-08-25 11:44 ` [PATCH v3 03/10] clk: samsung: artpec-8: Add initial clock " Ravi Patel @ 2025-08-31 13:28 ` Krzysztof Kozlowski 0 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-31 13:28 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd, Ravi Patel Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc, Varada Pavani On Mon, 25 Aug 2025 17:14:29 +0530, Ravi Patel wrote: > Add initial clock support for Axis ARTPEC-8 SoC which is required > for enabling basic clock management. > > Add clock support for below CMU (Clock Management Unit) blocks > in ARTPEC-8 SoC: > - CMU_CMU > - CMU_BUS > - CMU_CORE > - CMU_CPUCL > - CMU_FSYS > - CMU_IMEM > - CMU_PERI > > [...] Applied, thanks! [03/10] clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC https://git.kernel.org/krzk/linux/c/bd5336e3f7040f300b01702215b45e6267a400cc Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <CGME20250825120715epcas5p3a0c8b6eaff7bdd69cbed6ce463079c64@epcas5p3.samsung.com>]
* [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC [not found] ` <CGME20250825120715epcas5p3a0c8b6eaff7bdd69cbed6ce463079c64@epcas5p3.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 2025-08-31 13:25 ` Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc From: SeonGu Kang <ksk4725@coasia.com> Document the compatible string for ARTPEC-8 SoC pinctrl block, which is similar to other Samsung SoC pinctrl blocks. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index de8460856141..9386dcd418c2 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -35,6 +35,7 @@ properties: compatible: enum: + - axis,artpec8-pinctrl - google,gs101-pinctrl - samsung,s3c2412-pinctrl - samsung,s3c2416-pinctrl -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC 2025-08-25 11:44 ` [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible " Ravi Patel @ 2025-08-31 13:25 ` Krzysztof Kozlowski 2025-09-01 3:41 ` Ravi Patel 0 siblings, 1 reply; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-31 13:25 UTC (permalink / raw) To: Ravi Patel, jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On 25/08/2025 13:44, Ravi Patel wrote: > From: SeonGu Kang <ksk4725@coasia.com> > > Document the compatible string for ARTPEC-8 SoC pinctrl block, > which is similar to other Samsung SoC pinctrl blocks. > > Signed-off-by: SeonGu Kang <ksk4725@coasia.com> > Acked-by: Rob Herring (Arm) <robh@kernel.org> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com> > --- > Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + > 1 file changed, 1 insertion(+) No wakeup-eint interrupts here? samsung,pinctrl-wakeup-interrupt.yaml? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC 2025-08-31 13:25 ` Krzysztof Kozlowski @ 2025-09-01 3:41 ` Ravi Patel 2025-09-01 5:11 ` Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-09-01 3:41 UTC (permalink / raw) To: 'Krzysztof Kozlowski', jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: 31 August 2025 18:55 > To: Ravi Patel <ravi.patel@samsung.com>; jesper.nilsson@axis.com; mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org; > krzk+dt@kernel.org; conor+dt@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com; alim.akhtar@samsung.com; > linus.walleij@linaro.org; tomasz.figa@gmail.com; catalin.marinas@arm.com; will@kernel.org; arnd@arndb.de > Cc: ksk4725@coasia.com; kenkim@coasia.com; pjsin865@coasia.com; gwk1013@coasia.com; hgkim05@coasia.com; > mingyoungbo@coasia.com; smn1196@coasia.com; pankaj.dubey@samsung.com; shradha.t@samsung.com; inbaraj.e@samsung.com; > swathi.ks@samsung.com; hrishikesh.d@samsung.com; dj76.yang@samsung.com; hypmean.kim@samsung.com; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-arm-kernel@axis.com; linux- > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-gpio@vger.kernel.org; soc@lists.linux.dev > Subject: Re: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC > > On 25/08/2025 13:44, Ravi Patel wrote: > > From: SeonGu Kang <ksk4725@coasia.com> > > > > Document the compatible string for ARTPEC-8 SoC pinctrl block, > > which is similar to other Samsung SoC pinctrl blocks. > > > > Signed-off-by: SeonGu Kang <ksk4725@coasia.com> > > Acked-by: Rob Herring (Arm) <robh@kernel.org> > > Signed-off-by: Ravi Patel <ravi.patel@samsung.com> > > --- > > Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + > > 1 file changed, 1 insertion(+) > > > No wakeup-eint interrupts here? samsung,pinctrl-wakeup-interrupt.yaml? I don't see any use case for external wake-up interrupt here (as of now). So wakeup-eint entry is not present in dts and yaml both. Thanks, Ravi > > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC 2025-09-01 3:41 ` Ravi Patel @ 2025-09-01 5:11 ` Krzysztof Kozlowski 2025-09-01 5:29 ` Ravi Patel 0 siblings, 1 reply; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-09-01 5:11 UTC (permalink / raw) To: Ravi Patel, jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On 01/09/2025 05:41, Ravi Patel wrote: > > >> -----Original Message----- >> From: Krzysztof Kozlowski <krzk@kernel.org> >> Sent: 31 August 2025 18:55 >> To: Ravi Patel <ravi.patel@samsung.com>; jesper.nilsson@axis.com; mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org; >> krzk+dt@kernel.org; conor+dt@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com; alim.akhtar@samsung.com; >> linus.walleij@linaro.org; tomasz.figa@gmail.com; catalin.marinas@arm.com; will@kernel.org; arnd@arndb.de >> Cc: ksk4725@coasia.com; kenkim@coasia.com; pjsin865@coasia.com; gwk1013@coasia.com; hgkim05@coasia.com; >> mingyoungbo@coasia.com; smn1196@coasia.com; pankaj.dubey@samsung.com; shradha.t@samsung.com; inbaraj.e@samsung.com; >> swathi.ks@samsung.com; hrishikesh.d@samsung.com; dj76.yang@samsung.com; hypmean.kim@samsung.com; linux- >> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-arm-kernel@axis.com; linux- >> clk@vger.kernel.org; devicetree@vger.kernel.org; linux-gpio@vger.kernel.org; soc@lists.linux.dev >> Subject: Re: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC >> >> On 25/08/2025 13:44, Ravi Patel wrote: >>> From: SeonGu Kang <ksk4725@coasia.com> >>> >>> Document the compatible string for ARTPEC-8 SoC pinctrl block, >>> which is similar to other Samsung SoC pinctrl blocks. >>> >>> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> >>> Acked-by: Rob Herring (Arm) <robh@kernel.org> >>> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> >>> --- >>> Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + >>> 1 file changed, 1 insertion(+) >> >> >> No wakeup-eint interrupts here? samsung,pinctrl-wakeup-interrupt.yaml? > > I don't see any use case for external wake-up interrupt here (as of now). It is more about hardware, not use case. Does this hardware has EINT wakeup pin banks? > So wakeup-eint entry is not present in dts and yaml both. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC 2025-09-01 5:11 ` Krzysztof Kozlowski @ 2025-09-01 5:29 ` Ravi Patel 2025-09-01 6:31 ` Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-09-01 5:29 UTC (permalink / raw) To: 'Krzysztof Kozlowski', jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: 01 September 2025 10:42 > To: Ravi Patel <ravi.patel@samsung.com>; jesper.nilsson@axis.com; mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org; > krzk+dt@kernel.org; conor+dt@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com; alim.akhtar@samsung.com; > linus.walleij@linaro.org; tomasz.figa@gmail.com; catalin.marinas@arm.com; will@kernel.org; arnd@arndb.de > Cc: ksk4725@coasia.com; kenkim@coasia.com; pjsin865@coasia.com; gwk1013@coasia.com; hgkim05@coasia.com; > mingyoungbo@coasia.com; smn1196@coasia.com; pankaj.dubey@samsung.com; shradha.t@samsung.com; inbaraj.e@samsung.com; > swathi.ks@samsung.com; hrishikesh.d@samsung.com; dj76.yang@samsung.com; hypmean.kim@samsung.com; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-arm-kernel@axis.com; linux- > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-gpio@vger.kernel.org; soc@lists.linux.dev > Subject: Re: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC > > On 01/09/2025 05:41, Ravi Patel wrote: > > > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzk@kernel.org> > >> Sent: 31 August 2025 18:55 > >> To: Ravi Patel <ravi.patel@samsung.com>; jesper.nilsson@axis.com; mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org; > >> krzk+dt@kernel.org; conor+dt@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com; alim.akhtar@samsung.com; > >> linus.walleij@linaro.org; tomasz.figa@gmail.com; catalin.marinas@arm.com; will@kernel.org; arnd@arndb.de > >> Cc: ksk4725@coasia.com; kenkim@coasia.com; pjsin865@coasia.com; gwk1013@coasia.com; hgkim05@coasia.com; > >> mingyoungbo@coasia.com; smn1196@coasia.com; pankaj.dubey@samsung.com; shradha.t@samsung.com; inbaraj.e@samsung.com; > >> swathi.ks@samsung.com; hrishikesh.d@samsung.com; dj76.yang@samsung.com; hypmean.kim@samsung.com; linux- > >> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-arm-kernel@axis.com; linux- > >> clk@vger.kernel.org; devicetree@vger.kernel.org; linux-gpio@vger.kernel.org; soc@lists.linux.dev > >> Subject: Re: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC > >> > >> On 25/08/2025 13:44, Ravi Patel wrote: > >>> From: SeonGu Kang <ksk4725@coasia.com> > >>> > >>> Document the compatible string for ARTPEC-8 SoC pinctrl block, > >>> which is similar to other Samsung SoC pinctrl blocks. > >>> > >>> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> > >>> Acked-by: Rob Herring (Arm) <robh@kernel.org> > >>> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> > >>> --- > >>> Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + > >>> 1 file changed, 1 insertion(+) > >> > >> > >> No wakeup-eint interrupts here? samsung,pinctrl-wakeup-interrupt.yaml? > > > > I don't see any use case for external wake-up interrupt here (as of now). > > It is more about hardware, not use case. Does this hardware has EINT > wakeup pin banks? I checked SFR sheet, ARTPEC-8 does not have any EINT wakeup pins or SFRs. Thanks, Ravi > > > So wakeup-eint entry is not present in dts and yaml both. > > > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC 2025-09-01 5:29 ` Ravi Patel @ 2025-09-01 6:31 ` Krzysztof Kozlowski 0 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-09-01 6:31 UTC (permalink / raw) To: Ravi Patel, jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On 01/09/2025 07:29, Ravi Patel wrote: >>>> >>>> No wakeup-eint interrupts here? samsung,pinctrl-wakeup-interrupt.yaml? >>> >>> I don't see any use case for external wake-up interrupt here (as of now). >> >> It is more about hardware, not use case. Does this hardware has EINT >> wakeup pin banks? > > I checked SFR sheet, ARTPEC-8 does not have any EINT wakeup pins or SFRs. OK Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <CGME20250825120720epcas5p491e16bbfbdbcd751acbb0c0e55f9e2a2@epcas5p4.samsung.com>]
* [PATCH v3 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration [not found] ` <CGME20250825120720epcas5p491e16bbfbdbcd751acbb0c0e55f9e2a2@epcas5p4.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 2025-08-29 10:11 ` Linus Walleij 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc, Priyadarsini G From: SeonGu Kang <ksk4725@coasia.com> Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 50 +++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 10 ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 63 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 5fe7c4b9f7bd..323487dfa8c2 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -76,6 +76,15 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static const struct samsung_pin_bank_type artpec_bank_type_off = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -1816,3 +1825,44 @@ const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { .ctrl = gs101_pin_ctrl, .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), }; + +/* pin banks of artpec8 pin-controller (FSYS0) */ +static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = { + ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00), + ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04), + ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08), + ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c), + ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10), + ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14), + ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18), + ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c), + ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20), + ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24), +}; + +/* pin banks of artpec8 pin-controller (PERIC) */ +static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = { + ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04), + ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c), +}; + +static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 FSYS data */ + .pin_banks = artpec8_pin_banks0, + .nr_banks = ARRAY_SIZE(artpec8_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 1 PERIC data */ + .pin_banks = artpec8_pin_banks1, + .nr_banks = ARRAY_SIZE(artpec8_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = { + .ctrl = artpec8_pin_ctrl, + .num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 362dc533186f..c9c38f8988dd 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -236,6 +236,16 @@ .name = id \ } +#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &artpec_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 24745e1d78ce..c099195fc464 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1482,6 +1482,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &s5pv210_of_data }, #endif #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 + { .compatible = "axis,artpec8-pinctrl", + .data = &artpec8_of_data }, { .compatible = "google,gs101-pinctrl", .data = &gs101_of_data }, { .compatible = "samsung,exynos2200-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 1cabcbe1401a..be2dee886d81 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -381,6 +381,7 @@ struct samsung_pmx_func { }; /* list of all exported SoC specific data */ +extern const struct samsung_pinctrl_of_match_data artpec8_of_data; extern const struct samsung_pinctrl_of_match_data exynos2200_of_data; extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration 2025-08-25 11:44 ` [PATCH v3 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration Ravi Patel @ 2025-08-29 10:11 ` Linus Walleij 2025-08-29 10:28 ` Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Linus Walleij @ 2025-08-29 10:11 UTC (permalink / raw) To: Ravi Patel Cc: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, tomasz.figa, catalin.marinas, will, arnd, ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc, Priyadarsini G Hi Ravi / SeonGu, thanks for your patch! On Mon, Aug 25, 2025 at 2:07 PM Ravi Patel <ravi.patel@samsung.com> wrote: > From: SeonGu Kang <ksk4725@coasia.com> > > Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. > > Signed-off-by: SeonGu Kang <ksk4725@coasia.com> > Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Please avoid CC to soc@kernel.org on these patches, they end up in the patchwork for immediate merging for SoC: https://patchwork.kernel.org/project/linux-soc/patch/20250825114436.46882-6-ravi.patel@samsung.com/ I think this is not you intention, the pinctrl portions will be merged by Krzysztof who sends it to me once that part is finished reviewing. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration 2025-08-29 10:11 ` Linus Walleij @ 2025-08-29 10:28 ` Krzysztof Kozlowski 2025-09-01 3:35 ` Ravi Patel 0 siblings, 1 reply; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-29 10:28 UTC (permalink / raw) To: Linus Walleij, Ravi Patel Cc: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, tomasz.figa, catalin.marinas, will, arnd, ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc, Priyadarsini G On 29/08/2025 12:11, Linus Walleij wrote: > Hi Ravi / SeonGu, > > thanks for your patch! > > On Mon, Aug 25, 2025 at 2:07 PM Ravi Patel <ravi.patel@samsung.com> wrote: > >> From: SeonGu Kang <ksk4725@coasia.com> >> >> Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. >> >> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> >> Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com> >> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> > > Please avoid CC to soc@kernel.org on these patches, they end up in the > patchwork for immediate merging for SoC: > https://patchwork.kernel.org/project/linux-soc/patch/20250825114436.46882-6-ravi.patel@samsung.com/ Yeah, that's odd - most likely old CC-list. This could happen if using b4 but there is no b4 being used here, so why Cc-ing according to some old files? > > I think this is not you intention, the pinctrl portions will be merged by > Krzysztof who sends it to me once that part is finished reviewing. Version for review should not be merged via soc@, so that's wrong process in any case. But you are right that I will be taking everything, thus soc@ is not involved at all. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v3 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration 2025-08-29 10:28 ` Krzysztof Kozlowski @ 2025-09-01 3:35 ` Ravi Patel 0 siblings, 0 replies; 27+ messages in thread From: Ravi Patel @ 2025-09-01 3:35 UTC (permalink / raw) To: 'Krzysztof Kozlowski', 'Linus Walleij' Cc: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, tomasz.figa, catalin.marinas, will, arnd, ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc, 'Priyadarsini G' > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: 29 August 2025 15:59 > To: Linus Walleij <linus.walleij@linaro.org>; Ravi Patel <ravi.patel@samsung.com> > Cc: jesper.nilsson@axis.com; mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; > s.nawrocki@samsung.com; cw00.choi@samsung.com; alim.akhtar@samsung.com; tomasz.figa@gmail.com; catalin.marinas@arm.com; > will@kernel.org; arnd@arndb.de; ksk4725@coasia.com; kenkim@coasia.com; pjsin865@coasia.com; gwk1013@coasia.com; > hgkim05@coasia.com; mingyoungbo@coasia.com; smn1196@coasia.com; pankaj.dubey@samsung.com; shradha.t@samsung.com; > inbaraj.e@samsung.com; swathi.ks@samsung.com; hrishikesh.d@samsung.com; dj76.yang@samsung.com; hypmean.kim@samsung.com; > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-arm-kernel@axis.com; > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-gpio@vger.kernel.org; soc@lists.linux.dev; Priyadarsini G > <priya.ganesh@samsung.com> > Subject: Re: [PATCH v3 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration > > On 29/08/2025 12:11, Linus Walleij wrote: > > Hi Ravi / SeonGu, > > > > thanks for your patch! > > > > On Mon, Aug 25, 2025 at 2:07 PM Ravi Patel <ravi.patel@samsung.com> wrote: > > > >> From: SeonGu Kang <ksk4725@coasia.com> > >> > >> Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. > >> > >> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> > >> Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com> > >> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> > > > > Please avoid CC to soc@kernel.org on these patches, they end up in the > > patchwork for immediate merging for SoC: > > https://patchwork.kernel.org/project/linux-soc/patch/20250825114436.46882-6-ravi.patel@samsung.com/ > > Yeah, that's odd - most likely old CC-list. This could happen if using > b4 but there is no b4 being used here, so why Cc-ing according to some > old files? > > > > > I think this is not you intention, the pinctrl portions will be merged by > > Krzysztof who sends it to me once that part is finished reviewing. > Version for review should not be merged via soc@, so that's wrong > process in any case. But you are right that I will be taking everything, > thus soc@ is not involved at all. Ok, I will remove soc@ while sending next version. Thanks, Ravi > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
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* [PATCH v3 06/10] dt-bindings: arm: Convert Axis board/soc bindings to json-schema [not found] ` <CGME20250825120725epcas5p36cdf2c4e839db307f1cc0dc81346b913@epcas5p3.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 2025-08-31 13:28 ` (subset) " Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc Convert Axis SoC bindings to DT schema format using json-schema. Existing bindings supports ARTPEC-6 SoC and board. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- .../devicetree/bindings/arm/axis.txt | 13 --------- .../devicetree/bindings/arm/axis.yaml | 29 +++++++++++++++++++ 2 files changed, 29 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt deleted file mode 100644 index ebd33a88776f..000000000000 --- a/Documentation/devicetree/bindings/arm/axis.txt +++ /dev/null @@ -1,13 +0,0 @@ -Axis Communications AB -ARTPEC series SoC Device Tree Bindings - -ARTPEC-6 ARM SoC -================ - -Required root node properties: -- compatible = "axis,artpec6"; - -ARTPEC-6 Development board: ---------------------------- -Required root node properties: -- compatible = "axis,artpec6-dev-board", "axis,artpec6"; diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml new file mode 100644 index 000000000000..f9c218dc6883 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/axis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC platforms + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + - linux-arm-kernel@axis.com + +description: | + ARM platforms using SoCs designed by Axis branded as "ARTPEC". + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Axis ARTPEC-6 SoC board + items: + - enum: + - axis,artpec6-dev-board + - const: axis,artpec6 + +additionalProperties: true + +... -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: (subset) [PATCH v3 06/10] dt-bindings: arm: Convert Axis board/soc bindings to json-schema 2025-08-25 11:44 ` [PATCH v3 06/10] dt-bindings: arm: Convert Axis board/soc bindings to json-schema Ravi Patel @ 2025-08-31 13:28 ` Krzysztof Kozlowski 0 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-31 13:28 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd, Ravi Patel Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On Mon, 25 Aug 2025 17:14:32 +0530, Ravi Patel wrote: > Convert Axis SoC bindings to DT schema format using json-schema. > Existing bindings supports ARTPEC-6 SoC and board. > > Applied, thanks! [06/10] dt-bindings: arm: Convert Axis board/soc bindings to json-schema https://git.kernel.org/krzk/linux/c/ea0484e4b82b3496310a94684dfad5e61421f633 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 27+ messages in thread
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* [PATCH v3 07/10] dt-bindings: arm: axis: Add ARTPEC-8 grizzly board [not found] ` <CGME20250825120730epcas5p347b6acfa329848471d55191150c8c983@epcas5p3.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 0 siblings, 0 replies; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc From: SungMin Park <smn1196@coasia.com> Document the Axis ARTPEC-8 SoC binding and the grizzly board which uses ARTPEC-8 SoC. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- Documentation/devicetree/bindings/arm/axis.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml index f9c218dc6883..63e9aca85db7 100644 --- a/Documentation/devicetree/bindings/arm/axis.yaml +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -8,6 +8,7 @@ title: Axis ARTPEC platforms maintainers: - Jesper Nilsson <jesper.nilsson@axis.com> + - Lars Persson <lars.persson@axis.com> - linux-arm-kernel@axis.com description: | @@ -24,6 +25,12 @@ properties: - axis,artpec6-dev-board - const: axis,artpec6 + - description: Axis ARTPEC-8 SoC board + items: + - enum: + - axis,artpec8-grizzly + - const: axis,artpec8 + additionalProperties: true ... -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
[parent not found: <CGME20250825120735epcas5p3c86b9db5f17c0938f1d53ef6014ab342@epcas5p3.samsung.com>]
* [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support [not found] ` <CGME20250825120735epcas5p3c86b9db5f17c0938f1d53ef6014ab342@epcas5p3.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 2025-08-29 7:56 ` Krzysztof Kozlowski 0 siblings, 1 reply; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc From: SungMin Park <smn1196@coasia.com> Add initial device tree support for Axis ARTPEC-8 SoC. This SoC contains 4 Cortex-A53 CPUs and several other peripheral IPs. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- MAINTAINERS | 12 + arch/arm64/Kconfig.platforms | 7 + arch/arm64/boot/dts/exynos/Makefile | 1 + .../boot/dts/exynos/axis/artpec-pinctrl.h | 36 +++ .../boot/dts/exynos/axis/artpec8-pinctrl.dtsi | 120 +++++++++ arch/arm64/boot/dts/exynos/axis/artpec8.dtsi | 244 ++++++++++++++++++ 6 files changed, 420 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..4d0c1f10ffd4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4102,6 +4102,18 @@ S: Maintained F: Documentation/devicetree/bindings/sound/axentia,* F: sound/soc/atmel/tse850-pcm5142.c +AXIS ARTPEC ARM64 SoC SUPPORT +M: Jesper Nilsson <jesper.nilsson@axis.com> +M: Lars Persson <lars.persson@axis.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +L: linux-arm-kernel@axis.com +S: Maintained +F: Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml +F: arch/arm64/boot/dts/exynos/axis/ +F: drivers/clk/samsung/clk-artpec*.c +F: include/dt-bindings/clock/axis,artpec*-clk.h + AXI-FAN-CONTROL HARDWARE MONITOR DRIVER M: Nuno Sá <nuno.sa@analog.com> L: linux-hwmon@vger.kernel.org diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a88f5ad9328c..959f79d73b40 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -40,6 +40,13 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, such as the Apple M1. +config ARCH_ARTPEC + bool "Axis Communications ARTPEC SoC Family" + depends on ARCH_EXYNOS + select ARM_GIC + help + This enables support for the ARMv8 based ARTPEC SoC Family. + config ARCH_AXIADO bool "Axiado SoC Family" select GPIOLIB diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index bdb9e9813e50..bcca63136557 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += axis subdir-y += google dtb-$(CONFIG_ARCH_EXYNOS) += \ diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h new file mode 100644 index 000000000000..70bd1dcac85e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Axis ARTPEC-8 SoC device tree pinctrl constants + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ + +#define ARTPEC_PIN_PULL_NONE 0 +#define ARTPEC_PIN_PULL_DOWN 1 +#define ARTPEC_PIN_PULL_UP 3 + +#define ARTPEC_PIN_FUNC_INPUT 0 +#define ARTPEC_PIN_FUNC_OUTPUT 1 +#define ARTPEC_PIN_FUNC_2 2 +#define ARTPEC_PIN_FUNC_3 3 +#define ARTPEC_PIN_FUNC_4 4 +#define ARTPEC_PIN_FUNC_5 5 +#define ARTPEC_PIN_FUNC_6 6 +#define ARTPEC_PIN_FUNC_EINT 0xf +#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT + +/* Drive strength for ARTPEC */ +#define ARTPEC_PIN_DRV_SR1 0x8 +#define ARTPEC_PIN_DRV_SR2 0x9 +#define ARTPEC_PIN_DRV_SR3 0xa +#define ARTPEC_PIN_DRV_SR4 0xb +#define ARTPEC_PIN_DRV_SR5 0xc +#define ARTPEC_PIN_DRV_SR6 0xd + +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi new file mode 100644 index 000000000000..8d239a70f1b4 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include "artpec-pinctrl.h" + +&pinctrl_fsys { + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps0: gps0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps1: gps1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + serial0_bus: serial0-bus-pins { + samsung,pins = "gpf4-4", "gpf4-5"; + samsung,pin-function = <ARTPEC_PIN_FUNC_2>; + samsung,pin-pud = <ARTPEC_PIN_PULL_UP>; + samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>; + }; +}; + +&pinctrl_peric { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi new file mode 100644 index 000000000000..db9833297982 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/axis,artpec8-clk.h> + +/ { + compatible = "axis,artpec8"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + pinctrl0 = &pinctrl_fsys; + pinctrl1 = &pinctrl_peric; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + }; + }; + + fin_pll: clock-finpll { + compatible = "fixed-factor-clock"; + clocks = <&osc_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fin_pll"; + }; + + osc_clk: clock-osc { + /* XXTI */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc_clk"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x17000000>; + #address-cells = <1>; + #size-cells = <1>; + + cmu_imem: clock-controller@10010000 { + compatible = "axis,artpec8-cmu-imem"; + reg = <0x10010000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>; + clock-names = "fin_pll", "aclk", "jpeg"; + }; + + timer@10040000 { + compatible = "axis,artpec8-mct", "samsung,exynos4210-mct"; + reg = <0x10040000 0x1000>; + clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller@10201000 { + compatible = "arm,gic-400"; + reg = <0x10201000 0x1000>, + <0x10202000 0x2000>, + <0x10204000 0x2000>, + <0x10206000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + cmu_cpucl: clock-controller@11410000 { + compatible = "axis,artpec8-cmu-cpucl"; + reg = <0x11410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>; + clock-names = "fin_pll", "switch"; + }; + + cmu_cmu: clock-controller@12400000 { + compatible = "axis,artpec8-cmu-cmu"; + reg = <0x12400000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + cmu_core: clock-controller@12410000 { + compatible = "axis,artpec8-cmu-core"; + reg = <0x12410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>, + <&cmu_cmu CLK_DOUT_CMU_CORE_DLP>; + clock-names = "fin_pll", "main", "dlp"; + }; + + cmu_bus: clock-controller@12c10000 { + compatible = "axis,artpec8-cmu-bus"; + reg = <0x12c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_BUS>, + <&cmu_cmu CLK_DOUT_CMU_BUS_DLP>; + clock-names = "fin_pll", "bus", "dlp"; + }; + + cmu_peri: clock-controller@16410000 { + compatible = "axis,artpec8-cmu-peri"; + reg = <0x16410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_PERI_IP>, + <&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>, + <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>; + clock-names = "fin_pll", "ip", "audio", "disp"; + }; + + pinctrl_peric: pinctrl@165f0000 { + compatible = "axis,artpec8-pinctrl"; + reg = <0x165f0000 0x1000>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + }; + + cmu_fsys: clock-controller@16c10000 { + compatible = "axis,artpec8-cmu-fsys"; + reg = <0x16c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; + clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; + }; + + pinctrl_fsys: pinctrl@16c30000 { + compatible = "axis,artpec8-pinctrl"; + reg = <0x16c30000 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + }; + + serial_0: serial@16cc0000 { + compatible = "axis,artpec8-uart"; + reg = <0x16cc0000 0x100>; + clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>, + <&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&serial0_bus>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support 2025-08-25 11:44 ` [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support Ravi Patel @ 2025-08-29 7:56 ` Krzysztof Kozlowski 2025-09-01 3:33 ` Ravi Patel 0 siblings, 1 reply; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-29 7:56 UTC (permalink / raw) To: Ravi Patel Cc: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd, ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On Mon, Aug 25, 2025 at 05:14:34PM +0530, Ravi Patel wrote: > config ARCH_AXIADO > bool "Axiado SoC Family" > select GPIOLIB > diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile > index bdb9e9813e50..bcca63136557 100644 > --- a/arch/arm64/boot/dts/exynos/Makefile > +++ b/arch/arm64/boot/dts/exynos/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += axis > subdir-y += google > > dtb-$(CONFIG_ARCH_EXYNOS) += \ > diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h > new file mode 100644 > index 000000000000..70bd1dcac85e > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h > @@ -0,0 +1,36 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Does not match rest of licenses. > +/* > + * Axis ARTPEC-8 SoC device tree pinctrl constants > + * > + * Copyright (c) 2025 Samsung Electronics Co., Ltd. > + * https://www.samsung.com > + * Copyright (c) 2025 Axis Communications AB. > + * https://www.axis.com > + */ > + > +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ > +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ > + > +#define ARTPEC_PIN_PULL_NONE 0 > +#define ARTPEC_PIN_PULL_DOWN 1 > +#define ARTPEC_PIN_PULL_UP 3 > + > +#define ARTPEC_PIN_FUNC_INPUT 0 > +#define ARTPEC_PIN_FUNC_OUTPUT 1 > +#define ARTPEC_PIN_FUNC_2 2 > +#define ARTPEC_PIN_FUNC_3 3 > +#define ARTPEC_PIN_FUNC_4 4 > +#define ARTPEC_PIN_FUNC_5 5 > +#define ARTPEC_PIN_FUNC_6 6 > +#define ARTPEC_PIN_FUNC_EINT 0xf > +#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT > + > +/* Drive strength for ARTPEC */ > +#define ARTPEC_PIN_DRV_SR1 0x8 > +#define ARTPEC_PIN_DRV_SR2 0x9 > +#define ARTPEC_PIN_DRV_SR3 0xa > +#define ARTPEC_PIN_DRV_SR4 0xb > +#define ARTPEC_PIN_DRV_SR5 0xc > +#define ARTPEC_PIN_DRV_SR6 0xd > + > +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ > diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi > new file mode 100644 > index 000000000000..8d239a70f1b4 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi > @@ -0,0 +1,120 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) This is Dual license, so why pincltr header is not? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support 2025-08-29 7:56 ` Krzysztof Kozlowski @ 2025-09-01 3:33 ` Ravi Patel 0 siblings, 0 replies; 27+ messages in thread From: Ravi Patel @ 2025-09-01 3:33 UTC (permalink / raw) To: 'Krzysztof Kozlowski' Cc: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd, ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: 29 August 2025 13:26 ... > Subject: Re: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support > > On Mon, Aug 25, 2025 at 05:14:34PM +0530, Ravi Patel wrote: > > config ARCH_AXIADO > > bool "Axiado SoC Family" > > select GPIOLIB > > diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile > > index bdb9e9813e50..bcca63136557 100644 > > --- a/arch/arm64/boot/dts/exynos/Makefile > > +++ b/arch/arm64/boot/dts/exynos/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > +subdir-y += axis > > subdir-y += google > > > > dtb-$(CONFIG_ARCH_EXYNOS) += \ > > diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h > > new file mode 100644 > > index 000000000000..70bd1dcac85e > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h > > @@ -0,0 +1,36 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > Does not match rest of licenses. > > > +/* > > + * Axis ARTPEC-8 SoC device tree pinctrl constants > > + * > > + * Copyright (c) 2025 Samsung Electronics Co., Ltd. > > + * https://www.samsung.com > > + * Copyright (c) 2025 Axis Communications AB. > > + * https://www.axis.com > > + */ > > + > > +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ > > +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ > > + > > +#define ARTPEC_PIN_PULL_NONE 0 ... > > +#define ARTPEC_PIN_DRV_SR6 0xd > > + > > +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ > > diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi > > new file mode 100644 > > index 000000000000..8d239a70f1b4 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi > > @@ -0,0 +1,120 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > This is Dual license, so why pincltr header is not? Thanks for the review. I will update the Dual license in pinctrl header in the next version. Thanks, Ravi > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <CGME20250825120740epcas5p2b43e92d4d025d267ad6386bdc2ff6af7@epcas5p2.samsung.com>]
* [PATCH v3 09/10] arm64: dts: axis: Add ARTPEC-8 Grizzly dts support [not found] ` <CGME20250825120740epcas5p2b43e92d4d025d267ad6386bdc2ff6af7@epcas5p2.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 0 siblings, 0 replies; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc From: SeonGu Kang <ksk4725@coasia.com> Add initial devcie tree for the ARTPEC-8 Grizzly board. The ARTPEC-8 Grizzly is a small board developed by Axis, based on the Axis ARTPEC-8 SoC. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- arch/arm64/boot/dts/exynos/axis/Makefile | 4 +++ .../boot/dts/exynos/axis/artpec8-grizzly.dts | 35 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/axis/Makefile create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts diff --git a/arch/arm64/boot/dts/exynos/axis/Makefile b/arch/arm64/boot/dts/exynos/axis/Makefile new file mode 100644 index 000000000000..ccf00de64016 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ARTPEC) += \ + artpec8-grizzly.dtb diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts new file mode 100644 index 000000000000..5ae864ec3193 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 Grizzly board device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +/dts-v1/; +#include "artpec8.dtsi" +#include "artpec8-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +/ { + model = "ARTPEC-8 grizzly board"; + compatible = "axis,artpec8-grizzly", "axis,artpec8"; + + aliases { + serial0 = &serial_0; + }; + + chosen { + stdout-path = &serial_0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&osc_clk { + clock-frequency = <50000000>; +}; -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
[parent not found: <CGME20250825120746epcas5p42d5fdba608b004e1f2c1c45eda5cac5f@epcas5p4.samsung.com>]
* [PATCH v3 10/10] arm64: defconfig: Enable Axis ARTPEC SoC [not found] ` <CGME20250825120746epcas5p42d5fdba608b004e1f2c1c45eda5cac5f@epcas5p4.samsung.com> @ 2025-08-25 11:44 ` Ravi Patel 0 siblings, 0 replies; 27+ messages in thread From: Ravi Patel @ 2025-08-25 11:44 UTC (permalink / raw) To: jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, krzk, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, ravi.patel, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc From: SungMin Park <smn1196@coasia.com> Enable the Axis ARTPEC-8 SoC in arm64 defconfig. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58f87d09366c..6660d3ee6f99 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y CONFIG_ARCH_APPLE=y +CONFIG_ARCH_ARTPEC=y CONFIG_ARCH_AXIADO=y CONFIG_ARCH_BCM=y CONFIG_ARCH_BCM2835=y -- 2.49.0 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 00/10] Add support for the Axis ARTPEC-8 SoC 2025-08-25 11:44 ` [PATCH v3 00/10] Add support for the Axis ARTPEC-8 SoC Ravi Patel ` (9 preceding siblings ...) [not found] ` <CGME20250825120746epcas5p42d5fdba608b004e1f2c1c45eda5cac5f@epcas5p4.samsung.com> @ 2025-08-25 12:35 ` Krzysztof Kozlowski 2025-08-31 13:29 ` Krzysztof Kozlowski 10 siblings, 1 reply; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-25 12:35 UTC (permalink / raw) To: Ravi Patel, jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On 25/08/2025 13:44, Ravi Patel wrote: > List of Samsung-provided IPs: > - UART > - Ethernet (Vendor: Synopsys) > - SDIO > - SPI > - HSI2C > - I2S > - CMU (Clock Management Unit) > - Pinctrl (GPIO) > - PCIe (Vendor: Synopsys) > - USB (Vendor: Synopsys) > > List of Axis-provided IPs: > - VIP (Image Sensor Processing IP) > - VPP (Video Post Processing) > - GPU > - CDC (Video Encoder) > > This patch series includes below changes: > - CMU (Clock Management Unit) driver and its bindings > - GPIO pinctrl configuration and its bindings > - Basic Device Tree for ARTPEC-8 SoC and boards > > The patch series has been tested on the ARTPEC-8 EVB with > Linux v6.15-rc5 and intended to be merged via the `arm-soc` tree. > > --- > Changes in v3: > - Rebased patchset on linux-samsung-soc "for-next" branch which includes round_rate() drop > - Add CPU mask in dtsi patch #8 > > Link to v2: https://lore.kernel.org/all/20250821123310.94089-1-ravi.patel@samsung.com/ Thanks for v2. Just a note: due to OSSE 25 I will look at it at a later time, probably next week. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 00/10] Add support for the Axis ARTPEC-8 SoC 2025-08-25 12:35 ` [PATCH v3 00/10] Add support for the Axis ARTPEC-8 SoC Krzysztof Kozlowski @ 2025-08-31 13:29 ` Krzysztof Kozlowski 0 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2025-08-31 13:29 UTC (permalink / raw) To: Ravi Patel, jesper.nilsson, mturquette, sboyd, robh, krzk+dt, conor+dt, s.nawrocki, cw00.choi, alim.akhtar, linus.walleij, tomasz.figa, catalin.marinas, will, arnd Cc: ksk4725, kenkim, pjsin865, gwk1013, hgkim05, mingyoungbo, smn1196, pankaj.dubey, shradha.t, inbaraj.e, swathi.ks, hrishikesh.d, dj76.yang, hypmean.kim, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree, linux-gpio, soc On 25/08/2025 14:35, Krzysztof Kozlowski wrote: > On 25/08/2025 13:44, Ravi Patel wrote: >> This patch series includes below changes: >> - CMU (Clock Management Unit) driver and its bindings >> - GPIO pinctrl configuration and its bindings >> - Basic Device Tree for ARTPEC-8 SoC and boards >> >> The patch series has been tested on the ARTPEC-8 EVB with >> Linux v6.15-rc5 and intended to be merged via the `arm-soc` tree. >> >> --- >> Changes in v3: >> - Rebased patchset on linux-samsung-soc "for-next" branch which includes round_rate() drop >> - Add CPU mask in dtsi patch #8 >> >> Link to v2: https://lore.kernel.org/all/20250821123310.94089-1-ravi.patel@samsung.com/ > > Thanks for v2. Just a note: due to OSSE 25 I will look at it at a later > time, probably next week. I applied few patches and checked the rest (left review when applicable). Please send v4 after rebasing and dropping applied patches. In general everything looks pretty nice, so I am very happy! Note, I will be closing my trees earlier this cycle, probably 1-2 weeks more max. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2025-09-01 6:31 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
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[not found] <CGME20250825120654epcas5p17bdbd92679d2b4c0f0c9bbb348163c0b@epcas5p1.samsung.com>
2025-08-25 11:44 ` [PATCH v3 00/10] Add support for the Axis ARTPEC-8 SoC Ravi Patel
[not found] ` <CGME20250825120659epcas5p47ea3377840efb9ce3d5901a27c85e4ed@epcas5p4.samsung.com>
2025-08-25 11:44 ` [PATCH v3 01/10] dt-bindings: clock: Add ARTPEC-8 clock controller Ravi Patel
2025-08-31 13:28 ` (subset) " Krzysztof Kozlowski
[not found] ` <CGME20250825120704epcas5p37385c913027d74d221012c4ae1550c73@epcas5p3.samsung.com>
2025-08-25 11:44 ` [PATCH v3 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC Ravi Patel
2025-08-31 13:28 ` (subset) " Krzysztof Kozlowski
[not found] ` <CGME20250825120710epcas5p421c3c8169019599e76f782bb7086e0e1@epcas5p4.samsung.com>
2025-08-25 11:44 ` [PATCH v3 03/10] clk: samsung: artpec-8: Add initial clock " Ravi Patel
2025-08-31 13:28 ` (subset) " Krzysztof Kozlowski
[not found] ` <CGME20250825120715epcas5p3a0c8b6eaff7bdd69cbed6ce463079c64@epcas5p3.samsung.com>
2025-08-25 11:44 ` [PATCH v3 04/10] dt-bindings: pinctrl: samsung: Add compatible " Ravi Patel
2025-08-31 13:25 ` Krzysztof Kozlowski
2025-09-01 3:41 ` Ravi Patel
2025-09-01 5:11 ` Krzysztof Kozlowski
2025-09-01 5:29 ` Ravi Patel
2025-09-01 6:31 ` Krzysztof Kozlowski
[not found] ` <CGME20250825120720epcas5p491e16bbfbdbcd751acbb0c0e55f9e2a2@epcas5p4.samsung.com>
2025-08-25 11:44 ` [PATCH v3 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration Ravi Patel
2025-08-29 10:11 ` Linus Walleij
2025-08-29 10:28 ` Krzysztof Kozlowski
2025-09-01 3:35 ` Ravi Patel
[not found] ` <CGME20250825120725epcas5p36cdf2c4e839db307f1cc0dc81346b913@epcas5p3.samsung.com>
2025-08-25 11:44 ` [PATCH v3 06/10] dt-bindings: arm: Convert Axis board/soc bindings to json-schema Ravi Patel
2025-08-31 13:28 ` (subset) " Krzysztof Kozlowski
[not found] ` <CGME20250825120730epcas5p347b6acfa329848471d55191150c8c983@epcas5p3.samsung.com>
2025-08-25 11:44 ` [PATCH v3 07/10] dt-bindings: arm: axis: Add ARTPEC-8 grizzly board Ravi Patel
[not found] ` <CGME20250825120735epcas5p3c86b9db5f17c0938f1d53ef6014ab342@epcas5p3.samsung.com>
2025-08-25 11:44 ` [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support Ravi Patel
2025-08-29 7:56 ` Krzysztof Kozlowski
2025-09-01 3:33 ` Ravi Patel
[not found] ` <CGME20250825120740epcas5p2b43e92d4d025d267ad6386bdc2ff6af7@epcas5p2.samsung.com>
2025-08-25 11:44 ` [PATCH v3 09/10] arm64: dts: axis: Add ARTPEC-8 Grizzly dts support Ravi Patel
[not found] ` <CGME20250825120746epcas5p42d5fdba608b004e1f2c1c45eda5cac5f@epcas5p4.samsung.com>
2025-08-25 11:44 ` [PATCH v3 10/10] arm64: defconfig: Enable Axis ARTPEC SoC Ravi Patel
2025-08-25 12:35 ` [PATCH v3 00/10] Add support for the Axis ARTPEC-8 SoC Krzysztof Kozlowski
2025-08-31 13:29 ` Krzysztof Kozlowski
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