From: Stephen Boyd <sboyd@kernel.org>
To: "Benoît Monin" <benoit.monin@bootlin.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Gregory CLEMENT" <gregory.clement@bootlin.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Rob Herring" <robh@kernel.org>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Théo Lebrun" <theo.lebrun@bootlin.com>,
"Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>
Cc: "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
"Tawfik Bayouk" <tawfik.bayouk@mobileye.com>,
"Sari Khoury" <sari.khoury@mobileye.com>,
"Benoît Monin" <benoit.monin@bootlin.com>
Subject: Re: [PATCH 09/19] clk: divider: check validity of flags when a table is provided
Date: Fri, 19 Sep 2025 22:24:36 -0700 [thread overview]
Message-ID: <175834587624.4354.6026619740146574818@lazor> (raw)
In-Reply-To: <20250903-clk-eyeq7-v1-9-3f5024b5d6e2@bootlin.com>
Quoting Benoît Monin (2025-09-03 05:47:16)
> If any of the flag CLK_DIVIDER_ONE_BASED, CLK_DIVIDER_POWER_OF_TWO,
> CLK_DIVIDER_MAX_AT_ZERO or CLK_DIVIDER_EVEN_INTEGERS is set, the divider
> table will be ignored in _get_div and _get_val. This can lead to subtle
> bug when a clock is registered with some flags and an optional table,
> with the clock rate and register value being computed with the wrong
> type of conversion.
>
> Prevent this by refusing to register a divider with both the flag and
> the table set.
>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
> drivers/clk/clk-divider.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 8e8f87024e76625f348f1d66c15a7a938fa0c4db..b4861d519bac2121dd015d094c94a5fee2480148 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -561,6 +561,13 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
> return ERR_PTR(-EINVAL);
> }
> }
Nitpick: Prefer a newline here.
> + if (table && (clk_divider_flags & (CLK_DIVIDER_ONE_BASED |
> + CLK_DIVIDER_POWER_OF_TWO |
> + CLK_DIVIDER_MAX_AT_ZERO |
> + CLK_DIVIDER_EVEN_INTEGERS))) {
> + pr_warn("divider table and flags incompatible\n");
This pr_warn() (and the one above this one) are not very helpful because
we don't know which clk is the problem. We also don't know if this is
going to cause boot failures for devices out there that have this flag
set and a table. Were all drivers audited?
I wonder if we can check this condition at compile time with some sort
of test on the clk_divider_flags expression to see if it is a compile
time constant along with the table pointer being a compile time constant
as well that isn't NULL?
> + return ERR_PTR(-EINVAL);
> + }
next prev parent reply other threads:[~2025-09-20 5:24 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-03 12:47 [PATCH 00/19] Add clock and reset support for Mobileye eyeQ7H Benoît Monin
2025-09-03 12:47 ` [PATCH 01/19] dt-bindings: soc: mobileye: rename to eyeq-olb.yaml Benoît Monin
2025-09-04 9:20 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 02/19] dt-bindings: clock: mobileye: rename to eyeq-clk.h Benoît Monin
2025-09-04 9:24 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 03/19] dt-bindings: soc: mobileye: add eyeQ7H compatibles Benoît Monin
2025-09-04 9:22 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 04/19] dt-bindings: clock: mobileye: add eyeQ7H clock indexes Benoît Monin
2025-09-04 9:23 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 05/19] dt-bindings: reset: add Mobileye eyeQ Benoît Monin
2025-09-04 9:25 ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 06/19] reset: eyeq: add eyeQ7H compatibles Benoît Monin
2025-09-03 12:47 ` [PATCH 07/19] clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy Benoît Monin
2025-09-20 5:14 ` Stephen Boyd
2025-09-25 11:47 ` Benoît Monin
2025-09-03 12:47 ` [PATCH 08/19] clk: divider: check divider validity for CLK_DIVIDER_EVEN_INTEGERS Benoît Monin
2025-09-20 5:15 ` Stephen Boyd
2025-09-25 11:51 ` Benoît Monin
2025-09-03 12:47 ` [PATCH 09/19] clk: divider: check validity of flags when a table is provided Benoît Monin
2025-09-20 5:24 ` Stephen Boyd [this message]
2025-09-25 11:55 ` Benoît Monin
2025-09-03 12:47 ` [PATCH 10/19] clk: eyeq: skip post-divisor when computing pll divisor Benoît Monin
2025-09-03 12:47 ` [PATCH 11/19] clk: eyeq: rename the parent field to parent_idx Benoît Monin
2025-09-03 12:47 ` [PATCH 12/19] clk: eyeq: lookup parent clock by name Benoît Monin
2025-09-03 12:47 ` [PATCH 13/19] clk: eyeq: prefix the PLL registers with the PLL type Benoît Monin
2025-09-03 12:47 ` [PATCH 14/19] clk: eyeq: rename the reg64 field of eqc_pll Benoît Monin
2025-09-03 12:47 ` [PATCH 15/19] clk: eyeq: add a type for the PLL Benoît Monin
2025-09-03 12:47 ` [PATCH 16/19] clk: eyeq: add two PLL types Benoît Monin
2025-09-03 12:47 ` [PATCH 17/19] clk: eyeq: add a parent field to the pll Benoît Monin
2025-09-03 12:47 ` [PATCH 18/19] clk: eyeq: add an optional clk_div_table to divider Benoît Monin
2025-09-03 12:47 ` [PATCH 19/19] clk: eyeq: add eyeQ7H compatibles Benoît Monin
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