* [PATCH v3 01/10] ASoC: mediatek: mt8189: add common header
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
@ 2025-10-31 7:31 ` Cyril Chao
2025-10-31 7:31 ` [PATCH v3 02/10] ASoC: mediatek: mt8189: support audio clock control Cyril Chao
` (9 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:31 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add header files for register definitions and structures.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
sound/soc/mediatek/mt8189/mt8189-afe-common.h | 240 +
.../mediatek/mt8189/mt8189-interconnection.h | 97 +
sound/soc/mediatek/mt8189/mt8189-reg.h | 10773 ++++++++++++++++
3 files changed, 11110 insertions(+)
create mode 100644 sound/soc/mediatek/mt8189/mt8189-afe-common.h
create mode 100644 sound/soc/mediatek/mt8189/mt8189-interconnection.h
create mode 100644 sound/soc/mediatek/mt8189/mt8189-reg.h
diff --git a/sound/soc/mediatek/mt8189/mt8189-afe-common.h b/sound/soc/mediatek/mt8189/mt8189-afe-common.h
new file mode 100644
index 000000000000..910d90d3d146
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-afe-common.h
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt8189-afe-common.h -- Mediatek 8189 audio driver definitions
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#ifndef _MT_8189_AFE_COMMON_H_
+#define _MT_8189_AFE_COMMON_H_
+
+#include <linux/regmap.h>
+
+#include <sound/soc.h>
+
+#include "mt8189-reg.h"
+#include "../common/mtk-base-afe.h"
+
+enum {
+ MTK_AFE_RATE_8K,
+ MTK_AFE_RATE_11K,
+ MTK_AFE_RATE_12K,
+ MTK_AFE_RATE_384K,
+ MTK_AFE_RATE_16K,
+ MTK_AFE_RATE_22K,
+ MTK_AFE_RATE_24K,
+ MTK_AFE_RATE_352K,
+ MTK_AFE_RATE_32K,
+ MTK_AFE_RATE_44K,
+ MTK_AFE_RATE_48K,
+ MTK_AFE_RATE_88K,
+ MTK_AFE_RATE_96K,
+ MTK_AFE_RATE_176K,
+ MTK_AFE_RATE_192K,
+ MTK_AFE_RATE_260K,
+};
+
+/* HW IPM 2.0 */
+enum {
+ MTK_AFE_IPM2P0_RATE_8K = 0x0,
+ MTK_AFE_IPM2P0_RATE_11K = 0x1,
+ MTK_AFE_IPM2P0_RATE_12K = 0x2,
+ MTK_AFE_IPM2P0_RATE_16K = 0x4,
+ MTK_AFE_IPM2P0_RATE_22K = 0x5,
+ MTK_AFE_IPM2P0_RATE_24K = 0x6,
+ MTK_AFE_IPM2P0_RATE_32K = 0x8,
+ MTK_AFE_IPM2P0_RATE_44K = 0x9,
+ MTK_AFE_IPM2P0_RATE_48K = 0xa,
+ MTK_AFE_IPM2P0_RATE_88K = 0xd,
+ MTK_AFE_IPM2P0_RATE_96K = 0xe,
+ MTK_AFE_IPM2P0_RATE_176K = 0x11,
+ MTK_AFE_IPM2P0_RATE_192K = 0x12,
+ MTK_AFE_IPM2P0_RATE_352K = 0x15,
+ MTK_AFE_IPM2P0_RATE_384K = 0x16,
+};
+
+enum {
+ MTK_AFE_DAI_MEMIF_RATE_8K,
+ MTK_AFE_DAI_MEMIF_RATE_16K,
+ MTK_AFE_DAI_MEMIF_RATE_32K,
+ MTK_AFE_DAI_MEMIF_RATE_48K,
+};
+
+enum {
+ MTK_AFE_PCM_RATE_8K,
+ MTK_AFE_PCM_RATE_16K,
+ MTK_AFE_PCM_RATE_32K,
+ MTK_AFE_PCM_RATE_48K,
+};
+
+enum {
+ MTKAIF_PROTOCOL_1,
+ MTKAIF_PROTOCOL_2,
+ MTKAIF_PROTOCOL_2_CLK_P2,
+};
+
+enum {
+ MT8189_MEMIF_DL0,
+ MT8189_MEMIF_DL1,
+ MT8189_MEMIF_DL2,
+ MT8189_MEMIF_DL3,
+ MT8189_MEMIF_DL4,
+ MT8189_MEMIF_DL5,
+ MT8189_MEMIF_DL6,
+ MT8189_MEMIF_DL7,
+ MT8189_MEMIF_DL8,
+ MT8189_MEMIF_DL23,
+ MT8189_MEMIF_DL24,
+ MT8189_MEMIF_DL25,
+ MT8189_MEMIF_DL_24CH,
+ MT8189_MEMIF_VUL0,
+ MT8189_MEMIF_VUL1,
+ MT8189_MEMIF_VUL2,
+ MT8189_MEMIF_VUL3,
+ MT8189_MEMIF_VUL4,
+ MT8189_MEMIF_VUL5,
+ MT8189_MEMIF_VUL6,
+ MT8189_MEMIF_VUL7,
+ MT8189_MEMIF_VUL8,
+ MT8189_MEMIF_VUL9,
+ MT8189_MEMIF_VUL10,
+ MT8189_MEMIF_VUL24,
+ MT8189_MEMIF_VUL25,
+ MT8189_MEMIF_VUL_CM0,
+ MT8189_MEMIF_VUL_CM1,
+ MT8189_MEMIF_ETDM_IN0,
+ MT8189_MEMIF_ETDM_IN1,
+ MT8189_MEMIF_HDMI,
+ MT8189_MEMIF_NUM,
+ MT8189_DAI_ADDA = MT8189_MEMIF_NUM,
+ MT8189_DAI_ADDA_CH34,
+ MT8189_DAI_ADDA_CH56,
+ MT8189_DAI_AP_DMIC,
+ MT8189_DAI_AP_DMIC_CH34,
+ MT8189_DAI_I2S_IN0,
+ MT8189_DAI_I2S_IN1,
+ MT8189_DAI_I2S_OUT0,
+ MT8189_DAI_I2S_OUT1,
+ MT8189_DAI_I2S_OUT4,
+ MT8189_DAI_PCM_0,
+ MT8189_DAI_TDM,
+ MT8189_DAI_TDM_DPTX,
+ MT8189_DAI_NUM,
+};
+
+/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
+enum {
+ MT8189_IRQ_0,
+ MT8189_IRQ_1,
+ MT8189_IRQ_2,
+ MT8189_IRQ_3,
+ MT8189_IRQ_4,
+ MT8189_IRQ_5,
+ MT8189_IRQ_6,
+ MT8189_IRQ_7,
+ MT8189_IRQ_8,
+ MT8189_IRQ_9,
+ MT8189_IRQ_10,
+ MT8189_IRQ_11,
+ MT8189_IRQ_12,
+ MT8189_IRQ_13,
+ MT8189_IRQ_14,
+ MT8189_IRQ_15,
+ MT8189_IRQ_16,
+ MT8189_IRQ_17,
+ MT8189_IRQ_18,
+ MT8189_IRQ_19,
+ MT8189_IRQ_20,
+ MT8189_IRQ_21,
+ MT8189_IRQ_22,
+ MT8189_IRQ_23,
+ MT8189_IRQ_24,
+ MT8189_IRQ_25,
+ MT8189_IRQ_26,
+ MT8189_IRQ_31,
+ MT8189_IRQ_NUM,
+};
+
+/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
+enum {
+ MT8189_CUS_IRQ_TDM, /* used only for TDM */
+ MT8189_CUS_IRQ_NUM,
+};
+
+enum {
+ /* AUDIO_ENGEN_CON0 */
+ MT8189_AUDIO_26M_EN_ON,
+ MT8189_AUDIO_F3P25M_EN_ON,
+ MT8189_AUDIO_APLL1_EN_ON,
+ MT8189_AUDIO_APLL2_EN_ON,
+ MT8189_AUDIO_F26M_EN_RST,
+ MT8189_MULTI_USER_RST,
+ MT8189_MULTI_USER_BYPASS,
+ /* AUDIO_TOP_CON4 */
+ MT8189_CG_AUDIO_HOPPING_CK,
+ MT8189_CG_AUDIO_F26M_CK,
+ MT8189_CG_APLL1_CK,
+ MT8189_CG_APLL2_CK,
+ MT8189_PDN_APLL_TUNER2,
+ MT8189_PDN_APLL_TUNER1,
+ MT8189_AUDIO_CG_NUM,
+};
+
+/* MCLK */
+enum {
+ MT8189_I2SIN0_MCK,
+ MT8189_I2SIN1_MCK,
+ MT8189_I2SOUT0_MCK,
+ MT8189_I2SOUT1_MCK,
+ MT8189_FMI2S_MCK,
+ MT8189_TDMOUT_MCK,
+ MT8189_TDMOUT_BCK,
+ MT8189_MCK_NUM,
+};
+
+enum {
+ CM0,
+ CM1,
+ CM_NUM,
+};
+
+struct clk;
+
+struct mt8189_afe_private {
+ struct clk **clk;
+ struct regmap *pmic_regmap;
+
+ /* dai */
+ void *dai_priv[MT8189_DAI_NUM];
+
+ /* adda */
+ int mtkaif_protocol;
+ int mtkaif_chosen_phase[4];
+ int mtkaif_phase_cycle[4];
+ int mtkaif_calibration_num_phase;
+ int mtkaif_dmic;
+ int mtkaif_dmic_ch34;
+
+ /* add for vs1 voter */
+ bool is_adda_dl_on;
+ bool is_adda_ul_on;
+ /* adda dl vol idx is at maximum */
+ bool is_adda_dl_max_vol;
+ /* current vote status of vs1 */
+ bool is_mt6363_vote;
+
+ /* mck */
+ int mck_rate[MT8189_MCK_NUM];
+
+ /* channel merge */
+ unsigned int cm_rate[CM_NUM];
+ unsigned int cm_channels;
+};
+
+int mt8189_dai_adda_register(struct mtk_base_afe *afe);
+int mt8189_dai_i2s_register(struct mtk_base_afe *afe);
+int mt8189_dai_pcm_register(struct mtk_base_afe *afe);
+int mt8189_dai_tdm_register(struct mtk_base_afe *afe);
+
+#endif
diff --git a/sound/soc/mediatek/mt8189/mt8189-interconnection.h b/sound/soc/mediatek/mt8189/mt8189-interconnection.h
new file mode 100644
index 000000000000..a244a2599fa2
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-interconnection.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Mediatek MT8189 audio driver interconnection definition
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#ifndef _MT8189_INTERCONNECTION_H_
+#define _MT8189_INTERCONNECTION_H_
+
+/* in port define */
+#define I_CONNSYS_I2S_CH1 0
+#define I_CONNSYS_I2S_CH2 1
+#define I_GAIN0_OUT_CH1 6
+#define I_GAIN0_OUT_CH2 7
+#define I_GAIN1_OUT_CH1 8
+#define I_GAIN1_OUT_CH2 9
+#define I_GAIN2_OUT_CH1 10
+#define I_GAIN2_OUT_CH2 11
+#define I_GAIN3_OUT_CH1 12
+#define I_GAIN3_OUT_CH2 13
+#define I_STF_CH1 14
+#define I_ADDA_UL_CH1 16
+#define I_ADDA_UL_CH2 17
+#define I_ADDA_UL_CH3 18
+#define I_ADDA_UL_CH4 19
+#define I_UL_PROX_CH1 20
+#define I_UL_PROX_CH2 21
+#define I_ADDA_UL_CH5 24
+#define I_ADDA_UL_CH6 25
+#define I_DMIC0_CH1 28
+#define I_DMIC0_CH2 29
+#define I_DMIC1_CH1 30
+#define I_DMIC1_CH2 31
+
+/* in port define >= 32 */
+#define I_32_OFFSET 32
+#define I_DL0_CH1 (32 - I_32_OFFSET)
+#define I_DL0_CH2 (33 - I_32_OFFSET)
+#define I_DL1_CH1 (34 - I_32_OFFSET)
+#define I_DL1_CH2 (35 - I_32_OFFSET)
+#define I_DL2_CH1 (36 - I_32_OFFSET)
+#define I_DL2_CH2 (37 - I_32_OFFSET)
+#define I_DL3_CH1 (38 - I_32_OFFSET)
+#define I_DL3_CH2 (39 - I_32_OFFSET)
+#define I_DL4_CH1 (40 - I_32_OFFSET)
+#define I_DL4_CH2 (41 - I_32_OFFSET)
+#define I_DL5_CH1 (42 - I_32_OFFSET)
+#define I_DL5_CH2 (43 - I_32_OFFSET)
+#define I_DL6_CH1 (44 - I_32_OFFSET)
+#define I_DL6_CH2 (45 - I_32_OFFSET)
+#define I_DL7_CH1 (46 - I_32_OFFSET)
+#define I_DL7_CH2 (47 - I_32_OFFSET)
+#define I_DL8_CH1 (48 - I_32_OFFSET)
+#define I_DL8_CH2 (49 - I_32_OFFSET)
+#define I_DL_24CH_CH1 (54 - I_32_OFFSET)
+#define I_DL_24CH_CH2 (55 - I_32_OFFSET)
+#define I_DL_24CH_CH3 (56 - I_32_OFFSET)
+#define I_DL_24CH_CH4 (57 - I_32_OFFSET)
+#define I_DL_24CH_CH5 (58 - I_32_OFFSET)
+#define I_DL_24CH_CH6 (59 - I_32_OFFSET)
+#define I_DL_24CH_CH7 (60 - I_32_OFFSET)
+#define I_DL_24CH_CH8 (61 - I_32_OFFSET)
+
+/* in port define >= 64 */
+#define I_64_OFFSET 64
+#define I_DL23_CH1 (78 - I_64_OFFSET)
+#define I_DL23_CH2 (79 - I_64_OFFSET)
+#define I_DL24_CH1 (80 - I_64_OFFSET)
+#define I_DL24_CH2 (81 - I_64_OFFSET)
+#define I_DL25_CH1 (82 - I_64_OFFSET)
+#define I_DL25_CH2 (83 - I_64_OFFSET)
+
+/* in port define >= 128 */
+#define I_128_OFFSET 128
+#define I_PCM_0_CAP_CH1 (130 - I_128_OFFSET)
+#define I_PCM_0_CAP_CH2 (131 - I_128_OFFSET)
+#define I_I2SIN0_CH1 (134 - I_128_OFFSET)
+#define I_I2SIN0_CH2 (135 - I_128_OFFSET)
+#define I_I2SIN1_CH1 (136 - I_128_OFFSET)
+#define I_I2SIN1_CH2 (137 - I_128_OFFSET)
+
+/* in port define >= 192 */
+#define I_192_OFFSET 192
+#define I_SRC_0_OUT_CH1 (198 - I_192_OFFSET)
+#define I_SRC_0_OUT_CH2 (199 - I_192_OFFSET)
+#define I_SRC_1_OUT_CH1 (200 - I_192_OFFSET)
+#define I_SRC_1_OUT_CH2 (201 - I_192_OFFSET)
+#define I_SRC_2_OUT_CH1 (202 - I_192_OFFSET)
+#define I_SRC_2_OUT_CH2 (203 - I_192_OFFSET)
+#define I_SRC_3_OUT_CH1 (204 - I_192_OFFSET)
+#define I_SRC_3_OUT_CH2 (205 - I_192_OFFSET)
+#define I_SRC_4_OUT_CH1 (206 - I_192_OFFSET)
+#define I_SRC_4_OUT_CH2 (207 - I_192_OFFSET)
+
+#endif
diff --git a/sound/soc/mediatek/mt8189/mt8189-reg.h b/sound/soc/mediatek/mt8189/mt8189-reg.h
new file mode 100644
index 000000000000..25f9658b6eae
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-reg.h
@@ -0,0 +1,10773 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt8189-reg.h -- Mediatek 8189 audio driver reg definition
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#ifndef _MT8189_REG_H_
+#define _MT8189_REG_H_
+
+ /* reg bit enum */
+enum {
+ MT8189_MEMIF_PBUF_SIZE_32_BYTES,
+ MT8189_MEMIF_PBUF_SIZE_64_BYTES,
+ MT8189_MEMIF_PBUF_SIZE_128_BYTES,
+ MT8189_MEMIF_PBUF_SIZE_256_BYTES,
+ MT8189_MEMIF_PBUF_SIZE_NUM,
+};
+
+/*****************************************************************************
+ * R E G I S T E R D E F I N I T I O N
+ *****************************************************************************/
+/* AUDIO_TOP_CON0 */
+#define PDN_MTKAIFV4_SFT 25
+#define PDN_MTKAIFV4_MASK 0x1
+#define PDN_MTKAIFV4_MASK_SFT (0x1 << 25)
+#define PDN_FM_I2S_SFT 24
+#define PDN_FM_I2S_MASK 0x1
+#define PDN_FM_I2S_MASK_SFT (0x1 << 24)
+#define PDN_HW_GAIN01_SFT 21
+#define PDN_HW_GAIN01_MASK 0x1
+#define PDN_HW_GAIN01_MASK_SFT (0x1 << 21)
+#define PDN_HW_GAIN23_SFT 20
+#define PDN_HW_GAIN23_MASK 0x1
+#define PDN_HW_GAIN23_MASK_SFT (0x1 << 20)
+#define PDN_STF_SFT 19
+#define PDN_STF_MASK 0x1
+#define PDN_STF_MASK_SFT (0x1 << 19)
+#define PDN_CM0_SFT 18
+#define PDN_CM0_MASK 0x1
+#define PDN_CM0_MASK_SFT (0x1 << 18)
+#define PDN_CM1_SFT 17
+#define PDN_CM1_MASK 0x1
+#define PDN_CM1_MASK_SFT (0x1 << 17)
+#define PDN_PCM0_SFT 14
+#define PDN_PCM0_MASK 0x1
+#define PDN_PCM0_MASK_SFT (0x1 << 14)
+#define PDN_DL0_NLE_SFT 11
+#define PDN_DL0_NLE_MASK 0x1
+#define PDN_DL0_NLE_MASK_SFT (0x1 << 11)
+#define PDN_DL0_PREDIS_SFT 10
+#define PDN_DL0_PREDIS_MASK 0x1
+#define PDN_DL0_PREDIS_MASK_SFT (0x1 << 10)
+#define PDN_DL0_DAC_SFT 9
+#define PDN_DL0_DAC_MASK 0x1
+#define PDN_DL0_DAC_MASK_SFT (0x1 << 9)
+#define PDN_DL0_DAC_HIRES_SFT 8
+#define PDN_DL0_DAC_HIRES_MASK 0x1
+#define PDN_DL0_DAC_HIRES_MASK_SFT (0x1 << 8)
+#define PDN_DL0_DAC_TML_SFT 7
+#define PDN_DL0_DAC_TML_MASK 0x1
+#define PDN_DL0_DAC_TML_MASK_SFT (0x1 << 7)
+
+/* AUDIO_TOP_CON1 */
+#define PDN_UL0_ADC_SFT 23
+#define PDN_UL0_ADC_MASK 0x1
+#define PDN_UL0_ADC_MASK_SFT (0x1 << 23)
+#define PDN_UL0_TML_SFT 22
+#define PDN_UL0_TML_MASK 0x1
+#define PDN_UL0_TML_MASK_SFT (0x1 << 22)
+#define PDN_UL0_ADC_HIRES_SFT 21
+#define PDN_UL0_ADC_HIRES_MASK 0x1
+#define PDN_UL0_ADC_HIRES_MASK_SFT (0x1 << 21)
+#define PDN_UL0_ADC_HIRES_TML_SFT 20
+#define PDN_UL0_ADC_HIRES_TML_MASK 0x1
+#define PDN_UL0_ADC_HIRES_TML_MASK_SFT (0x1 << 20)
+#define PDN_UL1_ADC_SFT 19
+#define PDN_UL1_ADC_MASK 0x1
+#define PDN_UL1_ADC_MASK_SFT (0x1 << 19)
+#define PDN_UL1_TML_SFT 18
+#define PDN_UL1_TML_MASK 0x1
+#define PDN_UL1_TML_MASK_SFT (0x1 << 18)
+#define PDN_UL1_ADC_HIRES_SFT 17
+#define PDN_UL1_ADC_HIRES_MASK 0x1
+#define PDN_UL1_ADC_HIRES_MASK_SFT (0x1 << 17)
+#define PDN_UL1_ADC_HIRES_TML_SFT 16
+#define PDN_UL1_ADC_HIRES_TML_MASK 0x1
+#define PDN_UL1_ADC_HIRES_TML_MASK_SFT (0x1 << 16)
+#define PDN_DMIC0_ADC_SFT 7
+#define PDN_DMIC0_ADC_MASK 0x1
+#define PDN_DMIC0_ADC_MASK_SFT (0x1 << 7)
+#define PDN_DMIC1_ADC_SFT 3
+#define PDN_DMIC1_ADC_MASK 0x1
+#define PDN_DMIC1_ADC_MASK_SFT (0x1 << 3)
+
+/* AUDIO_TOP_CON2 */
+#define PDN_TDM_OUT_SFT 24
+#define PDN_TDM_OUT_MASK 0x1
+#define PDN_TDM_OUT_MASK_SFT (0x1 << 24)
+#define PDN_ETDM_OUT0_SFT 21
+#define PDN_ETDM_OUT0_MASK 0x1
+#define PDN_ETDM_OUT0_MASK_SFT (0x1 << 21)
+#define PDN_ETDM_OUT1_SFT 20
+#define PDN_ETDM_OUT1_MASK 0x1
+#define PDN_ETDM_OUT1_MASK_SFT (0x1 << 20)
+#define PDN_ETDM_OUT4_SFT 17
+#define PDN_ETDM_OUT4_MASK 0x1
+#define PDN_ETDM_OUT4_MASK_SFT (0x1 << 17)
+#define PDN_ETDM_IN0_SFT 13
+#define PDN_ETDM_IN0_MASK 0x1
+#define PDN_ETDM_IN0_MASK_SFT (0x1 << 13)
+#define PDN_ETDM_IN1_SFT 12
+#define PDN_ETDM_IN1_MASK 0x1
+#define PDN_ETDM_IN1_MASK_SFT (0x1 << 12)
+
+/* AUDIO_TOP_CON3 */
+#define PDN_CONNSYS_I2S_ASRC_SFT 25
+#define PDN_CONNSYS_I2S_ASRC_MASK 0x1
+#define PDN_CONNSYS_I2S_ASRC_MASK_SFT (0x1 << 25)
+#define PDN_GENERAL0_ASRC_SFT 24
+#define PDN_GENERAL0_ASRC_MASK 0x1
+#define PDN_GENERAL0_ASRC_MASK_SFT (0x1 << 24)
+#define PDN_GENERAL1_ASRC_SFT 23
+#define PDN_GENERAL1_ASRC_MASK 0x1
+#define PDN_GENERAL1_ASRC_MASK_SFT (0x1 << 23)
+#define PDN_GENERAL2_ASRC_SFT 22
+#define PDN_GENERAL2_ASRC_MASK 0x1
+#define PDN_GENERAL2_ASRC_MASK_SFT (0x1 << 22)
+#define PDN_GENERAL3_ASRC_SFT 21
+#define PDN_GENERAL3_ASRC_MASK 0x1
+#define PDN_GENERAL3_ASRC_MASK_SFT (0x1 << 21)
+#define PDN_GENERAL4_ASRC_SFT 20
+#define PDN_GENERAL4_ASRC_MASK 0x1
+#define PDN_GENERAL4_ASRC_MASK_SFT (0x1 << 20)
+
+/* AUDIO_TOP_CON4 */
+#define PDN_APLL_TUNER1_SFT 13
+#define PDN_APLL_TUNER1_MASK 0x1
+#define PDN_APLL_TUNER1_MASK_SFT (0x1 << 13)
+#define PDN_APLL_TUNER2_SFT 12
+#define PDN_APLL_TUNER2_MASK 0x1
+#define PDN_APLL_TUNER2_MASK_SFT (0x1 << 12)
+#define CG_H208M_CK_SFT 4
+#define CG_H208M_CK_MASK 0x1
+#define CG_H208M_CK_MASK_SFT (0x1 << 4)
+#define CG_APLL2_CK_SFT 3
+#define CG_APLL2_CK_MASK 0x1
+#define CG_APLL2_CK_MASK_SFT (0x1 << 3)
+#define CG_APLL1_CK_SFT 2
+#define CG_APLL1_CK_MASK 0x1
+#define CG_APLL1_CK_MASK_SFT (0x1 << 2)
+#define CG_AUDIO_F26M_CK_SFT 1
+#define CG_AUDIO_F26M_CK_MASK 0x1
+#define CG_AUDIO_F26M_CK_MASK_SFT (0x1 << 1)
+#define CG_AUDIO_HOPPING_CK_SFT 0
+#define CG_AUDIO_HOPPING_CK_MASK 0x1
+#define CG_AUDIO_HOPPING_CK_MASK_SFT (0x1 << 0)
+
+/* AUDIO_ENGEN_CON0 */
+/* AUDIO_ENGEN_CON0_USER1 */
+/* AUDIO_ENGEN_CON0_USER2 */
+#define MULTI_USER_BYPASS_SFT 17
+#define MULTI_USER_BYPASS_MASK 0x1
+#define MULTI_USER_BYPASS_MASK_SFT (0x1 << 17)
+#define MULTI_USER_RST_SFT 16
+#define MULTI_USER_RST_MASK 0x1
+#define MULTI_USER_RST_MASK_SFT (0x1 << 16)
+#define AUDIO_F26M_EN_RST_SFT 8
+#define AUDIO_F26M_EN_RST_MASK 0x1
+#define AUDIO_F26M_EN_RST_MASK_SFT (0x1 << 8)
+#define AUDIO_APLL2_EN_ON_SFT 3
+#define AUDIO_APLL2_EN_ON_MASK 0x1
+#define AUDIO_APLL2_EN_ON_MASK_SFT (0x1 << 3)
+#define AUDIO_APLL1_EN_ON_SFT 2
+#define AUDIO_APLL1_EN_ON_MASK 0x1
+#define AUDIO_APLL1_EN_ON_MASK_SFT (0x1 << 2)
+#define AUDIO_F3P25M_EN_ON_SFT 1
+#define AUDIO_F3P25M_EN_ON_MASK 0x1
+#define AUDIO_F3P25M_EN_ON_MASK_SFT (0x1 << 1)
+#define AUDIO_26M_EN_ON_SFT 0
+#define AUDIO_26M_EN_ON_MASK 0x1
+#define AUDIO_26M_EN_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_SINEGEN_CON0 */
+#define DAC_EN_SFT 26
+#define DAC_EN_MASK 0x1
+#define DAC_EN_MASK_SFT (0x1 << 26)
+#define TIE_SW_CH2_SFT 25
+#define TIE_SW_CH2_MASK 0x1
+#define TIE_SW_CH2_MASK_SFT (0x1 << 25)
+#define TIE_SW_CH1_SFT 24
+#define TIE_SW_CH1_MASK 0x1
+#define TIE_SW_CH1_MASK_SFT (0x1 << 24)
+#define AMP_DIV_CH2_SFT 20
+#define AMP_DIV_CH2_MASK 0xf
+#define AMP_DIV_CH2_MASK_SFT (0xf << 20)
+#define FREQ_DIV_CH2_SFT 12
+#define FREQ_DIV_CH2_MASK 0x1f
+#define FREQ_DIV_CH2_MASK_SFT (0x1f << 12)
+#define AMP_DIV_CH1_SFT 8
+#define AMP_DIV_CH1_MASK 0xf
+#define AMP_DIV_CH1_MASK_SFT (0xf << 8)
+#define FREQ_DIV_CH1_SFT 0
+#define FREQ_DIV_CH1_MASK 0x1f
+#define FREQ_DIV_CH1_MASK_SFT (0x1f << 0)
+
+/* AFE_SINEGEN_CON1 */
+#define SINE_DOMAIN_SFT 20
+#define SINE_DOMAIN_MASK 0x7
+#define SINE_DOMAIN_MASK_SFT (0x7 << 20)
+#define SINE_MODE_SFT 12
+#define SINE_MODE_MASK 0x1f
+#define SINE_MODE_MASK_SFT (0x1f << 12)
+#define INNER_LOOP_BACKI_SEL_SFT 8
+#define INNER_LOOP_BACKI_SEL_MASK 0x1
+#define INNER_LOOP_BACKI_SEL_MASK_SFT (0x1 << 8)
+#define INNER_LOOP_BACK_MODE_SFT 0
+#define INNER_LOOP_BACK_MODE_MASK 0xff
+#define INNER_LOOP_BACK_MODE_MASK_SFT (0xff << 0)
+
+/* AFE_SINEGEN_CON2 */
+#define TIE_CH1_CONSTANT_SFT 0
+#define TIE_CH1_CONSTANT_MASK 0xffffffff
+#define TIE_CH1_CONSTANT_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SINEGEN_CON3 */
+#define TIE_CH2_CONSTANT_SFT 0
+#define TIE_CH2_CONSTANT_MASK 0xffffffff
+#define TIE_CH2_CONSTANT_MASK_SFT (0xffffffff << 0)
+
+/* AFE_APLL1_TUNER_CFG */
+#define UPPER_BOUND_SFT 8
+#define UPPER_BOUND_MASK 0xff
+#define UPPER_BOUND_MASK_SFT (0xff << 8)
+#define APLL_DIV_SFT 4
+#define APLL_DIV_MASK 0xf
+#define APLL_DIV_MASK_SFT (0xf << 4)
+#define XTAL_EN_128FS_SEL_SFT 1
+#define XTAL_EN_128FS_SEL_MASK 0x3
+#define XTAL_EN_128FS_SEL_MASK_SFT (0x3 << 1)
+#define FREQ_TUNER_EN_SFT 0
+#define FREQ_TUNER_EN_MASK 0x1
+#define FREQ_TUNER_EN_MASK_SFT (0x1 << 0)
+
+/* AFE_APLL1_TUNER_MON0 */
+#define TUNER_MON_SFT 0
+#define TUNER_MON_MASK 0xffffffff
+#define TUNER_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_APLL2_TUNER_CFG */
+#define UPPER_BOUND_SFT 8
+#define UPPER_BOUND_MASK 0xff
+#define UPPER_BOUND_MASK_SFT (0xff << 8)
+#define APLL_DIV_SFT 4
+#define APLL_DIV_MASK 0xf
+#define APLL_DIV_MASK_SFT (0xf << 4)
+#define XTAL_EN_128FS_SEL_SFT 1
+#define XTAL_EN_128FS_SEL_MASK 0x3
+#define XTAL_EN_128FS_SEL_MASK_SFT (0x3 << 1)
+#define FREQ_TUNER_EN_SFT 0
+#define FREQ_TUNER_EN_MASK 0x1
+#define FREQ_TUNER_EN_MASK_SFT (0x1 << 0)
+
+/* AFE_APLL2_TUNER_MON0 */
+#define TUNER_MON_SFT 0
+#define TUNER_MON_MASK 0xffffffff
+#define TUNER_MON_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_TOP_RG0 */
+#define RESERVE_RG_SFT 0
+#define RESERVE_RG_MASK 0xffffffff
+#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_TOP_RG1 */
+#define RESERVE_RG_SFT 0
+#define RESERVE_RG_MASK 0xffffffff
+#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_TOP_RG2 */
+#define RESERVE_RG_SFT 0
+#define RESERVE_RG_MASK 0xffffffff
+#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_TOP_RG3 */
+#define RESERVE_RG_SFT 0
+#define RESERVE_RG_MASK 0xffffffff
+#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_TOP_RG4 */
+#define RESERVE_RG_SFT 0
+#define RESERVE_RG_MASK 0xffffffff
+#define RESERVE_RG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SPM_CONTROL_REQ */
+#define AFE_DDREN_REQ_SFT 4
+#define AFE_DDREN_REQ_MASK 0x1
+#define AFE_DDREN_REQ_MASK_SFT (0x1 << 4)
+#define AFE_INFRA_REQ_SFT 3
+#define AFE_INFRA_REQ_MASK 0x1
+#define AFE_INFRA_REQ_MASK_SFT (0x1 << 3)
+#define AFE_VRF18_REQ_SFT 2
+#define AFE_VRF18_REQ_MASK 0x1
+#define AFE_VRF18_REQ_MASK_SFT (0x1 << 2)
+#define AFE_APSRC_REQ_SFT 1
+#define AFE_APSRC_REQ_MASK 0x1
+#define AFE_APSRC_REQ_MASK_SFT (0x1 << 1)
+#define AFE_SRCCLKENA_REQ_SFT 0
+#define AFE_SRCCLKENA_REQ_MASK 0x1
+#define AFE_SRCCLKENA_REQ_MASK_SFT (0x1 << 0)
+
+/* AFE_SPM_CONTROL_ACK */
+#define SPM_RESOURCE_CONTROL_ACK_SFT 0
+#define SPM_RESOURCE_CONTROL_ACK_MASK 0xffffffff
+#define SPM_RESOURCE_CONTROL_ACK_MASK_SFT (0xffffffff << 0)
+
+/* AUD_TOP_CFG_VCORE_RG */
+#define AUD_TOP_CFG_SFT 0
+#define AUD_TOP_CFG_MASK 0xffffffff
+#define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_TOP_IP_VERSION */
+#define AUDIO_TOP_IP_VERSION_SFT 0
+#define AUDIO_TOP_IP_VERSION_MASK 0xffffffff
+#define AUDIO_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_ENGEN_CON0_MON */
+#define AUDIO_ENGEN_MON_SFT 0
+#define AUDIO_ENGEN_MON_MASK 0xffffffff
+#define AUDIO_ENGEN_MON_MASK_SFT (0xffffffff << 0)
+
+/* AUD_TOP_CFG_VLP_RG */
+#define AUD_TOP_CFG_SFT 0
+#define AUD_TOP_CFG_MASK 0xffffffff
+#define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0)
+
+/* AUD_TOP_MON_RG */
+#define AUD_TOP_MON_SFT 0
+#define AUD_TOP_MON_MASK 0xffffffff
+#define AUD_TOP_MON_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_USE_DEFAULT_DELSEL0 */
+#define USE_DEFAULT_DELSEL_RG_SFT 0
+#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff
+#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_USE_DEFAULT_DELSEL1 */
+#define USE_DEFAULT_DELSEL_RG_SFT 0
+#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff
+#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0)
+
+/* AUDIO_USE_DEFAULT_DELSEL2 */
+#define USE_DEFAULT_DELSEL_RG_SFT 0
+#define USE_DEFAULT_DELSEL_RG_MASK 0xffffffff
+#define USE_DEFAULT_DELSEL_RG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CONNSYS_I2S_IPM_VER_MON */
+#define RG_CONNSYS_I2S_IPM_VER_MON_SFT 0
+#define RG_CONNSYS_I2S_IPM_VER_MON_MASK 0xffffffff
+#define RG_CONNSYS_I2S_IPM_VER_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CONNSYS_I2S_MON_SEL */
+#define RG_CONNSYS_I2S_MON_SEL_SFT 0
+#define RG_CONNSYS_I2S_MON_SEL_MASK 0xff
+#define RG_CONNSYS_I2S_MON_SEL_MASK_SFT (0xff << 0)
+
+/* AFE_CONNSYS_I2S_MON */
+#define RG_CONNSYS_I2S_MON_SFT 0
+#define RG_CONNSYS_I2S_MON_MASK 0xffffffff
+#define RG_CONNSYS_I2S_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CONNSYS_I2S_CON */
+#define I2S_SOFT_RST_SFT 31
+#define I2S_SOFT_RST_MASK 0x1
+#define I2S_SOFT_RST_MASK_SFT (0x1 << 31)
+#define BCK_NEG_EG_LATCH_SFT 30
+#define BCK_NEG_EG_LATCH_MASK 0x1
+#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
+#define BCK_INV_SFT 29
+#define BCK_INV_MASK 0x1
+#define BCK_INV_MASK_SFT (0x1 << 29)
+#define I2SIN_PAD_SEL_SFT 28
+#define I2SIN_PAD_SEL_MASK 0x1
+#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)
+#define I2S_LOOPBACK_SFT 20
+#define I2S_LOOPBACK_MASK 0x1
+#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
+#define I2S_HDEN_SFT 12
+#define I2S_HDEN_MASK 0x1
+#define I2S_HDEN_MASK_SFT (0x1 << 12)
+#define I2S_MODE_SFT 8
+#define I2S_MODE_MASK 0xf
+#define I2S_MODE_MASK_SFT (0xf << 8)
+#define I2S_BYPSRC_SFT 6
+#define I2S_BYPSRC_MASK 0x1
+#define I2S_BYPSRC_MASK_SFT (0x1 << 6)
+#define INV_LRCK_SFT 5
+#define INV_LRCK_MASK 0x1
+#define INV_LRCK_MASK_SFT (0x1 << 5)
+#define I2S_FMT_SFT 3
+#define I2S_FMT_MASK 0x1
+#define I2S_FMT_MASK_SFT (0x1 << 3)
+#define I2S_SRC_SFT 2
+#define I2S_SRC_MASK 0x1
+#define I2S_SRC_MASK_SFT (0x1 << 2)
+#define I2S_WLEN_SFT 1
+#define I2S_WLEN_MASK 0x1
+#define I2S_WLEN_MASK_SFT (0x1 << 1)
+#define I2S_EN_SFT 0
+#define I2S_EN_MASK 0x1
+#define I2S_EN_MASK_SFT (0x1 << 0)
+
+/* AFE_PCM0_INTF_CON0 */
+#define PCM0_HDEN_SFT 26
+#define PCM0_HDEN_MASK 0x1
+#define PCM0_HDEN_MASK_SFT (0x1 << 26)
+#define PCM0_SYNC_DELSEL_SFT 25
+#define PCM0_SYNC_DELSEL_MASK 0x1
+#define PCM0_SYNC_DELSEL_MASK_SFT (0x1 << 25)
+#define PCM0_TX_LR_SWAP_SFT 24
+#define PCM0_TX_LR_SWAP_MASK 0x1
+#define PCM0_TX_LR_SWAP_MASK_SFT (0x1 << 24)
+#define PCM0_SYNC_OUT_INV_SFT 23
+#define PCM0_SYNC_OUT_INV_MASK 0x1
+#define PCM0_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
+#define PCM0_BCLK_OUT_INV_SFT 22
+#define PCM0_BCLK_OUT_INV_MASK 0x1
+#define PCM0_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
+#define PCM0_SYNC_IN_INV_SFT 21
+#define PCM0_SYNC_IN_INV_MASK 0x1
+#define PCM0_SYNC_IN_INV_MASK_SFT (0x1 << 21)
+#define PCM0_BCLK_IN_INV_SFT 20
+#define PCM0_BCLK_IN_INV_MASK 0x1
+#define PCM0_BCLK_IN_INV_MASK_SFT (0x1 << 20)
+#define PCM0_TX_LCH_RPT_SFT 19
+#define PCM0_TX_LCH_RPT_MASK 0x1
+#define PCM0_TX_LCH_RPT_MASK_SFT (0x1 << 19)
+#define PCM0_VBT_16K_MODE_SFT 18
+#define PCM0_VBT_16K_MODE_MASK 0x1
+#define PCM0_VBT_16K_MODE_MASK_SFT (0x1 << 18)
+#define PCM0_BIT_LENGTH_SFT 16
+#define PCM0_BIT_LENGTH_MASK 0x3
+#define PCM0_BIT_LENGTH_MASK_SFT (0x3 << 16)
+#define PCM0_WLEN_SFT 14
+#define PCM0_WLEN_MASK 0x3
+#define PCM0_WLEN_MASK_SFT (0x3 << 14)
+#define PCM0_SYNC_LENGTH_SFT 9
+#define PCM0_SYNC_LENGTH_MASK 0x1f
+#define PCM0_SYNC_LENGTH_MASK_SFT (0x1f << 9)
+#define PCM0_SYNC_TYPE_SFT 8
+#define PCM0_SYNC_TYPE_MASK 0x1
+#define PCM0_SYNC_TYPE_MASK_SFT (0x1 << 8)
+#define PCM0_BYP_ASRC_SFT 7
+#define PCM0_BYP_ASRC_MASK 0x1
+#define PCM0_BYP_ASRC_MASK_SFT (0x1 << 7)
+#define PCM0_SLAVE_SFT 6
+#define PCM0_SLAVE_MASK 0x1
+#define PCM0_SLAVE_MASK_SFT (0x1 << 6)
+#define PCM0_MODE_SFT 3
+#define PCM0_MODE_MASK 0x7
+#define PCM0_MODE_MASK_SFT (0x7 << 3)
+#define PCM0_FMT_SFT 1
+#define PCM0_FMT_MASK 0x3
+#define PCM0_FMT_MASK_SFT (0x3 << 1)
+#define PCM0_EN_SFT 0
+#define PCM0_EN_MASK 0x1
+#define PCM0_EN_MASK_SFT (0x1 << 0)
+
+/* AFE_PCM0_INTF_CON1 */
+#define PCM0_TX_RX_LOOPBACK_SFT 31
+#define PCM0_TX_RX_LOOPBACK_MASK 0x1
+#define PCM0_TX_RX_LOOPBACK_MASK_SFT (0x1 << 31)
+#define PCM0_BUFFER_LOOPBACK_SFT 30
+#define PCM0_BUFFER_LOOPBACK_MASK 0x1
+#define PCM0_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
+#define PCM0_PARALLEL_LOOPBACK_SFT 29
+#define PCM0_PARALLEL_LOOPBACK_MASK 0x1
+#define PCM0_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
+#define PCM0_SERIAL_LOOPBACK_SFT 28
+#define PCM0_SERIAL_LOOPBACK_MASK 0x1
+#define PCM0_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
+#define PCM0_DAI_LOOPBACK_SFT 27
+#define PCM0_DAI_LOOPBACK_MASK 0x1
+#define PCM0_DAI_LOOPBACK_MASK_SFT (0x1 << 27)
+#define PCM0_I2S_LOOPBACK_SFT 26
+#define PCM0_I2S_LOOPBACK_MASK 0x1
+#define PCM0_I2S_LOOPBACK_MASK_SFT (0x1 << 26)
+#define PCM0_1X_EN_DOMAIN_SFT 23
+#define PCM0_1X_EN_DOMAIN_MASK 0x7
+#define PCM0_1X_EN_DOMAIN_MASK_SFT (0x7 << 23)
+#define PCM0_1X_EN_MODE_SFT 18
+#define PCM0_1X_EN_MODE_MASK 0x1f
+#define PCM0_1X_EN_MODE_MASK_SFT (0x1f << 18)
+#define PCM0_TX3_RCH_DBG_MODE_SFT 17
+#define PCM0_TX3_RCH_DBG_MODE_MASK 0x1
+#define PCM0_TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)
+#define PCM0_PCM1_LOOPBACK_SFT 16
+#define PCM0_PCM1_LOOPBACK_MASK 0x1
+#define PCM0_PCM1_LOOPBACK_MASK_SFT (0x1 << 16)
+#define PCM0_LOOPBACK_CH_SEL_SFT 12
+#define PCM0_LOOPBACK_CH_SEL_MASK 0x3
+#define PCM0_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 12)
+#define PCM0_BT_MODE_SFT 11
+#define PCM0_BT_MODE_MASK 0x1
+#define PCM0_BT_MODE_MASK_SFT (0x1 << 11)
+#define PCM0_EXT_MODEM_SFT 10
+#define PCM0_EXT_MODEM_MASK 0x1
+#define PCM0_EXT_MODEM_MASK_SFT (0x1 << 10)
+#define PCM0_USE_MD3_SFT 9
+#define PCM0_USE_MD3_MASK 0x1
+#define PCM0_USE_MD3_MASK_SFT (0x1 << 9)
+#define PCM0_FIX_VALUE_SEL_SFT 8
+#define PCM0_FIX_VALUE_SEL_MASK 0x1
+#define PCM0_FIX_VALUE_SEL_MASK_SFT (0x1 << 8)
+#define PCM0_TX_FIX_VALUE_SFT 0
+#define PCM0_TX_FIX_VALUE_MASK 0xff
+#define PCM0_TX_FIX_VALUE_MASK_SFT (0xff << 0)
+
+/* AFE_PCM_INTF_MON */
+#define PCM0_TX_FIFO_OV_SFT 5
+#define PCM0_TX_FIFO_OV_MASK 0x1
+#define PCM0_TX_FIFO_OV_MASK_SFT (0x1 << 5)
+#define PCM0_RX_FIFO_OV_SFT 4
+#define PCM0_RX_FIFO_OV_MASK 0x1
+#define PCM0_RX_FIFO_OV_MASK_SFT (0x1 << 4)
+#define PCM1_TX_FIFO_OV_SFT 3
+#define PCM1_TX_FIFO_OV_MASK 0x1
+#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 3)
+#define PCM1_RX_FIFO_OV_SFT 2
+#define PCM1_RX_FIFO_OV_MASK 0x1
+#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 2)
+#define PCM0_SYNC_GLITCH_SFT 1
+#define PCM0_SYNC_GLITCH_MASK 0x1
+#define PCM0_SYNC_GLITCH_MASK_SFT (0x1 << 1)
+#define PCM1_SYNC_GLITCH_SFT 0
+#define PCM1_SYNC_GLITCH_MASK 0x1
+#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 0)
+
+/* AFE_PCM_TOP_IP_VERSION */
+#define AFE_PCM_TOP_IP_VERSION_SFT 0
+#define AFE_PCM_TOP_IP_VERSION_MASK 0xffffffff
+#define AFE_PCM_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_EN */
+#define AFE_IRQ_MCU_EN_SFT 0
+#define AFE_IRQ_MCU_EN_MASK 0xffffffff
+#define AFE_IRQ_MCU_EN_MASK_SFT (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_DSP_EN */
+#define AFE_IRQ_DSP_EN_SFT 0
+#define AFE_IRQ_DSP_EN_MASK 0xffffffff
+#define AFE_IRQ_DSP_EN_MASK_SFT (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_DSP2_EN */
+#define AFE_IRQ_DSP2_EN_SFT 0
+#define AFE_IRQ_DSP2_EN_MASK 0xffffffff
+#define AFE_IRQ_DSP2_EN_MASK_SFT (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_SCP_EN */
+#define IRQ31_MCU_SCP_EN_SFT 31
+#define IRQ30_MCU_SCP_EN_SFT 30
+#define IRQ29_MCU_SCP_EN_SFT 29
+#define IRQ28_MCU_SCP_EN_SFT 28
+#define IRQ27_MCU_SCP_EN_SFT 27
+#define IRQ26_MCU_SCP_EN_SFT 26
+#define IRQ25_MCU_SCP_EN_SFT 25
+#define IRQ24_MCU_SCP_EN_SFT 24
+#define IRQ23_MCU_SCP_EN_SFT 23
+#define IRQ22_MCU_SCP_EN_SFT 22
+#define IRQ21_MCU_SCP_EN_SFT 21
+#define IRQ20_MCU_SCP_EN_SFT 20
+#define IRQ19_MCU_SCP_EN_SFT 19
+#define IRQ18_MCU_SCP_EN_SFT 18
+#define IRQ17_MCU_SCP_EN_SFT 17
+#define IRQ16_MCU_SCP_EN_SFT 16
+#define IRQ15_MCU_SCP_EN_SFT 15
+#define IRQ14_MCU_SCP_EN_SFT 14
+#define IRQ13_MCU_SCP_EN_SFT 13
+#define IRQ12_MCU_SCP_EN_SFT 12
+#define IRQ11_MCU_SCP_EN_SFT 11
+#define IRQ10_MCU_SCP_EN_SFT 10
+#define IRQ9_MCU_SCP_EN_SFT 9
+#define IRQ8_MCU_SCP_EN_SFT 8
+#define IRQ7_MCU_SCP_EN_SFT 7
+#define IRQ6_MCU_SCP_EN_SFT 6
+#define IRQ5_MCU_SCP_EN_SFT 5
+#define IRQ4_MCU_SCP_EN_SFT 4
+#define IRQ3_MCU_SCP_EN_SFT 3
+#define IRQ2_MCU_SCP_EN_SFT 2
+#define IRQ1_MCU_SCP_EN_SFT 1
+#define IRQ0_MCU_SCP_EN_SFT 0
+
+/* AFE_CUSTOM_IRQ_MCU_EN */
+#define AFE_CUSTOM_IRQ_MCU_EN_SFT 0
+#define AFE_CUSTOM_IRQ_MCU_EN_MASK 0xffffffff
+#define AFE_CUSTOM_IRQ_MCU_EN_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CUSTOM_IRQ_MCU_DSP_EN */
+#define AFE_CUSTOM_IRQ_DSP_EN_SFT 0
+#define AFE_CUSTOM_IRQ_DSP_EN_MASK 0xffffffff
+#define AFE_CUSTOM_IRQ_DSP_EN_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CUSTOM_IRQ_MCU_DSP2_EN */
+#define AFE_CUSTOM_IRQ_DSP2_EN_SFT 0
+#define AFE_CUSTOM_IRQ_DSP2_EN_MASK 0xffffffff
+#define AFE_CUSTOM_IRQ_DSP2_EN_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CUSTOM_IRQ_MCU_SCP_EN */
+#define AFE_CUSTOM_IRQ_SCP_EN_SFT 0
+#define AFE_CUSTOM_IRQ_SCP_EN_MASK 0xffffffff
+#define AFE_CUSTOM_IRQ_SCP_EN_MASK_SFT (0xffffffff << 0)
+
+/* AFE_IRQ_MCU_STATUS */
+#define IRQ26_MCU_SFT 26
+#define IRQ26_MCU_MASK 0x1
+#define IRQ26_MCU_MASK_SFT (0x1 << 26)
+#define IRQ25_MCU_SFT 25
+#define IRQ25_MCU_MASK 0x1
+#define IRQ25_MCU_MASK_SFT (0x1 << 25)
+#define IRQ24_MCU_SFT 24
+#define IRQ24_MCU_MASK 0x1
+#define IRQ24_MCU_MASK_SFT (0x1 << 24)
+#define IRQ23_MCU_SFT 23
+#define IRQ23_MCU_MASK 0x1
+#define IRQ23_MCU_MASK_SFT (0x1 << 23)
+#define IRQ22_MCU_SFT 22
+#define IRQ22_MCU_MASK 0x1
+#define IRQ22_MCU_MASK_SFT (0x1 << 22)
+#define IRQ21_MCU_SFT 21
+#define IRQ21_MCU_MASK 0x1
+#define IRQ21_MCU_MASK_SFT (0x1 << 21)
+#define IRQ20_MCU_SFT 20
+#define IRQ20_MCU_MASK 0x1
+#define IRQ20_MCU_MASK_SFT (0x1 << 20)
+#define IRQ19_MCU_SFT 19
+#define IRQ19_MCU_MASK 0x1
+#define IRQ19_MCU_MASK_SFT (0x1 << 19)
+#define IRQ18_MCU_SFT 18
+#define IRQ18_MCU_MASK 0x1
+#define IRQ18_MCU_MASK_SFT (0x1 << 18)
+#define IRQ17_MCU_SFT 17
+#define IRQ17_MCU_MASK 0x1
+#define IRQ17_MCU_MASK_SFT (0x1 << 17)
+#define IRQ16_MCU_SFT 16
+#define IRQ16_MCU_MASK 0x1
+#define IRQ16_MCU_MASK_SFT (0x1 << 16)
+#define IRQ15_MCU_SFT 15
+#define IRQ15_MCU_MASK 0x1
+#define IRQ15_MCU_MASK_SFT (0x1 << 15)
+#define IRQ14_MCU_SFT 14
+#define IRQ14_MCU_MASK 0x1
+#define IRQ14_MCU_MASK_SFT (0x1 << 14)
+#define IRQ13_MCU_SFT 13
+#define IRQ13_MCU_MASK 0x1
+#define IRQ13_MCU_MASK_SFT (0x1 << 13)
+#define IRQ12_MCU_SFT 12
+#define IRQ12_MCU_MASK 0x1
+#define IRQ12_MCU_MASK_SFT (0x1 << 12)
+#define IRQ11_MCU_SFT 11
+#define IRQ11_MCU_MASK 0x1
+#define IRQ11_MCU_MASK_SFT (0x1 << 11)
+#define IRQ10_MCU_SFT 10
+#define IRQ10_MCU_MASK 0x1
+#define IRQ10_MCU_MASK_SFT (0x1 << 10)
+#define IRQ9_MCU_SFT 9
+#define IRQ9_MCU_MASK 0x1
+#define IRQ9_MCU_MASK_SFT (0x1 << 9)
+#define IRQ8_MCU_SFT 8
+#define IRQ8_MCU_MASK 0x1
+#define IRQ8_MCU_MASK_SFT (0x1 << 8)
+#define IRQ7_MCU_SFT 7
+#define IRQ7_MCU_MASK 0x1
+#define IRQ7_MCU_MASK_SFT (0x1 << 7)
+#define IRQ6_MCU_SFT 6
+#define IRQ6_MCU_MASK 0x1
+#define IRQ6_MCU_MASK_SFT (0x1 << 6)
+#define IRQ5_MCU_SFT 5
+#define IRQ5_MCU_MASK 0x1
+#define IRQ5_MCU_MASK_SFT (0x1 << 5)
+#define IRQ4_MCU_SFT 4
+#define IRQ4_MCU_MASK 0x1
+#define IRQ4_MCU_MASK_SFT (0x1 << 4)
+#define IRQ3_MCU_SFT 3
+#define IRQ3_MCU_MASK 0x1
+#define IRQ3_MCU_MASK_SFT (0x1 << 3)
+#define IRQ2_MCU_SFT 2
+#define IRQ2_MCU_MASK 0x1
+#define IRQ2_MCU_MASK_SFT (0x1 << 2)
+#define IRQ1_MCU_SFT 1
+#define IRQ1_MCU_MASK 0x1
+#define IRQ1_MCU_MASK_SFT (0x1 << 1)
+#define IRQ0_MCU_SFT 0
+#define IRQ0_MCU_MASK 0x1
+#define IRQ0_MCU_MASK_SFT (0x1 << 0)
+
+/* AFE_CUSTOM_IRQ_MCU_STATUS */
+#define CUSTOM_IRQ21_MCU_SFT 21
+#define CUSTOM_IRQ21_MCU_MASK 0x1
+#define CUSTOM_IRQ21_MCU_MASK_SFT (0x1 << 21)
+#define CUSTOM_IRQ20_MCU_SFT 20
+#define CUSTOM_IRQ20_MCU_MASK 0x1
+#define CUSTOM_IRQ20_MCU_MASK_SFT (0x1 << 20)
+#define CUSTOM_IRQ19_MCU_SFT 19
+#define CUSTOM_IRQ19_MCU_MASK 0x1
+#define CUSTOM_IRQ19_MCU_MASK_SFT (0x1 << 19)
+#define CUSTOM_IRQ18_MCU_SFT 18
+#define CUSTOM_IRQ18_MCU_MASK 0x1
+#define CUSTOM_IRQ18_MCU_MASK_SFT (0x1 << 18)
+#define CUSTOM_IRQ17_MCU_SFT 17
+#define CUSTOM_IRQ17_MCU_MASK 0x1
+#define CUSTOM_IRQ17_MCU_MASK_SFT (0x1 << 17)
+#define CUSTOM_IRQ16_MCU_SFT 16
+#define CUSTOM_IRQ16_MCU_MASK 0x1
+#define CUSTOM_IRQ16_MCU_MASK_SFT (0x1 << 16)
+#define CUSTOM_IRQ9_MCU_SFT 9
+#define CUSTOM_IRQ9_MCU_MASK 0x1
+#define CUSTOM_IRQ9_MCU_MASK_SFT (0x1 << 9)
+#define CUSTOM_IRQ8_MCU_SFT 8
+#define CUSTOM_IRQ8_MCU_MASK 0x1
+#define CUSTOM_IRQ8_MCU_MASK_SFT (0x1 << 8)
+#define CUSTOM_IRQ7_MCU_SFT 7
+#define CUSTOM_IRQ7_MCU_MASK 0x1
+#define CUSTOM_IRQ7_MCU_MASK_SFT (0x1 << 7)
+#define CUSTOM_IRQ6_MCU_SFT 6
+#define CUSTOM_IRQ6_MCU_MASK 0x1
+#define CUSTOM_IRQ6_MCU_MASK_SFT (0x1 << 6)
+#define CUSTOM_IRQ5_MCU_SFT 5
+#define CUSTOM_IRQ5_MCU_MASK 0x1
+#define CUSTOM_IRQ5_MCU_MASK_SFT (0x1 << 5)
+#define CUSTOM_IRQ4_MCU_SFT 4
+#define CUSTOM_IRQ4_MCU_MASK 0x1
+#define CUSTOM_IRQ4_MCU_MASK_SFT (0x1 << 4)
+#define CUSTOM_IRQ3_MCU_SFT 3
+#define CUSTOM_IRQ3_MCU_MASK 0x1
+#define CUSTOM_IRQ3_MCU_MASK_SFT (0x1 << 3)
+#define CUSTOM_IRQ2_MCU_SFT 2
+#define CUSTOM_IRQ2_MCU_MASK 0x1
+#define CUSTOM_IRQ2_MCU_MASK_SFT (0x1 << 2)
+#define CUSTOM_IRQ1_MCU_SFT 1
+#define CUSTOM_IRQ1_MCU_MASK 0x1
+#define CUSTOM_IRQ1_MCU_MASK_SFT (0x1 << 1)
+#define CUSTOM_IRQ0_MCU_SFT 0
+#define CUSTOM_IRQ0_MCU_MASK 0x1
+#define CUSTOM_IRQ0_MCU_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ_MCU_CFG */
+#define AFE_IRQ_CLR_CFG_SFT 31
+#define AFE_IRQ_CLR_CFG_MASK 0x1
+#define AFE_IRQ_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ_MCU_CNT_SFT 0
+#define AFE_IRQ_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ0_MCU_CFG0 */
+#define AFE_IRQ0_MCU_DOMAIN_SFT 9
+#define AFE_IRQ0_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ0_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ0_MCU_FS_SFT 4
+#define AFE_IRQ0_MCU_FS_MASK 0x1f
+#define AFE_IRQ0_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ0_MCU_ON_SFT 0
+#define AFE_IRQ0_MCU_ON_MASK 0x1
+#define AFE_IRQ0_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ0_MCU_CFG1 */
+#define AFE_IRQ0_CLR_CFG_SFT 31
+#define AFE_IRQ0_CLR_CFG_MASK 0x1
+#define AFE_IRQ0_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ0_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ0_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ0_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ0_MCU_CNT_SFT 0
+#define AFE_IRQ0_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ0_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ1_MCU_CFG0 */
+#define AFE_IRQ1_MCU_DOMAIN_SFT 9
+#define AFE_IRQ1_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ1_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ1_MCU_FS_SFT 4
+#define AFE_IRQ1_MCU_FS_MASK 0x1f
+#define AFE_IRQ1_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ1_MCU_ON_SFT 0
+#define AFE_IRQ1_MCU_ON_MASK 0x1
+#define AFE_IRQ1_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ1_MCU_CFG1 */
+#define AFE_IRQ1_CLR_CFG_SFT 31
+#define AFE_IRQ1_CLR_CFG_MASK 0x1
+#define AFE_IRQ1_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ1_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ1_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ1_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ1_MCU_CNT_SFT 0
+#define AFE_IRQ1_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ1_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ2_MCU_CFG0 */
+#define AFE_IRQ2_MCU_DOMAIN_SFT 9
+#define AFE_IRQ2_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ2_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ2_MCU_FS_SFT 4
+#define AFE_IRQ2_MCU_FS_MASK 0x1f
+#define AFE_IRQ2_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ2_MCU_ON_SFT 0
+#define AFE_IRQ2_MCU_ON_MASK 0x1
+#define AFE_IRQ2_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ2_MCU_CFG1 */
+#define AFE_IRQ2_CLR_CFG_SFT 31
+#define AFE_IRQ2_CLR_CFG_MASK 0x1
+#define AFE_IRQ2_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ2_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ2_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ2_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ2_MCU_CNT_SFT 0
+#define AFE_IRQ2_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ2_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ3_MCU_CFG0 */
+#define AFE_IRQ3_MCU_DOMAIN_SFT 9
+#define AFE_IRQ3_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ3_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ3_MCU_FS_SFT 4
+#define AFE_IRQ3_MCU_FS_MASK 0x1f
+#define AFE_IRQ3_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ3_MCU_ON_SFT 0
+#define AFE_IRQ3_MCU_ON_MASK 0x1
+#define AFE_IRQ3_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ3_MCU_CFG1 */
+#define AFE_IRQ3_CLR_CFG_SFT 31
+#define AFE_IRQ3_CLR_CFG_MASK 0x1
+#define AFE_IRQ3_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ3_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ3_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ3_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ3_MCU_CNT_SFT 0
+#define AFE_IRQ3_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ3_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ4_MCU_CFG0 */
+#define AFE_IRQ4_MCU_DOMAIN_SFT 9
+#define AFE_IRQ4_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ4_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ4_MCU_FS_SFT 4
+#define AFE_IRQ4_MCU_FS_MASK 0x1f
+#define AFE_IRQ4_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ4_MCU_ON_SFT 0
+#define AFE_IRQ4_MCU_ON_MASK 0x1
+#define AFE_IRQ4_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ4_MCU_CFG1 */
+#define AFE_IRQ4_CLR_CFG_SFT 31
+#define AFE_IRQ4_CLR_CFG_MASK 0x1
+#define AFE_IRQ4_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ4_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ4_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ4_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ4_MCU_CNT_SFT 0
+#define AFE_IRQ4_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ4_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ5_MCU_CFG0 */
+#define AFE_IRQ5_MCU_DOMAIN_SFT 9
+#define AFE_IRQ5_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ5_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ5_MCU_FS_SFT 4
+#define AFE_IRQ5_MCU_FS_MASK 0x1f
+#define AFE_IRQ5_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ5_MCU_ON_SFT 0
+#define AFE_IRQ5_MCU_ON_MASK 0x1
+#define AFE_IRQ5_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ5_MCU_CFG1 */
+#define AFE_IRQ5_CLR_CFG_SFT 31
+#define AFE_IRQ5_CLR_CFG_MASK 0x1
+#define AFE_IRQ5_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ5_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ5_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ5_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ5_MCU_CNT_SFT 0
+#define AFE_IRQ5_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ5_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ6_MCU_CFG0 */
+#define AFE_IRQ6_MCU_DOMAIN_SFT 9
+#define AFE_IRQ6_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ6_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ6_MCU_FS_SFT 4
+#define AFE_IRQ6_MCU_FS_MASK 0x1f
+#define AFE_IRQ6_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ6_MCU_ON_SFT 0
+#define AFE_IRQ6_MCU_ON_MASK 0x1
+#define AFE_IRQ6_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ6_MCU_CFG1 */
+#define AFE_IRQ6_CLR_CFG_SFT 31
+#define AFE_IRQ6_CLR_CFG_MASK 0x1
+#define AFE_IRQ6_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ6_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ6_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ6_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ6_MCU_CNT_SFT 0
+#define AFE_IRQ6_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ6_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ7_MCU_CFG0 */
+#define AFE_IRQ7_MCU_DOMAIN_SFT 9
+#define AFE_IRQ7_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ7_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ7_MCU_FS_SFT 4
+#define AFE_IRQ7_MCU_FS_MASK 0x1f
+#define AFE_IRQ7_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ7_MCU_ON_SFT 0
+#define AFE_IRQ7_MCU_ON_MASK 0x1
+#define AFE_IRQ7_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ7_MCU_CFG1 */
+#define AFE_IRQ7_CLR_CFG_SFT 31
+#define AFE_IRQ7_CLR_CFG_MASK 0x1
+#define AFE_IRQ7_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ7_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ7_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ7_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ7_MCU_CNT_SFT 0
+#define AFE_IRQ7_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ7_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ8_MCU_CFG0 */
+#define AFE_IRQ8_MCU_DOMAIN_SFT 9
+#define AFE_IRQ8_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ8_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ8_MCU_FS_SFT 4
+#define AFE_IRQ8_MCU_FS_MASK 0x1f
+#define AFE_IRQ8_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ8_MCU_ON_SFT 0
+#define AFE_IRQ8_MCU_ON_MASK 0x1
+#define AFE_IRQ8_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ8_MCU_CFG1 */
+#define AFE_IRQ8_CLR_CFG_SFT 31
+#define AFE_IRQ8_CLR_CFG_MASK 0x1
+#define AFE_IRQ8_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ8_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ8_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ8_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ8_MCU_CNT_SFT 0
+#define AFE_IRQ8_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ8_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ9_MCU_CFG0 */
+#define AFE_IRQ9_MCU_DOMAIN_SFT 9
+#define AFE_IRQ9_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ9_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ9_MCU_FS_SFT 4
+#define AFE_IRQ9_MCU_FS_MASK 0x1f
+#define AFE_IRQ9_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ9_MCU_ON_SFT 0
+#define AFE_IRQ9_MCU_ON_MASK 0x1
+#define AFE_IRQ9_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ9_MCU_CFG1 */
+#define AFE_IRQ9_CLR_CFG_SFT 31
+#define AFE_IRQ9_CLR_CFG_MASK 0x1
+#define AFE_IRQ9_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ9_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ9_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ9_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ9_MCU_CNT_SFT 0
+#define AFE_IRQ9_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ9_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ10_MCU_CFG0 */
+#define AFE_IRQ10_MCU_DOMAIN_SFT 9
+#define AFE_IRQ10_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ10_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ10_MCU_FS_SFT 4
+#define AFE_IRQ10_MCU_FS_MASK 0x1f
+#define AFE_IRQ10_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ10_MCU_ON_SFT 0
+#define AFE_IRQ10_MCU_ON_MASK 0x1
+#define AFE_IRQ10_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ10_MCU_CFG1 */
+#define AFE_IRQ10_CLR_CFG_SFT 31
+#define AFE_IRQ10_CLR_CFG_MASK 0x1
+#define AFE_IRQ10_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ10_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ10_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ10_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ10_MCU_CNT_SFT 0
+#define AFE_IRQ10_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ10_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ11_MCU_CFG0 */
+#define AFE_IRQ11_MCU_DOMAIN_SFT 9
+#define AFE_IRQ11_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ11_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ11_MCU_FS_SFT 4
+#define AFE_IRQ11_MCU_FS_MASK 0x1f
+#define AFE_IRQ11_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ11_MCU_ON_SFT 0
+#define AFE_IRQ11_MCU_ON_MASK 0x1
+#define AFE_IRQ11_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ11_MCU_CFG1 */
+#define AFE_IRQ11_CLR_CFG_SFT 31
+#define AFE_IRQ11_CLR_CFG_MASK 0x1
+#define AFE_IRQ11_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ11_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ11_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ11_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ11_MCU_CNT_SFT 0
+#define AFE_IRQ11_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ11_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ12_MCU_CFG0 */
+#define AFE_IRQ12_MCU_DOMAIN_SFT 9
+#define AFE_IRQ12_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ12_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ12_MCU_FS_SFT 4
+#define AFE_IRQ12_MCU_FS_MASK 0x1f
+#define AFE_IRQ12_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ12_MCU_ON_SFT 0
+#define AFE_IRQ12_MCU_ON_MASK 0x1
+#define AFE_IRQ12_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ12_MCU_CFG1 */
+#define AFE_IRQ12_CLR_CFG_SFT 31
+#define AFE_IRQ12_CLR_CFG_MASK 0x1
+#define AFE_IRQ12_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ12_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ12_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ12_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ12_MCU_CNT_SFT 0
+#define AFE_IRQ12_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ12_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ13_MCU_CFG0 */
+#define AFE_IRQ13_MCU_DOMAIN_SFT 9
+#define AFE_IRQ13_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ13_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ13_MCU_FS_SFT 4
+#define AFE_IRQ13_MCU_FS_MASK 0x1f
+#define AFE_IRQ13_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ13_MCU_ON_SFT 0
+#define AFE_IRQ13_MCU_ON_MASK 0x1
+#define AFE_IRQ13_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ13_MCU_CFG1 */
+#define AFE_IRQ13_CLR_CFG_SFT 31
+#define AFE_IRQ13_CLR_CFG_MASK 0x1
+#define AFE_IRQ13_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ13_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ13_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ13_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ13_MCU_CNT_SFT 0
+#define AFE_IRQ13_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ13_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ14_MCU_CFG0 */
+#define AFE_IRQ14_MCU_DOMAIN_SFT 9
+#define AFE_IRQ14_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ14_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ14_MCU_FS_SFT 4
+#define AFE_IRQ14_MCU_FS_MASK 0x1f
+#define AFE_IRQ14_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ14_MCU_ON_SFT 0
+#define AFE_IRQ14_MCU_ON_MASK 0x1
+#define AFE_IRQ14_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ14_MCU_CFG1 */
+#define AFE_IRQ14_CLR_CFG_SFT 31
+#define AFE_IRQ14_CLR_CFG_MASK 0x1
+#define AFE_IRQ14_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ14_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ14_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ14_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ14_MCU_CNT_SFT 0
+#define AFE_IRQ14_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ14_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ15_MCU_CFG0 */
+#define AFE_IRQ15_MCU_DOMAIN_SFT 9
+#define AFE_IRQ15_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ15_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ15_MCU_FS_SFT 4
+#define AFE_IRQ15_MCU_FS_MASK 0x1f
+#define AFE_IRQ15_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ15_MCU_ON_SFT 0
+#define AFE_IRQ15_MCU_ON_MASK 0x1
+#define AFE_IRQ15_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ15_MCU_CFG1 */
+#define AFE_IRQ15_CLR_CFG_SFT 31
+#define AFE_IRQ15_CLR_CFG_MASK 0x1
+#define AFE_IRQ15_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ15_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ15_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ15_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ15_MCU_CNT_SFT 0
+#define AFE_IRQ15_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ15_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ16_MCU_CFG0 */
+#define AFE_IRQ16_MCU_DOMAIN_SFT 9
+#define AFE_IRQ16_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ16_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ16_MCU_FS_SFT 4
+#define AFE_IRQ16_MCU_FS_MASK 0x1f
+#define AFE_IRQ16_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ16_MCU_ON_SFT 0
+#define AFE_IRQ16_MCU_ON_MASK 0x1
+#define AFE_IRQ16_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ16_MCU_CFG1 */
+#define AFE_IRQ16_CLR_CFG_SFT 31
+#define AFE_IRQ16_CLR_CFG_MASK 0x1
+#define AFE_IRQ16_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ16_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ16_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ16_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ16_MCU_CNT_SFT 0
+#define AFE_IRQ16_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ16_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ17_MCU_CFG0 */
+#define AFE_IRQ17_MCU_DOMAIN_SFT 9
+#define AFE_IRQ17_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ17_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ17_MCU_FS_SFT 4
+#define AFE_IRQ17_MCU_FS_MASK 0x1f
+#define AFE_IRQ17_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ17_MCU_ON_SFT 0
+#define AFE_IRQ17_MCU_ON_MASK 0x1
+#define AFE_IRQ17_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ17_MCU_CFG1 */
+#define AFE_IRQ17_CLR_CFG_SFT 31
+#define AFE_IRQ17_CLR_CFG_MASK 0x1
+#define AFE_IRQ17_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ17_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ17_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ17_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ17_MCU_CNT_SFT 0
+#define AFE_IRQ17_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ17_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ18_MCU_CFG0 */
+#define AFE_IRQ18_MCU_DOMAIN_SFT 9
+#define AFE_IRQ18_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ18_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ18_MCU_FS_SFT 4
+#define AFE_IRQ18_MCU_FS_MASK 0x1f
+#define AFE_IRQ18_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ18_MCU_ON_SFT 0
+#define AFE_IRQ18_MCU_ON_MASK 0x1
+#define AFE_IRQ18_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ18_MCU_CFG1 */
+#define AFE_IRQ18_CLR_CFG_SFT 31
+#define AFE_IRQ18_CLR_CFG_MASK 0x1
+#define AFE_IRQ18_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ18_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ18_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ18_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ18_MCU_CNT_SFT 0
+#define AFE_IRQ18_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ18_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ19_MCU_CFG0 */
+#define AFE_IRQ19_MCU_DOMAIN_SFT 9
+#define AFE_IRQ19_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ19_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ19_MCU_FS_SFT 4
+#define AFE_IRQ19_MCU_FS_MASK 0x1f
+#define AFE_IRQ19_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ19_MCU_ON_SFT 0
+#define AFE_IRQ19_MCU_ON_MASK 0x1
+#define AFE_IRQ19_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ19_MCU_CFG1 */
+#define AFE_IRQ19_CLR_CFG_SFT 31
+#define AFE_IRQ19_CLR_CFG_MASK 0x1
+#define AFE_IRQ19_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ19_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ19_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ19_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ19_MCU_CNT_SFT 0
+#define AFE_IRQ19_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ19_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ20_MCU_CFG0 */
+#define AFE_IRQ20_MCU_DOMAIN_SFT 9
+#define AFE_IRQ20_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ20_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ20_MCU_FS_SFT 4
+#define AFE_IRQ20_MCU_FS_MASK 0x1f
+#define AFE_IRQ20_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ20_MCU_ON_SFT 0
+#define AFE_IRQ20_MCU_ON_MASK 0x1
+#define AFE_IRQ20_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ20_MCU_CFG1 */
+#define AFE_IRQ20_CLR_CFG_SFT 31
+#define AFE_IRQ20_CLR_CFG_MASK 0x1
+#define AFE_IRQ20_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ20_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ20_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ20_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ20_MCU_CNT_SFT 0
+#define AFE_IRQ20_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ20_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ21_MCU_CFG0 */
+#define AFE_IRQ21_MCU_DOMAIN_SFT 9
+#define AFE_IRQ21_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ21_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ21_MCU_FS_SFT 4
+#define AFE_IRQ21_MCU_FS_MASK 0x1f
+#define AFE_IRQ21_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ21_MCU_ON_SFT 0
+#define AFE_IRQ21_MCU_ON_MASK 0x1
+#define AFE_IRQ21_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ21_MCU_CFG1 */
+#define AFE_IRQ21_CLR_CFG_SFT 31
+#define AFE_IRQ21_CLR_CFG_MASK 0x1
+#define AFE_IRQ21_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ21_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ21_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ21_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ21_MCU_CNT_SFT 0
+#define AFE_IRQ21_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ21_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ22_MCU_CFG0 */
+#define AFE_IRQ22_MCU_DOMAIN_SFT 9
+#define AFE_IRQ22_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ22_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ22_MCU_FS_SFT 4
+#define AFE_IRQ22_MCU_FS_MASK 0x1f
+#define AFE_IRQ22_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ22_MCU_ON_SFT 0
+#define AFE_IRQ22_MCU_ON_MASK 0x1
+#define AFE_IRQ22_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ22_MCU_CFG1 */
+#define AFE_IRQ22_CLR_CFG_SFT 31
+#define AFE_IRQ22_CLR_CFG_MASK 0x1
+#define AFE_IRQ22_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ22_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ22_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ22_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ22_MCU_CNT_SFT 0
+#define AFE_IRQ22_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ22_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ23_MCU_CFG0 */
+#define AFE_IRQ23_MCU_DOMAIN_SFT 9
+#define AFE_IRQ23_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ23_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ23_MCU_FS_SFT 4
+#define AFE_IRQ23_MCU_FS_MASK 0x1f
+#define AFE_IRQ23_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ23_MCU_ON_SFT 0
+#define AFE_IRQ23_MCU_ON_MASK 0x1
+#define AFE_IRQ23_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ23_MCU_CFG1 */
+#define AFE_IRQ23_CLR_CFG_SFT 31
+#define AFE_IRQ23_CLR_CFG_MASK 0x1
+#define AFE_IRQ23_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ23_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ23_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ23_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ23_MCU_CNT_SFT 0
+#define AFE_IRQ23_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ23_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ24_MCU_CFG0 */
+#define AFE_IRQ24_MCU_DOMAIN_SFT 9
+#define AFE_IRQ24_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ24_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ24_MCU_FS_SFT 4
+#define AFE_IRQ24_MCU_FS_MASK 0x1f
+#define AFE_IRQ24_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ24_MCU_ON_SFT 0
+#define AFE_IRQ24_MCU_ON_MASK 0x1
+#define AFE_IRQ24_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ24_MCU_CFG1 */
+#define AFE_IRQ24_CLR_CFG_SFT 31
+#define AFE_IRQ24_CLR_CFG_MASK 0x1
+#define AFE_IRQ24_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ24_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ24_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ24_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ24_MCU_CNT_SFT 0
+#define AFE_IRQ24_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ24_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ25_MCU_CFG0 */
+#define AFE_IRQ25_MCU_DOMAIN_SFT 9
+#define AFE_IRQ25_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ25_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ25_MCU_FS_SFT 4
+#define AFE_IRQ25_MCU_FS_MASK 0x1f
+#define AFE_IRQ25_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ25_MCU_ON_SFT 0
+#define AFE_IRQ25_MCU_ON_MASK 0x1
+#define AFE_IRQ25_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ25_MCU_CFG1 */
+#define AFE_IRQ25_CLR_CFG_SFT 31
+#define AFE_IRQ25_CLR_CFG_MASK 0x1
+#define AFE_IRQ25_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ25_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ25_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ25_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ25_MCU_CNT_SFT 0
+#define AFE_IRQ25_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ25_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ26_MCU_CFG0 */
+#define AFE_IRQ26_MCU_DOMAIN_SFT 9
+#define AFE_IRQ26_MCU_DOMAIN_MASK 0x7
+#define AFE_IRQ26_MCU_DOMAIN_MASK_SFT (0x7 << 9)
+#define AFE_IRQ26_MCU_FS_SFT 4
+#define AFE_IRQ26_MCU_FS_MASK 0x1f
+#define AFE_IRQ26_MCU_FS_MASK_SFT (0x1f << 4)
+#define AFE_IRQ26_MCU_ON_SFT 0
+#define AFE_IRQ26_MCU_ON_MASK 0x1
+#define AFE_IRQ26_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ26_MCU_CFG1 */
+#define AFE_IRQ26_CLR_CFG_SFT 31
+#define AFE_IRQ26_CLR_CFG_MASK 0x1
+#define AFE_IRQ26_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_IRQ26_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_IRQ26_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_IRQ26_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_IRQ26_MCU_CNT_SFT 0
+#define AFE_IRQ26_MCU_CNT_MASK 0xffffff
+#define AFE_IRQ26_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_CUSTOM_IRQ0_MCU_CFG0 */
+#define AFE_CUSTOM_IRQ0_MCU_ON_SFT 0
+#define AFE_CUSTOM_IRQ0_MCU_ON_MASK 0x1
+#define AFE_CUSTOM_IRQ0_MCU_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_CUSTOM_IRQ0_CNT_MON */
+#define AFE_CUSTOM_IRQ0_CNT_MON_SFT 0
+#define AFE_CUSTOM_IRQ0_CNT_MON_MASK 0xffffff
+#define AFE_CUSTOM_IRQ0_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_CUSTOM_IRQ0_MCU_CFG1 */
+#define AFE_CUSTOM_IRQ0_CLR_CFG_SFT 31
+#define AFE_CUSTOM_IRQ0_CLR_CFG_MASK 0x1
+#define AFE_CUSTOM_IRQ0_CLR_CFG_MASK_SFT (0x1 << 31)
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_SFT 30
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_MASK 0x1
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_CLR_CFG_MASK_SFT (0x1 << 30)
+#define AFE_CUSTOM_IRQ0_MCU_CNT_SFT 0
+#define AFE_CUSTOM_IRQ0_MCU_CNT_MASK 0xffffff
+#define AFE_CUSTOM_IRQ0_MCU_CNT_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ_MCU_MON0 */
+#define AFE_IRQ26_MISS_FLAG_SFT 26
+#define AFE_IRQ26_MISS_FLAG_MASK 0x1
+#define AFE_IRQ26_MISS_FLAG_MASK_SFT (0x1 << 26)
+#define AFE_IRQ25_MISS_FLAG_SFT 25
+#define AFE_IRQ25_MISS_FLAG_MASK 0x1
+#define AFE_IRQ25_MISS_FLAG_MASK_SFT (0x1 << 25)
+#define AFE_IRQ24_MISS_FLAG_SFT 24
+#define AFE_IRQ24_MISS_FLAG_MASK 0x1
+#define AFE_IRQ24_MISS_FLAG_MASK_SFT (0x1 << 24)
+#define AFE_IRQ23_MISS_FLAG_SFT 23
+#define AFE_IRQ23_MISS_FLAG_MASK 0x1
+#define AFE_IRQ23_MISS_FLAG_MASK_SFT (0x1 << 23)
+#define AFE_IRQ22_MISS_FLAG_SFT 22
+#define AFE_IRQ22_MISS_FLAG_MASK 0x1
+#define AFE_IRQ22_MISS_FLAG_MASK_SFT (0x1 << 22)
+#define AFE_IRQ21_MISS_FLAG_SFT 21
+#define AFE_IRQ21_MISS_FLAG_MASK 0x1
+#define AFE_IRQ21_MISS_FLAG_MASK_SFT (0x1 << 21)
+#define AFE_IRQ20_MISS_FLAG_SFT 20
+#define AFE_IRQ20_MISS_FLAG_MASK 0x1
+#define AFE_IRQ20_MISS_FLAG_MASK_SFT (0x1 << 20)
+#define AFE_IRQ19_MISS_FLAG_SFT 19
+#define AFE_IRQ19_MISS_FLAG_MASK 0x1
+#define AFE_IRQ19_MISS_FLAG_MASK_SFT (0x1 << 19)
+#define AFE_IRQ18_MISS_FLAG_SFT 18
+#define AFE_IRQ18_MISS_FLAG_MASK 0x1
+#define AFE_IRQ18_MISS_FLAG_MASK_SFT (0x1 << 18)
+#define AFE_IRQ17_MISS_FLAG_SFT 17
+#define AFE_IRQ17_MISS_FLAG_MASK 0x1
+#define AFE_IRQ17_MISS_FLAG_MASK_SFT (0x1 << 17)
+#define AFE_IRQ16_MISS_FLAG_SFT 16
+#define AFE_IRQ16_MISS_FLAG_MASK 0x1
+#define AFE_IRQ16_MISS_FLAG_MASK_SFT (0x1 << 16)
+#define AFE_IRQ15_MISS_FLAG_SFT 15
+#define AFE_IRQ15_MISS_FLAG_MASK 0x1
+#define AFE_IRQ15_MISS_FLAG_MASK_SFT (0x1 << 15)
+#define AFE_IRQ14_MISS_FLAG_SFT 14
+#define AFE_IRQ14_MISS_FLAG_MASK 0x1
+#define AFE_IRQ14_MISS_FLAG_MASK_SFT (0x1 << 14)
+#define AFE_IRQ13_MISS_FLAG_SFT 13
+#define AFE_IRQ13_MISS_FLAG_MASK 0x1
+#define AFE_IRQ13_MISS_FLAG_MASK_SFT (0x1 << 13)
+#define AFE_IRQ12_MISS_FLAG_SFT 12
+#define AFE_IRQ12_MISS_FLAG_MASK 0x1
+#define AFE_IRQ12_MISS_FLAG_MASK_SFT (0x1 << 12)
+#define AFE_IRQ11_MISS_FLAG_SFT 11
+#define AFE_IRQ11_MISS_FLAG_MASK 0x1
+#define AFE_IRQ11_MISS_FLAG_MASK_SFT (0x1 << 11)
+#define AFE_IRQ10_MISS_FLAG_SFT 10
+#define AFE_IRQ10_MISS_FLAG_MASK 0x1
+#define AFE_IRQ10_MISS_FLAG_MASK_SFT (0x1 << 10)
+#define AFE_IRQ9_MISS_FLAG_SFT 9
+#define AFE_IRQ9_MISS_FLAG_MASK 0x1
+#define AFE_IRQ9_MISS_FLAG_MASK_SFT (0x1 << 9)
+#define AFE_IRQ8_MISS_FLAG_SFT 8
+#define AFE_IRQ8_MISS_FLAG_MASK 0x1
+#define AFE_IRQ8_MISS_FLAG_MASK_SFT (0x1 << 8)
+#define AFE_IRQ7_MISS_FLAG_SFT 7
+#define AFE_IRQ7_MISS_FLAG_MASK 0x1
+#define AFE_IRQ7_MISS_FLAG_MASK_SFT (0x1 << 7)
+#define AFE_IRQ6_MISS_FLAG_SFT 6
+#define AFE_IRQ6_MISS_FLAG_MASK 0x1
+#define AFE_IRQ6_MISS_FLAG_MASK_SFT (0x1 << 6)
+#define AFE_IRQ5_MISS_FLAG_SFT 5
+#define AFE_IRQ5_MISS_FLAG_MASK 0x1
+#define AFE_IRQ5_MISS_FLAG_MASK_SFT (0x1 << 5)
+#define AFE_IRQ4_MISS_FLAG_SFT 4
+#define AFE_IRQ4_MISS_FLAG_MASK 0x1
+#define AFE_IRQ4_MISS_FLAG_MASK_SFT (0x1 << 4)
+#define AFE_IRQ3_MISS_FLAG_SFT 3
+#define AFE_IRQ3_MISS_FLAG_MASK 0x1
+#define AFE_IRQ3_MISS_FLAG_MASK_SFT (0x1 << 3)
+#define AFE_IRQ2_MISS_FLAG_SFT 2
+#define AFE_IRQ2_MISS_FLAG_MASK 0x1
+#define AFE_IRQ2_MISS_FLAG_MASK_SFT (0x1 << 2)
+#define AFE_IRQ1_MISS_FLAG_SFT 1
+#define AFE_IRQ1_MISS_FLAG_MASK 0x1
+#define AFE_IRQ1_MISS_FLAG_MASK_SFT (0x1 << 1)
+#define AFE_IRQ0_MISS_FLAG_SFT 0
+#define AFE_IRQ0_MISS_FLAG_MASK 0x1
+#define AFE_IRQ0_MISS_FLAG_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ_MCU_MON1 */
+#define AFE_CUSTOM_IRQ21_MISS_FLAG_SFT 21
+#define AFE_CUSTOM_IRQ21_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ21_MISS_FLAG_MASK_SFT (0x1 << 21)
+#define AFE_CUSTOM_IRQ20_MISS_FLAG_SFT 20
+#define AFE_CUSTOM_IRQ20_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ20_MISS_FLAG_MASK_SFT (0x1 << 20)
+#define AFE_CUSTOM_IRQ19_MISS_FLAG_SFT 19
+#define AFE_CUSTOM_IRQ19_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ19_MISS_FLAG_MASK_SFT (0x1 << 19)
+#define AFE_CUSTOM_IRQ18_MISS_FLAG_SFT 18
+#define AFE_CUSTOM_IRQ18_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ18_MISS_FLAG_MASK_SFT (0x1 << 18)
+#define AFE_CUSTOM_IRQ17_MISS_FLAG_SFT 17
+#define AFE_CUSTOM_IRQ17_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ17_MISS_FLAG_MASK_SFT (0x1 << 17)
+#define AFE_CUSTOM_IRQ16_MISS_FLAG_SFT 16
+#define AFE_CUSTOM_IRQ16_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ16_MISS_FLAG_MASK_SFT (0x1 << 16)
+#define AFE_CUSTOM_IRQ9_MISS_FLAG_SFT 9
+#define AFE_CUSTOM_IRQ9_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ9_MISS_FLAG_MASK_SFT (0x1 << 9)
+#define AFE_CUSTOM_IRQ8_MISS_FLAG_SFT 8
+#define AFE_CUSTOM_IRQ8_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ8_MISS_FLAG_MASK_SFT (0x1 << 8)
+#define AFE_CUSTOM_IRQ7_MISS_FLAG_SFT 7
+#define AFE_CUSTOM_IRQ7_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ7_MISS_FLAG_MASK_SFT (0x1 << 7)
+#define AFE_CUSTOM_IRQ6_MISS_FLAG_SFT 6
+#define AFE_CUSTOM_IRQ6_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ6_MISS_FLAG_MASK_SFT (0x1 << 6)
+#define AFE_CUSTOM_IRQ5_MISS_FLAG_SFT 5
+#define AFE_CUSTOM_IRQ5_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ5_MISS_FLAG_MASK_SFT (0x1 << 5)
+#define AFE_CUSTOM_IRQ4_MISS_FLAG_SFT 4
+#define AFE_CUSTOM_IRQ4_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ4_MISS_FLAG_MASK_SFT (0x1 << 4)
+#define AFE_CUSTOM_IRQ3_MISS_FLAG_SFT 3
+#define AFE_CUSTOM_IRQ3_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ3_MISS_FLAG_MASK_SFT (0x1 << 3)
+#define AFE_CUSTOM_IRQ2_MISS_FLAG_SFT 2
+#define AFE_CUSTOM_IRQ2_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ2_MISS_FLAG_MASK_SFT (0x1 << 2)
+#define AFE_CUSTOM_IRQ1_MISS_FLAG_SFT 1
+#define AFE_CUSTOM_IRQ1_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ1_MISS_FLAG_MASK_SFT (0x1 << 1)
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_SFT 0
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_MASK 0x1
+#define AFE_CUSTOM_IRQ0_MISS_FLAG_MASK_SFT (0x1 << 0)
+
+/* AFE_IRQ_MCU_MON2 */
+#define AFE_IRQ_B_R_CNT_SFT 8
+#define AFE_IRQ_B_R_CNT_MASK 0xff
+#define AFE_IRQ_B_R_CNT_MASK_SFT (0xff << 8)
+#define AFE_IRQ_B_F_CNT_SFT 0
+#define AFE_IRQ_B_F_CNT_MASK 0xff
+#define AFE_IRQ_B_F_CNT_MASK_SFT (0xff << 0)
+
+/* AFE_IRQ0_CNT_MON */
+#define AFE_IRQ0_CNT_MON_SFT 0
+#define AFE_IRQ0_CNT_MON_MASK 0xffffff
+#define AFE_IRQ0_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ1_CNT_MON */
+#define AFE_IRQ1_CNT_MON_SFT 0
+#define AFE_IRQ1_CNT_MON_MASK 0xffffff
+#define AFE_IRQ1_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ2_CNT_MON */
+#define AFE_IRQ2_CNT_MON_SFT 0
+#define AFE_IRQ2_CNT_MON_MASK 0xffffff
+#define AFE_IRQ2_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ3_CNT_MON */
+#define AFE_IRQ3_CNT_MON_SFT 0
+#define AFE_IRQ3_CNT_MON_MASK 0xffffff
+#define AFE_IRQ3_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ4_CNT_MON */
+#define AFE_IRQ4_CNT_MON_SFT 0
+#define AFE_IRQ4_CNT_MON_MASK 0xffffff
+#define AFE_IRQ4_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ5_CNT_MON */
+#define AFE_IRQ5_CNT_MON_SFT 0
+#define AFE_IRQ5_CNT_MON_MASK 0xffffff
+#define AFE_IRQ5_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ6_CNT_MON */
+#define AFE_IRQ6_CNT_MON_SFT 0
+#define AFE_IRQ6_CNT_MON_MASK 0xffffff
+#define AFE_IRQ6_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ7_CNT_MON */
+#define AFE_IRQ7_CNT_MON_SFT 0
+#define AFE_IRQ7_CNT_MON_MASK 0xffffff
+#define AFE_IRQ7_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ8_CNT_MON */
+#define AFE_IRQ8_CNT_MON_SFT 0
+#define AFE_IRQ8_CNT_MON_MASK 0xffffff
+#define AFE_IRQ8_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ9_CNT_MON */
+#define AFE_IRQ9_CNT_MON_SFT 0
+#define AFE_IRQ9_CNT_MON_MASK 0xffffff
+#define AFE_IRQ9_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ10_CNT_MON */
+#define AFE_IRQ10_CNT_MON_SFT 0
+#define AFE_IRQ10_CNT_MON_MASK 0xffffff
+#define AFE_IRQ10_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ11_CNT_MON */
+#define AFE_IRQ11_CNT_MON_SFT 0
+#define AFE_IRQ11_CNT_MON_MASK 0xffffff
+#define AFE_IRQ11_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ12_CNT_MON */
+#define AFE_IRQ12_CNT_MON_SFT 0
+#define AFE_IRQ12_CNT_MON_MASK 0xffffff
+#define AFE_IRQ12_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ13_CNT_MON */
+#define AFE_IRQ13_CNT_MON_SFT 0
+#define AFE_IRQ13_CNT_MON_MASK 0xffffff
+#define AFE_IRQ13_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ14_CNT_MON */
+#define AFE_IRQ14_CNT_MON_SFT 0
+#define AFE_IRQ14_CNT_MON_MASK 0xffffff
+#define AFE_IRQ14_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ15_CNT_MON */
+#define AFE_IRQ15_CNT_MON_SFT 0
+#define AFE_IRQ15_CNT_MON_MASK 0xffffff
+#define AFE_IRQ15_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ16_CNT_MON */
+#define AFE_IRQ16_CNT_MON_SFT 0
+#define AFE_IRQ16_CNT_MON_MASK 0xffffff
+#define AFE_IRQ16_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ17_CNT_MON */
+#define AFE_IRQ17_CNT_MON_SFT 0
+#define AFE_IRQ17_CNT_MON_MASK 0xffffff
+#define AFE_IRQ17_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ18_CNT_MON */
+#define AFE_IRQ18_CNT_MON_SFT 0
+#define AFE_IRQ18_CNT_MON_MASK 0xffffff
+#define AFE_IRQ18_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ19_CNT_MON */
+#define AFE_IRQ19_CNT_MON_SFT 0
+#define AFE_IRQ19_CNT_MON_MASK 0xffffff
+#define AFE_IRQ19_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ20_CNT_MON */
+#define AFE_IRQ20_CNT_MON_SFT 0
+#define AFE_IRQ20_CNT_MON_MASK 0xffffff
+#define AFE_IRQ20_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ21_CNT_MON */
+#define AFE_IRQ21_CNT_MON_SFT 0
+#define AFE_IRQ21_CNT_MON_MASK 0xffffff
+#define AFE_IRQ21_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ22_CNT_MON */
+#define AFE_IRQ22_CNT_MON_SFT 0
+#define AFE_IRQ22_CNT_MON_MASK 0xffffff
+#define AFE_IRQ22_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ23_CNT_MON */
+#define AFE_IRQ23_CNT_MON_SFT 0
+#define AFE_IRQ23_CNT_MON_MASK 0xffffff
+#define AFE_IRQ23_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ24_CNT_MON */
+#define AFE_IRQ24_CNT_MON_SFT 0
+#define AFE_IRQ24_CNT_MON_MASK 0xffffff
+#define AFE_IRQ24_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ25_CNT_MON */
+#define AFE_IRQ25_CNT_MON_SFT 0
+#define AFE_IRQ25_CNT_MON_MASK 0xffffff
+#define AFE_IRQ25_CNT_MON_MASK_SFT (0xffffff << 0)
+
+/* AFE_IRQ26_CNT_MON */
+#define AFE_IRQ26_CNT_MON_SFT 0
+#define AFE_IRQ26_CNT_MON_MASK 0xffffff
+#define AFE_IRQ26_CNT_MON_MASK_SFT (0xffffff << 0)
+
+ /* AFE_GAIN0_CON0 */
+ /* AFE_GAIN1_CON0 */
+ /* AFE_GAIN2_CON0 */
+ /* AFE_GAIN3_CON0 */
+#define GAIN_TARGET_SYNC_ON_SFT 24
+#define GAIN_TARGET_SYNC_ON_MASK 0x1
+#define GAIN_TARGET_SYNC_ON_MASK_SFT (0x1 << 24)
+#define GAIN_TIMEOUT_SFT 18
+#define GAIN_TIMEOUT_MASK 0x3f
+#define GAIN_TIMEOUT_MASK_SFT (0x3f << 18)
+#define GAIN_TRIG_SFT 17
+#define GAIN_TRIG_MASK 0x1
+#define GAIN_TRIG_MASK_SFT (0x1 << 17)
+#define GAIN_ON_SFT 16
+#define GAIN_ON_MASK 0x1
+#define GAIN_ON_MASK_SFT (0x1 << 16)
+#define GAIN_SAMPLE_PER_STEP_SFT 8
+#define GAIN_SAMPLE_PER_STEP_MASK 0xff
+#define GAIN_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)
+#define GAIN_SEL_DOMAIN_SFT 5
+#define GAIN_SEL_DOMAIN_MASK 0x7
+#define GAIN_SEL_DOMAIN_MASK_SFT (0x7 << 5)
+#define GAIN_SEL_FS_SFT 0
+#define GAIN_SEL_FS_MASK 0x1f
+#define GAIN_SEL_FS_MASK_SFT (0x1f << 0)
+
+ /* AFE_GAIN0_CON1_R */
+ /* AFE_GAIN1_CON1_R */
+ /* AFE_GAIN2_CON1_R */
+ /* AFE_GAIN3_CON1_R */
+#define GAIN_TARGET_R_SFT 0
+#define GAIN_TARGET_R_MASK 0xffffffff
+#define GAIN_TARGET_R_MASK_SFT (0xffffffff << 0)
+
+ /* AFE_GAIN0_CON1_L */
+ /* AFE_GAIN1_CON1_L */
+ /* AFE_GAIN2_CON1_L */
+ /* AFE_GAIN3_CON1_L */
+#define GAIN_TARGET_L_SFT 0
+#define GAIN_TARGET_L_MASK 0xffffffff
+#define GAIN_TARGET_L_MASK_SFT (0xffffffff << 0)
+
+ /* AFE_GAIN0_CON2 */
+ /* AFE_GAIN1_CON2 */
+ /* AFE_GAIN2_CON2 */
+ /* AFE_GAIN3_CON2 */
+#define GAIN_DOWN_STEP_SFT 0
+#define GAIN_DOWN_STEP_MASK 0x3fffff
+#define GAIN_DOWN_STEP_MASK_SFT (0x3fffff << 0)
+
+ /* AFE_GAIN0_CON3 */
+ /* AFE_GAIN1_CON3 */
+ /* AFE_GAIN2_CON3 */
+ /* AFE_GAIN3_CON3 */
+#define GAIN_UP_STEP_SFT 0
+#define GAIN_UP_STEP_MASK 0x3fffff
+#define GAIN_UP_STEP_MASK_SFT (0x3fffff << 0)
+
+ /* AFE_GAIN0_CUR_R */
+ /* AFE_GAIN1_CUR_R */
+ /* AFE_GAIN2_CUR_R */
+ /* AFE_GAIN3_CUR_R */
+#define AFE_GAIN_CUR_R_SFT 0
+#define AFE_GAIN_CUR_R_MASK 0xffffffff
+#define AFE_GAIN_CUR_R_MASK_SFT (0xffffffff << 0)
+
+ /* AFE_GAIN0_CUR_L */
+ /* AFE_GAIN1_CUR_L */
+ /* AFE_GAIN2_CUR_L */
+ /* AFE_GAIN3_CUR_L */
+#define AFE_GAIN_CUR_L_SFT 0
+#define AFE_GAIN_CUR_L_MASK 0xffffffff
+#define AFE_GAIN_CUR_L_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_IPM_VER_MON */
+#define RG_DL_IPM_VER_MON_SFT 0
+#define RG_DL_IPM_VER_MON_MASK 0xffffffff
+#define RG_DL_IPM_VER_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_SRC_CON0 */
+#define AFE_DL_INPUT_MODE_CTL_SFT 24
+#define AFE_DL_INPUT_MODE_CTL_MASK 0x1f
+#define AFE_DL_INPUT_MODE_CTL_MASK_SFT (0x1f << 24)
+#define AFE_DL_CH1_SATURATION_EN_CTL_SFT 21
+#define AFE_DL_CH1_SATURATION_EN_CTL_MASK 0x1
+#define AFE_DL_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 21)
+#define AFE_DL_CH2_SATURATION_EN_CTL_SFT 20
+#define AFE_DL_CH2_SATURATION_EN_CTL_MASK 0x1
+#define AFE_DL_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 20)
+#define AFE_DL_OUTPUT_SEL_CTL_SFT 18
+#define AFE_DL_OUTPUT_SEL_CTL_MASK 0x3
+#define AFE_DL_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 18)
+#define AFE_DL_FADEIN_0START_EN_SFT 16
+#define AFE_DL_FADEIN_0START_EN_MASK 0x3
+#define AFE_DL_FADEIN_0START_EN_MASK_SFT (0x3 << 16)
+#define AFE_DL_DISABLE_HW_CG_CTL_SFT 15
+#define AFE_DL_DISABLE_HW_CG_CTL_MASK 0x1
+#define AFE_DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
+#define AFE_DL_MUTE_CH1_OFF_CTL_PRE_SFT 12
+#define AFE_DL_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
+#define AFE_DL_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
+#define AFE_DL_MUTE_CH2_OFF_CTL_PRE_SFT 11
+#define AFE_DL_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
+#define AFE_DL_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
+#define AFE_DL_ARAMPSP_CTL_PRE_SFT 9
+#define AFE_DL_ARAMPSP_CTL_PRE_MASK 0x3
+#define AFE_DL_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)
+#define AFE_DL_VOICE_MODE_CTL_PRE_SFT 5
+#define AFE_DL_VOICE_MODE_CTL_PRE_MASK 0x1
+#define AFE_DL_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
+#define AFE_DL_MUTE_CH1_ON_CTL_PRE_SFT 4
+#define AFE_DL_MUTE_CH1_ON_CTL_PRE_MASK 0x1
+#define AFE_DL_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
+#define AFE_DL_MUTE_CH2_ON_CTL_PRE_SFT 3
+#define AFE_DL_MUTE_CH2_ON_CTL_PRE_MASK 0x1
+#define AFE_DL_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
+#define AFE_DL_GAIN_ON_CTL_PRE_SFT 1
+#define AFE_DL_GAIN_ON_CTL_PRE_MASK 0x1
+#define AFE_DL_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
+#define AFE_DL_SRC_ON_TMP_CTL_PRE_SFT 0
+#define AFE_DL_SRC_ON_TMP_CTL_PRE_MASK 0x1
+#define AFE_DL_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_DL_SRC_CON1 */
+#define AFE_DL_GAIN1_CTL_PRE_SFT 16
+#define AFE_DL_GAIN1_CTL_PRE_MASK 0xffff
+#define AFE_DL_GAIN1_CTL_PRE_MASK_SFT (0xffff << 16)
+#define AFE_DL_GAIN2_CTL_PRE_SFT 0
+#define AFE_DL_GAIN2_CTL_PRE_MASK 0xffff
+#define AFE_DL_GAIN2_CTL_PRE_MASK_SFT (0xffff << 0)
+
+/* AFE_ADDA_DL_SRC_DEBUG_MON0 */
+#define AFE_DL_SLT_CNT_FLAG_CTL_SFT 15
+#define AFE_DL_SLT_CNT_FLAG_CTL_MASK 0x1
+#define AFE_DL_SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 15)
+#define AFE_DL_INI_SRAM_FINISH_CTL_SFT 12
+#define AFE_DL_INI_SRAM_FINISH_CTL_MASK 0x1
+#define AFE_DL_INI_SRAM_FINISH_CTL_MASK_SFT (0x1 << 12)
+#define AFE_DL_SLT_COUNTER_CTL_SFT 0
+#define AFE_DL_SLT_COUNTER_CTL_MASK 0xfff
+#define AFE_DL_SLT_COUNTER_CTL_MASK_SFT (0xfff << 0)
+
+/* AFE_ADDA_DL_PREDIS_CON0 */
+#define AFE_DL_PREDIS_ON_CH1_CTL_SFT 31
+#define AFE_DL_PREDIS_ON_CH1_CTL_MASK 0x1
+#define AFE_DL_PREDIS_ON_CH1_CTL_MASK_SFT (0x1 << 31)
+#define AFE_DL_PREDIS_A2_CH1_CTL_SFT 16
+#define AFE_DL_PREDIS_A2_CH1_CTL_MASK 0xfff
+#define AFE_DL_PREDIS_A2_CH1_CTL_MASK_SFT (0xfff << 16)
+#define AFE_DL_PREDIS_A3_CH1_CTL_SFT 0
+#define AFE_DL_PREDIS_A3_CH1_CTL_MASK 0xfff
+#define AFE_DL_PREDIS_A3_CH1_CTL_MASK_SFT (0xfff << 0)
+
+/* AFE_ADDA_DL_PREDIS_CON1 */
+#define AFE_DL_PREDIS_ON_CH2_CTL_SFT 31
+#define AFE_DL_PREDIS_ON_CH2_CTL_MASK 0x1
+#define AFE_DL_PREDIS_ON_CH2_CTL_MASK_SFT (0x1 << 31)
+#define AFE_DL_PREDIS_A2_CH2_CTL_SFT 16
+#define AFE_DL_PREDIS_A2_CH2_CTL_MASK 0xfff
+#define AFE_DL_PREDIS_A2_CH2_CTL_MASK_SFT (0xfff << 16)
+#define AFE_DL_PREDIS_A3_CH2_CTL_SFT 0
+#define AFE_DL_PREDIS_A3_CH2_CTL_MASK 0xfff
+#define AFE_DL_PREDIS_A3_CH2_CTL_MASK_SFT (0xfff << 0)
+
+/* AFE_ADDA_DL_PREDIS_CON2 */
+#define AFE_DL_PREDIS_A4_CH1_CTL_SFT 16
+#define AFE_DL_PREDIS_A4_CH1_CTL_MASK 0xfff
+#define AFE_DL_PREDIS_A4_CH1_CTL_MASK_SFT (0xfff << 16)
+#define AFE_DL_PREDIS_A5_CH1_CTL_SFT 0
+#define AFE_DL_PREDIS_A5_CH1_CTL_MASK 0xfff
+#define AFE_DL_PREDIS_A5_CH1_CTL_MASK_SFT (0xfff << 0)
+
+/* AFE_ADDA_DL_PREDIS_CON3 */
+#define AFE_DL_PREDIS_A4_CH2_CTL_SFT 16
+#define AFE_DL_PREDIS_A4_CH2_CTL_MASK 0xfff
+#define AFE_DL_PREDIS_A4_CH2_CTL_MASK_SFT (0xfff << 16)
+#define AFE_DL_PREDIS_A5_CH2_CTL_SFT 0
+#define AFE_DL_PREDIS_A5_CH2_CTL_MASK 0xfff
+#define AFE_DL_PREDIS_A5_CH2_CTL_MASK_SFT (0xfff << 0)
+
+/* AFE_ADDA_DL_SDM_DCCOMP_CON */
+#define AFE_DL_USE_NEW_2ND_12BIT_SDM_SFT 31
+#define AFE_DL_USE_NEW_2ND_12BIT_SDM_MASK 0x1
+#define AFE_DL_USE_NEW_2ND_12BIT_SDM_MASK_SFT (0x1 << 31)
+#define AFE_DL_USE_NEW_2ND_SDM_SFT 30
+#define AFE_DL_USE_NEW_2ND_SDM_MASK 0x1
+#define AFE_DL_USE_NEW_2ND_SDM_MASK_SFT (0x1 << 30)
+#define AFE_DL_USE_3RD_SDM_SFT 28
+#define AFE_DL_USE_3RD_SDM_MASK 0x1
+#define AFE_DL_USE_3RD_SDM_MASK_SFT (0x1 << 28)
+#define AFE_DL_DCM_AUTO_IDLE_EN_SFT 14
+#define AFE_DL_DCM_AUTO_IDLE_EN_MASK 0x1
+#define AFE_DL_DCM_AUTO_IDLE_EN_MASK_SFT (0x1 << 14)
+#define AFE_DL_SRC_DCM_EN_SFT 13
+#define AFE_DL_SRC_DCM_EN_MASK 0x1
+#define AFE_DL_SRC_DCM_EN_MASK_SFT (0x1 << 13)
+#define AFE_DL_POST_SRC_DCM_EN_SFT 12
+#define AFE_DL_POST_SRC_DCM_EN_MASK 0x1
+#define AFE_DL_POST_SRC_DCM_EN_MASK_SFT (0x1 << 12)
+#define AFE_DL_DCCOMP_SYNC_TOGGLE_SFT 11
+#define AFE_DL_DCCOMP_SYNC_TOGGLE_MASK 0x1
+#define AFE_DL_DCCOMP_SYNC_TOGGLE_MASK_SFT (0x1 << 11)
+#define AFE_DL_AUD_SDM_MONO_SFT 9
+#define AFE_DL_AUD_SDM_MONO_MASK 0x1
+#define AFE_DL_AUD_SDM_MONO_MASK_SFT (0x1 << 9)
+#define AFE_DL_AUD_DC_COMP_EN_SFT 8
+#define AFE_DL_AUD_DC_COMP_EN_MASK 0x1
+#define AFE_DL_AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)
+#define AFE_DL_ATTGAIN_CTL_SFT 0
+#define AFE_DL_ATTGAIN_CTL_MASK 0x3f
+#define AFE_DL_ATTGAIN_CTL_MASK_SFT (0x3f << 0)
+
+/* AFE_ADDA_DL_SDM_TEST */
+#define AFE_DL_TRI_AMP_DIV_SFT 12
+#define AFE_DL_TRI_AMP_DIV_MASK 0x7
+#define AFE_DL_TRI_AMP_DIV_MASK_SFT (0x7 << 12)
+#define AFE_DL_TRI_FREQ_DIV_SFT 4
+#define AFE_DL_TRI_FREQ_DIV_MASK 0x3f
+#define AFE_DL_TRI_FREQ_DIV_MASK_SFT (0x3f << 4)
+#define AFE_DL_RG_DL_LEFT_SAT_RSTN_SFT 3
+#define AFE_DL_RG_DL_LEFT_SAT_RSTN_MASK 0x1
+#define AFE_DL_RG_DL_LEFT_SAT_RSTN_MASK_SFT (0x1 << 3)
+#define AFE_DL_RG_DL_RIGHT_SAT_RSTN_SFT 2
+#define AFE_DL_RG_DL_RIGHT_SAT_RSTN_MASK 0x1
+#define AFE_DL_RG_DL_RIGHT_SAT_RSTN_MASK_SFT (0x1 << 2)
+#define AFE_DL_TRI_MUTE_SW_SFT 1
+#define AFE_DL_TRI_MUTE_SW_MASK 0x1
+#define AFE_DL_TRI_MUTE_SW_MASK_SFT (0x1 << 1)
+#define AFE_DL_TRI_DAC_EN_SFT 0
+#define AFE_DL_TRI_DAC_EN_MASK 0x1
+#define AFE_DL_TRI_DAC_EN_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_DL_DC_COMP_CFG0 */
+#define AFE_DL_AUD_DC_COMP_LCH_H_SFT 16
+#define AFE_DL_AUD_DC_COMP_LCH_H_MASK 0xffff
+#define AFE_DL_AUD_DC_COMP_LCH_H_MASK_SFT (0xffff << 16)
+#define AFE_DL_AUD_DC_COMP_LCH_L_SFT 0
+#define AFE_DL_AUD_DC_COMP_LCH_L_MASK 0xffff
+#define AFE_DL_AUD_DC_COMP_LCH_L_MASK_SFT (0xffff << 0)
+
+/* AFE_ADDA_DL_DC_COMP_CFG1 */
+#define AFE_DL_AUD_DC_COMP_RCH_H_SFT 16
+#define AFE_DL_AUD_DC_COMP_RCH_H_MASK 0xffff
+#define AFE_DL_AUD_DC_COMP_RCH_H_MASK_SFT (0xffff << 16)
+#define AFE_DL_AUD_DC_COMP_RCH_L_SFT 0
+#define AFE_DL_AUD_DC_COMP_RCH_L_MASK 0xffff
+#define AFE_DL_AUD_DC_COMP_RCH_L_MASK_SFT (0xffff << 0)
+
+/* AFE_ADDA_DL_SDM_OUT_MON */
+#define AFE_DL_SDM_DITHER_MON_SFT 28
+#define AFE_DL_SDM_DITHER_MON_MASK 0x3
+#define AFE_DL_SDM_DITHER_MON_MASK_SFT (0x3 << 28)
+#define AFE_DL_BF_SDM_LEFT_SAT_SFT 21
+#define AFE_DL_BF_SDM_LEFT_SAT_MASK 0x1
+#define AFE_DL_BF_SDM_LEFT_SAT_MASK_SFT (0x1 << 21)
+#define AFE_DL_BF_SDM_RIGHT_SAT_SFT 20
+#define AFE_DL_BF_SDM_RIGHT_SAT_MASK 0x1
+#define AFE_DL_BF_SDM_RIGHT_SAT_MASK_SFT (0x1 << 20)
+#define AFE_DL_3RD_SDM_AUTO_RESET_R_SFT 19
+#define AFE_DL_3RD_SDM_AUTO_RESET_R_MASK 0x1
+#define AFE_DL_3RD_SDM_AUTO_RESET_R_MASK_SFT (0x1 << 19)
+#define AFE_DL_3RD_SDM_AUTO_RESET_L_SFT 18
+#define AFE_DL_3RD_SDM_AUTO_RESET_L_MASK 0x1
+#define AFE_DL_3RD_SDM_AUTO_RESET_L_MASK_SFT (0x1 << 18)
+#define AFE_DL_2ND_SDM_AUTO_RESET_R_SFT 17
+#define AFE_DL_2ND_SDM_AUTO_RESET_R_MASK 0x1
+#define AFE_DL_2ND_SDM_AUTO_RESET_R_MASK_SFT (0x1 << 17)
+#define AFE_DL_2ND_SDM_AUTO_RESET_L_SFT 16
+#define AFE_DL_2ND_SDM_AUTO_RESET_L_MASK 0x1
+#define AFE_DL_2ND_SDM_AUTO_RESET_L_MASK_SFT (0x1 << 16)
+#define AFE_DL_AUD_SDM_OUT_L_SFT 8
+#define AFE_DL_AUD_SDM_OUT_L_MASK 0xff
+#define AFE_DL_AUD_SDM_OUT_L_MASK_SFT (0xff << 8)
+#define AFE_DL_AUD_SDM_OUT_R_SFT 0
+#define AFE_DL_AUD_SDM_OUT_R_MASK 0xff
+#define AFE_DL_AUD_SDM_OUT_R_MASK_SFT (0xff << 0)
+
+/* AFE_ADDA_DL_SRC_LCH_MON */
+#define AFE_DL_ASDM_LEFT_SFT 0
+#define AFE_DL_ASDM_LEFT_MASK 0xffffff
+#define AFE_DL_ASDM_LEFT_MASK_SFT (0xffffff << 0)
+
+/* AFE_ADDA_DL_SRC_RCH_MON */
+#define AFE_DL_ASDM_RIGHT_SFT 0
+#define AFE_DL_ASDM_RIGHT_MASK 0xffffff
+#define AFE_DL_ASDM_RIGHT_MASK_SFT (0xffffff << 0)
+
+/* AFE_ADDA_DL_SRC_DEBUG */
+#define AFE_DL_SLT_CNT_FLAG_RESET_CTL_SFT 12
+#define AFE_DL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1
+#define AFE_DL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 12)
+#define AFE_DL_SLT_CNT_THD_CTL_SFT 0
+#define AFE_DL_SLT_CNT_THD_CTL_MASK 0xfff
+#define AFE_DL_SLT_CNT_THD_CTL_MASK_SFT (0xfff << 0)
+
+/* AFE_ADDA_DL_SDM_DITHER_CON */
+#define AFE_DL_SDM_DITHER_64TAP_EN_SFT 20
+#define AFE_DL_SDM_DITHER_64TAP_EN_MASK 0x1
+#define AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT (0x1 << 20)
+#define AFE_DL_SDM_DITHER_EN_SFT 16
+#define AFE_DL_SDM_DITHER_EN_MASK 0x1
+#define AFE_DL_SDM_DITHER_EN_MASK_SFT (0x1 << 16)
+#define AFE_DL_SDM_DITHER_GAIN_SFT 0
+#define AFE_DL_SDM_DITHER_GAIN_MASK 0xff
+#define AFE_DL_SDM_DITHER_GAIN_MASK_SFT (0xff << 0)
+
+/* AFE_ADDA_DL_SDM_AUTO_RESET_CON */
+#define AFE_DL_SDM_AUTO_RESET_TEST_ON_SFT 31
+#define AFE_DL_SDM_AUTO_RESET_TEST_ON_MASK 0x1
+#define AFE_DL_SDM_AUTO_RESET_TEST_ON_MASK_SFT (0x1 << 31)
+#define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_SFT 24
+#define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_MASK 0x1
+#define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_MASK_SFT (0x1 << 24)
+#define AFE_DL_SDM_AUTO_RESET_COUNT_TH_SFT 0
+#define AFE_DL_SDM_AUTO_RESET_COUNT_TH_MASK 0xffffff
+#define AFE_DL_SDM_AUTO_RESET_COUNT_TH_MASK_SFT (0xffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_CONFIG */
+#define AFE_DL_HBF1_SW_CONFIG_SFT 31
+#define AFE_DL_HBF1_SW_CONFIG_MASK 0x1
+#define AFE_DL_HBF1_SW_CONFIG_MASK_SFT (0x1 << 31)
+#define AFE_DL_HBF1_TAPNUM_CONFIG_SFT 16
+#define AFE_DL_HBF1_TAPNUM_CONFIG_MASK 0x7f
+#define AFE_DL_HBF1_TAPNUM_CONFIG_MASK_SFT (0x7f << 16)
+#define AFE_DL_SCF1_SW_CONFIG_SFT 8
+#define AFE_DL_SCF1_SW_CONFIG_MASK 0x1
+#define AFE_DL_SCF1_SW_CONFIG_MASK_SFT (0x1 << 8)
+#define AFE_DL_SCF1_TAPNUM_CONFIG_SFT 0
+#define AFE_DL_SCF1_TAPNUM_CONFIG_MASK 0xff
+#define AFE_DL_SCF1_TAPNUM_CONFIG_MASK_SFT (0xff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG */
+#define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_SFT 0
+#define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_MASK 0xffffffff
+#define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_NLE_R_CFG0 */
+#define RG_NLE_R_GAIN_DIG_TAR_SFT 24
+#define RG_NLE_R_GAIN_DIG_TAR_MASK 0x3f
+#define RG_NLE_R_GAIN_DIG_TAR_MASK_SFT (0x3f << 24)
+#define RG_NLE_R_GAIN_ANA_TAR_SFT 16
+#define RG_NLE_R_GAIN_ANA_TAR_MASK 0x3f
+#define RG_NLE_R_GAIN_ANA_TAR_MASK_SFT (0x3f << 16)
+#define RG_NLE_R_NO_ZCE_SFT 15
+#define RG_NLE_R_NO_ZCE_MASK 0x1
+#define RG_NLE_R_NO_ZCE_MASK_SFT (0x1 << 15)
+#define RG_NLE_R_HP_MODE_SFT 14
+#define RG_NLE_R_HP_MODE_MASK 0x1
+#define RG_NLE_R_HP_MODE_MASK_SFT (0x1 << 14)
+#define RG_NLE_R_GAIN_STEP_SFT 8
+#define RG_NLE_R_GAIN_STEP_MASK 0x7
+#define RG_NLE_R_GAIN_STEP_MASK_SFT (0x7 << 8)
+#define RG_NLE_R_TOGGLE_NUM_SFT 0
+#define RG_NLE_R_TOGGLE_NUM_MASK 0x3f
+#define RG_NLE_R_TOGGLE_NUM_MASK_SFT (0x3f << 0)
+
+/* AFE_DL_NLE_R_CFG1 */
+#define RG_NLE_R_INITIATE_SFT 24
+#define RG_NLE_R_INITIATE_MASK 0x1
+#define RG_NLE_R_INITIATE_MASK_SFT (0x1 << 24)
+#define RG_NLE_R_READY_SFT 16
+#define RG_NLE_R_READY_MASK 0x1
+#define RG_NLE_R_READY_MASK_SFT (0x1 << 16)
+#define RG_NLE_R_TIMEOUT_SCALE_SFT 12
+#define RG_NLE_R_TIMEOUT_SCALE_MASK 0x7
+#define RG_NLE_R_TIMEOUT_SCALE_MASK_SFT (0x7 << 12)
+#define RG_NLE_R_ANC_ON_SFT 11
+#define RG_NLE_R_ANC_ON_MASK 0x1
+#define RG_NLE_R_ANC_ON_MASK_SFT (0x1 << 11)
+#define RG_NLE_R_GTIME_SFT 8
+#define RG_NLE_R_GTIME_MASK 0x7
+#define RG_NLE_R_GTIME_MASK_SFT (0x7 << 8)
+#define RG_NLE_R_ON_SFT 7
+#define RG_NLE_R_ON_MASK 0x1
+#define RG_NLE_R_ON_MASK_SFT (0x1 << 7)
+#define RG_PDN_NLE_CTL_SFT 6
+#define RG_PDN_NLE_CTL_MASK 0x1
+#define RG_PDN_NLE_CTL_MASK_SFT (0x1 << 6)
+#define RG_NLE_R_DELAY_ANA_SFT 0
+#define RG_NLE_R_DELAY_ANA_MASK 0x3f
+#define RG_NLE_R_DELAY_ANA_MASK_SFT (0x3f << 0)
+
+/* AFE_DL_NLE_L_CFG0 */
+#define RG_NLE_L_GAIN_DIG_TAR_SFT 24
+#define RG_NLE_L_GAIN_DIG_TAR_MASK 0x3f
+#define RG_NLE_L_GAIN_DIG_TAR_MASK_SFT (0x3f << 24)
+#define RG_NLE_L_GAIN_ANA_TAR_SFT 16
+#define RG_NLE_L_GAIN_ANA_TAR_MASK 0x3f
+#define RG_NLE_L_GAIN_ANA_TAR_MASK_SFT (0x3f << 16)
+#define RG_NLE_L_NO_ZCE_SFT 15
+#define RG_NLE_L_NO_ZCE_MASK 0x1
+#define RG_NLE_L_NO_ZCE_MASK_SFT (0x1 << 15)
+#define RG_NLE_L_HP_MODE_SFT 14
+#define RG_NLE_L_HP_MODE_MASK 0x1
+#define RG_NLE_L_HP_MODE_MASK_SFT (0x1 << 14)
+#define RG_NLE_L_GAIN_STEP_SFT 8
+#define RG_NLE_L_GAIN_STEP_MASK 0x7
+#define RG_NLE_L_GAIN_STEP_MASK_SFT (0x7 << 8)
+#define RG_NLE_L_TOGGLE_NUM_SFT 0
+#define RG_NLE_L_TOGGLE_NUM_MASK 0x3f
+#define RG_NLE_L_TOGGLE_NUM_MASK_SFT (0x3f << 0)
+
+/* AFE_DL_NLE_L_CFG1 */
+#define RG_NLE_L_INITIATE_SFT 24
+#define RG_NLE_L_INITIATE_MASK 0x1
+#define RG_NLE_L_INITIATE_MASK_SFT (0x1 << 24)
+#define RG_NLE_L_READY_SFT 16
+#define RG_NLE_L_READY_MASK 0x1
+#define RG_NLE_L_READY_MASK_SFT (0x1 << 16)
+#define RG_NLE_L_TIMEOUT_SCALE_SFT 12
+#define RG_NLE_L_TIMEOUT_SCALE_MASK 0x7
+#define RG_NLE_L_TIMEOUT_SCALE_MASK_SFT (0x7 << 12)
+#define RG_NLE_L_ANC_ON_SFT 11
+#define RG_NLE_L_ANC_ON_MASK 0x1
+#define RG_NLE_L_ANC_ON_MASK_SFT (0x1 << 11)
+#define RG_NLE_L_GTIME_SFT 8
+#define RG_NLE_L_GTIME_MASK 0x7
+#define RG_NLE_L_GTIME_MASK_SFT (0x7 << 8)
+#define RG_NLE_L_ON_SFT 7
+#define RG_NLE_L_ON_MASK 0x1
+#define RG_NLE_L_ON_MASK_SFT (0x1 << 7)
+#define RG_PDN_NLE_CTL_SFT 6
+#define RG_PDN_NLE_CTL_MASK 0x1
+#define RG_PDN_NLE_CTL_MASK_SFT (0x1 << 6)
+#define RG_NLE_L_DELAY_ANA_SFT 0
+#define RG_NLE_L_DELAY_ANA_MASK 0x3f
+#define RG_NLE_L_DELAY_ANA_MASK_SFT (0x3f << 0)
+
+/* AFE_DL_NLE_R_MON0 */
+#define NLE_R_GAIN_DIG_CUR_SFT 24
+#define NLE_R_GAIN_DIG_CUR_MASK 0x3f
+#define NLE_R_GAIN_DIG_CUR_MASK_SFT (0x3f << 24)
+#define NLE_R_ANC_MASK_SFT 23
+#define NLE_R_ANC_MASK_MASK 0x1
+#define NLE_R_ANC_MASK_MASK_SFT (0x1 << 23)
+#define NLE_R_GAIN_ANA_CUR_SFT 16
+#define NLE_R_GAIN_ANA_CUR_MASK 0x3f
+#define NLE_R_GAIN_ANA_CUR_MASK_SFT (0x3f << 16)
+#define NLE_R_GAIN_DIG_TAR_CUR_SFT 8
+#define NLE_R_GAIN_DIG_TAR_CUR_MASK 0x3f
+#define NLE_R_GAIN_DIG_TAR_CUR_MASK_SFT (0x3f << 8)
+#define NLE_R_GAIN_ANA_TAR_CUR_SFT 0
+#define NLE_R_GAIN_ANA_TAR_CUR_MASK 0x3f
+#define NLE_R_GAIN_ANA_TAR_CUR_MASK_SFT (0x3f << 0)
+
+/* AFE_DL_NLE_R_MON1 */
+#define NLE_R_STATE_CUR_SFT 28
+#define NLE_R_STATE_CUR_MASK 0x7
+#define NLE_R_STATE_CUR_MASK_SFT (0x7 << 28)
+#define NLE_R_GAIN_STEP_CUR_SFT 24
+#define NLE_R_GAIN_STEP_CUR_MASK 0xf
+#define NLE_R_GAIN_STEP_CUR_MASK_SFT (0xf << 24)
+#define NLE_R_TOGGLE_NUM_CUR_SFT 16
+#define NLE_R_TOGGLE_NUM_CUR_MASK 0x3f
+#define NLE_R_TOGGLE_NUM_CUR_MASK_SFT (0x3f << 16)
+#define NLE_R_DIG_GAIN_TARGETED_SFT 15
+#define NLE_R_DIG_GAIN_TARGETED_MASK 0x1
+#define NLE_R_DIG_GAIN_TARGETED_MASK_SFT (0x1 << 15)
+#define NLE_R_DIG_GAIN_INCREASE_SFT 14
+#define NLE_R_DIG_GAIN_INCREASE_MASK 0x1
+#define NLE_R_DIG_GAIN_INCREASE_MASK_SFT (0x1 << 14)
+#define NLE_R_DIG_GAIN_DECREASE_SFT 13
+#define NLE_R_DIG_GAIN_DECREASE_MASK 0x1
+#define NLE_R_DIG_GAIN_DECREASE_MASK_SFT (0x1 << 13)
+#define NLE_R_ANA_GAIN_TARGETED_SFT 12
+#define NLE_R_ANA_GAIN_TARGETED_MASK 0x1
+#define NLE_R_ANA_GAIN_TARGETED_MASK_SFT (0x1 << 12)
+#define NLE_R_ANA_GAIN_INCREASE_SFT 11
+#define NLE_R_ANA_GAIN_INCREASE_MASK 0x1
+#define NLE_R_ANA_GAIN_INCREASE_MASK_SFT (0x1 << 11)
+#define NLE_R_ANA_GAIN_DECREASE_SFT 10
+#define NLE_R_ANA_GAIN_DECREASE_MASK 0x1
+#define NLE_R_ANA_GAIN_DECREASE_MASK_SFT (0x1 << 10)
+#define NLE_R_TIME_COUNTER_CUR_SFT 0
+#define NLE_R_TIME_COUNTER_CUR_MASK 0x1ff
+#define NLE_R_TIME_COUNTER_CUR_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL_NLE_R_MON2 */
+#define NLE_R_ANA_GAIN_SFT 8
+#define NLE_R_ANA_GAIN_MASK 0x1f
+#define NLE_R_ANA_GAIN_MASK_SFT (0x1f << 8)
+#define NLE_MOSI2_ANA_GAIN_SFT 0
+#define NLE_MOSI2_ANA_GAIN_MASK 0x7f
+#define NLE_MOSI2_ANA_GAIN_MASK_SFT (0x7f << 0)
+
+/* AFE_DL_NLE_L_MON0 */
+#define NLE_L_GAIN_DIG_CUR_SFT 24
+#define NLE_L_GAIN_DIG_CUR_MASK 0x3f
+#define NLE_L_GAIN_DIG_CUR_MASK_SFT (0x3f << 24)
+#define NLE_L_ANC_MASK_SFT 23
+#define NLE_L_ANC_MASK_MASK 0x1
+#define NLE_L_ANC_MASK_MASK_SFT (0x1 << 23)
+#define NLE_L_GAIN_ANA_CUR_SFT 16
+#define NLE_L_GAIN_ANA_CUR_MASK 0x3f
+#define NLE_L_GAIN_ANA_CUR_MASK_SFT (0x3f << 16)
+#define NLE_L_GAIN_DIG_TAR_CUR_SFT 8
+#define NLE_L_GAIN_DIG_TAR_CUR_MASK 0x3f
+#define NLE_L_GAIN_DIG_TAR_CUR_MASK_SFT (0x3f << 8)
+#define NLE_L_GAIN_ANA_TAR_CUR_SFT 0
+#define NLE_L_GAIN_ANA_TAR_CUR_MASK 0x3f
+#define NLE_L_GAIN_ANA_TAR_CUR_MASK_SFT (0x3f << 0)
+
+/* AFE_DL_NLE_L_MON1 */
+#define NLE_L_STATE_CUR_SFT 28
+#define NLE_L_STATE_CUR_MASK 0x7
+#define NLE_L_STATE_CUR_MASK_SFT (0x7 << 28)
+#define NLE_L_GAIN_STEP_CUR_SFT 24
+#define NLE_L_GAIN_STEP_CUR_MASK 0xf
+#define NLE_L_GAIN_STEP_CUR_MASK_SFT (0xf << 24)
+#define NLE_L_TOGGLE_NUM_CUR_SFT 16
+#define NLE_L_TOGGLE_NUM_CUR_MASK 0x3f
+#define NLE_L_TOGGLE_NUM_CUR_MASK_SFT (0x3f << 16)
+#define NLE_L_DIG_GAIN_TARGETED_SFT 15
+#define NLE_L_DIG_GAIN_TARGETED_MASK 0x1
+#define NLE_L_DIG_GAIN_TARGETED_MASK_SFT (0x1 << 15)
+#define NLE_L_DIG_GAIN_INCREASE_SFT 14
+#define NLE_L_DIG_GAIN_INCREASE_MASK 0x1
+#define NLE_L_DIG_GAIN_INCREASE_MASK_SFT (0x1 << 14)
+#define NLE_L_DIG_GAIN_DECREASE_SFT 13
+#define NLE_L_DIG_GAIN_DECREASE_MASK 0x1
+#define NLE_L_DIG_GAIN_DECREASE_MASK_SFT (0x1 << 13)
+#define NLE_L_ANA_GAIN_TARGETED_SFT 12
+#define NLE_L_ANA_GAIN_TARGETED_MASK 0x1
+#define NLE_L_ANA_GAIN_TARGETED_MASK_SFT (0x1 << 12)
+#define NLE_L_ANA_GAIN_INCREASE_SFT 11
+#define NLE_L_ANA_GAIN_INCREASE_MASK 0x1
+#define NLE_L_ANA_GAIN_INCREASE_MASK_SFT (0x1 << 11)
+#define NLE_L_ANA_GAIN_DECREASE_SFT 10
+#define NLE_L_ANA_GAIN_DECREASE_MASK 0x1
+#define NLE_L_ANA_GAIN_DECREASE_MASK_SFT (0x1 << 10)
+#define NLE_L_TIME_COUNTER_CUR_SFT 0
+#define NLE_L_TIME_COUNTER_CUR_MASK 0x1ff
+#define NLE_L_TIME_COUNTER_CUR_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL_NLE_L_MON2 */
+#define NLE_L_ANA_GAIN_SFT 8
+#define NLE_L_ANA_GAIN_MASK 0x1f
+#define NLE_L_ANA_GAIN_MASK_SFT (0x1f << 8)
+#define NLE_MOSI1_ANA_GAIN_SFT 0
+#define NLE_MOSI1_ANA_GAIN_MASK 0x7f
+#define NLE_MOSI1_ANA_GAIN_MASK_SFT (0x7f << 0)
+
+/* AFE_DL_NLE_GAIN_CFG0 */
+#define MISO2_SEL_SFT 4
+#define MISO2_SEL_MASK 0x3
+#define MISO2_SEL_MASK_SFT (0x3 << 4)
+#define MISO1_SEL_SFT 0
+#define MISO1_SEL_MASK 0x3
+#define MISO1_SEL_MASK_SFT (0x3 << 0)
+
+/* AFE_DEM_IDWA_CON0 */
+#define RG_IDWA_SDM_MAV_EN_SFT 31
+#define RG_IDWA_SDM_MAV_EN_MASK 0x1
+#define RG_IDWA_SDM_MAV_EN_MASK_SFT (0x1 << 31)
+#define RG_IDWA_SDM_ADITHON_SFT 30
+#define RG_IDWA_SDM_ADITHON_MASK 0x1
+#define RG_IDWA_SDM_ADITHON_MASK_SFT (0x1 << 30)
+#define RG_IDWA_SDM_ADITHVAL_SFT 28
+#define RG_IDWA_SDM_ADITHVAL_MASK 0x3
+#define RG_IDWA_SDM_ADITHVAL_MASK_SFT (0x3 << 28)
+#define RG_IDWA_SDM_LOOPBACK_SFT 27
+#define RG_IDWA_SDM_LOOPBACK_MASK 0x1
+#define RG_IDWA_SDM_LOOPBACK_MASK_SFT (0x1 << 27)
+#define RG_IDWA_SEL_SFT 26
+#define RG_IDWA_SEL_MASK 0x1
+#define RG_IDWA_SEL_MASK_SFT (0x1 << 26)
+#define RG_IDWA_ON_SFT 25
+#define RG_IDWA_ON_MASK 0x1
+#define RG_IDWA_ON_MASK_SFT (0x1 << 25)
+#define RG_DEM_IN_LR_SWAP_SFT 24
+#define RG_DEM_IN_LR_SWAP_MASK 0x1
+#define RG_DEM_IN_LR_SWAP_MASK_SFT (0x1 << 24)
+#define RG_DEM_IN_L_INV_SFT 23
+#define RG_DEM_IN_L_INV_MASK 0x1
+#define RG_DEM_IN_L_INV_MASK_SFT (0x1 << 23)
+#define RG_DEM_IN_R_EQ_L_SFT 22
+#define RG_DEM_IN_R_EQ_L_MASK 0x1
+#define RG_DEM_IN_R_EQ_L_MASK_SFT (0x1 << 22)
+#define RG_DEM_IN_L_MUTE_SFT 21
+#define RG_DEM_IN_L_MUTE_MASK 0x1
+#define RG_DEM_IN_L_MUTE_MASK_SFT (0x1 << 21)
+#define RG_DEM_IN_R_MUTE_SFT 20
+#define RG_DEM_IN_R_MUTE_MASK 0x1
+#define RG_DEM_IN_R_MUTE_MASK_SFT (0x1 << 20)
+#define RG_DEM_IN_SOURCE_SFT 19
+#define RG_DEM_IN_SOURCE_MASK 0x1
+#define RG_DEM_IN_SOURCE_MASK_SFT (0x1 << 19)
+#define RG_DEM_SPLITTER_TRUNC_RND_SFT 18
+#define RG_DEM_SPLITTER_TRUNC_RND_MASK 0x1
+#define RG_DEM_SPLITTER_TRUNC_RND_MASK_SFT (0x1 << 18)
+#define RG_DEM_SCRAMBLER_CG_EN_SFT 17
+#define RG_DEM_SCRAMBLER_CG_EN_MASK 0x1
+#define RG_DEM_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 17)
+#define RG_DEM_SCRAMBLER_EN_SFT 16
+#define RG_DEM_SCRAMBLER_EN_MASK 0x1
+#define RG_DEM_SCRAMBLER_EN_MASK_SFT (0x1 << 16)
+#define RG_DEM_AUD_SDM_7BIT_SEL_SFT 15
+#define RG_DEM_AUD_SDM_7BIT_SEL_MASK 0x1
+#define RG_DEM_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 15)
+#define RG_DEM_ZERO_PAD_DISABLE_SFT 14
+#define RG_DEM_ZERO_PAD_DISABLE_MASK 0x1
+#define RG_DEM_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 14)
+#define RG_DEM_SPLITTER_TEST_EN_SFT 13
+#define RG_DEM_SPLITTER_TEST_EN_MASK 0x1
+#define RG_DEM_SPLITTER_TEST_EN_MASK_SFT (0x1 << 13)
+#define RG_DEM_IDAC_TEST_EN_SFT 12
+#define RG_DEM_IDAC_TEST_EN_MASK 0x1
+#define RG_DEM_IDAC_TEST_EN_MASK_SFT (0x1 << 12)
+#define RG_DEM_SPLIT_SCRAM_ON_SFT 11
+#define RG_DEM_SPLIT_SCRAM_ON_MASK 0x1
+#define RG_DEM_SPLIT_SCRAM_ON_MASK_SFT (0x1 << 11)
+#define RG_DEM_RAND_EN_SFT 10
+#define RG_DEM_RAND_EN_MASK 0x1
+#define RG_DEM_RAND_EN_MASK_SFT (0x1 << 10)
+#define RG_DEM_SPLITTER2_DITHER_EN_SFT 9
+#define RG_DEM_SPLITTER2_DITHER_EN_MASK 0x1
+#define RG_DEM_SPLITTER2_DITHER_EN_MASK_SFT (0x1 << 9)
+#define RG_DEM_SPLITTER1_DITHER_EN_SFT 8
+#define RG_DEM_SPLITTER1_DITHER_EN_MASK 0x1
+#define RG_DEM_SPLITTER1_DITHER_EN_MASK_SFT (0x1 << 8)
+#define RG_DEM_SPLITTER2_DITHER_GAIN_SFT 4
+#define RG_DEM_SPLITTER2_DITHER_GAIN_MASK 0xf
+#define RG_DEM_SPLITTER2_DITHER_GAIN_MASK_SFT (0xf << 4)
+#define RG_DEM_SPLITTER1_DITHER_GAIN_SFT 0
+#define RG_DEM_SPLITTER1_DITHER_GAIN_MASK 0xf
+#define RG_DEM_SPLITTER1_DITHER_GAIN_MASK_SFT (0xf << 0)
+
+/* DEM_RECONSTRUCT_MON */
+#define DEM_RECONSTRUCT_L_MON_SFT 8
+#define DEM_RECONSTRUCT_L_MON_MASK 0xff
+#define DEM_RECONSTRUCT_L_MON_MASK_SFT (0xff << 8)
+#define DEM_RECONSTRUCT_R_MON_SFT 0
+#define DEM_RECONSTRUCT_R_MON_MASK 0xff
+#define DEM_RECONSTRUCT_R_MON_MASK_SFT (0xff << 0)
+
+/* AFE_STF_CON0 */
+#define SLT_CNT_FLAG_RESET_SFT 28
+#define SLT_CNT_FLAG_RESET_MASK 0x1
+#define SLT_CNT_FLAG_RESET_MASK_SFT (0x1 << 28)
+#define SLT_CNT_THD_SFT 16
+#define SLT_CNT_THD_MASK 0xfff
+#define SLT_CNT_THD_MASK_SFT (0xfff << 16)
+#define SIDE_TONE_HALF_TAP_NUM_SFT 4
+#define SIDE_TONE_HALF_TAP_NUM_MASK 0x7f
+#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x7f << 4)
+#define SIDE_TONE_ODD_MODE_SFT 1
+#define SIDE_TONE_ODD_MODE_MASK 0x1
+#define SIDE_TONE_ODD_MODE_MASK_SFT (0x1 << 1)
+#define SIDE_TONE_ON_SFT 0
+#define SIDE_TONE_ON_MASK 0x1
+#define SIDE_TONE_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_STF_CON1 */
+#define SIDE_TONE_IN_EN_SEL_DOMAIN_SFT 5
+#define SIDE_TONE_IN_EN_SEL_DOMAIN_MASK 0x7
+#define SIDE_TONE_IN_EN_SEL_DOMAIN_MASK_SFT (0x7 << 5)
+#define SIDE_TONE_IN_EN_SEL_FS_SFT 0
+#define SIDE_TONE_IN_EN_SEL_FS_MASK 0x1f
+#define SIDE_TONE_IN_EN_SEL_FS_MASK_SFT (0x1f << 0)
+
+/* AFE_STF_COEFF */
+#define SIDE_TONE_COEFFICIENT_R_W_SEL_SFT 24
+#define SIDE_TONE_COEFFICIENT_R_W_SEL_MASK 0x1
+#define SIDE_TONE_COEFFICIENT_R_W_SEL_MASK_SFT (0x1 << 24)
+#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16
+#define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f
+#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16)
+#define SIDE_TONE_COEFFICIENT_SFT 0
+#define SIDE_TONE_COEFFICIENT_MASK 0xffff
+#define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0)
+
+/* AFE_STF_GAIN */
+#define SIDE_TONE_POSITIVE_GAIN_SFT 16
+#define SIDE_TONE_POSITIVE_GAIN_MASK 0x7
+#define SIDE_TONE_POSITIVE_GAIN_MASK_SFT (0x7 << 16)
+#define SIDE_TONE_GAIN_SFT 0
+#define SIDE_TONE_GAIN_MASK 0xffff
+#define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0)
+
+/* AFE_STF_MON */
+#define SIDE_TONE_R_RDY_SFT 30
+#define SIDE_TONE_R_RDY_MASK 0x1
+#define SIDE_TONE_R_RDY_MASK_SFT (0x1 << 30)
+#define SIDE_TONE_W_RDY_SFT 29
+#define SIDE_TONE_W_RDY_MASK 0x1
+#define SIDE_TONE_W_RDY_MASK_SFT (0x1 << 29)
+#define SLT_CNT_FLAG_SFT 28
+#define SLT_CNT_FLAG_MASK 0x1
+#define SLT_CNT_FLAG_MASK_SFT (0x1 << 28)
+#define SLT_CNT_SFT 16
+#define SLT_CNT_MASK 0xfff
+#define SLT_CNT_MASK_SFT (0xfff << 16)
+#define SIDE_TONE_COEFF_SFT 0
+#define SIDE_TONE_COEFF_MASK 0xffff
+#define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0)
+
+/* AFE_STF_IP_VERSION */
+#define SIDE_TONE_IP_VERSION_SFT 0
+#define SIDE_TONE_IP_VERSION_MASK 0xffffffff
+#define SIDE_TONE_IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CM_REG */
+#define AFE_CM_UPDATE_CNT_SFT 16
+#define AFE_CM_UPDATE_CNT_MASK 0x7fff
+#define AFE_CM_UPDATE_CNT_MASK_SFT (0x7fff << 16)
+#define AFE_CM_1X_EN_SEL_FS_SFT 8
+#define AFE_CM_1X_EN_SEL_FS_MASK 0x1f
+#define AFE_CM_1X_EN_SEL_FS_MASK_SFT (0x1f << 8)
+#define AFE_CM_CH_NUM_SFT 2
+#define AFE_CM_CH_NUM_MASK 0x1f
+#define AFE_CM_CH_NUM_MASK_SFT (0x1f << 2)
+#define AFE_CM_BYTE_SWAP_SFT 1
+#define AFE_CM_BYTE_SWAP_MASK 0x1
+#define AFE_CM_BYTE_SWAP_MASK_SFT (0x1 << 1)
+#define AFE_CM_BYPASS_MODE_SFT 31
+#define AFE_CM_BYPASS_MODE_MASK 0x1
+#define AFE_CM_BYPASS_MODE_MASK_SFT (0x1 << 31)
+
+/* AFE_CM0_CON0 */
+#define AFE_CM0_BYPASS_MODE_SFT 31
+#define AFE_CM0_BYPASS_MODE_MASK 0x1
+#define AFE_CM0_BYPASS_MODE_MASK_SFT (0x1 << 31)
+#define AFE_CM0_UPDATE_CNT_SFT 16
+#define AFE_CM0_UPDATE_CNT_MASK 0x7fff
+#define AFE_CM0_UPDATE_CNT_MASK_SFT (0x7fff << 16)
+#define AFE_CM0_1X_EN_SEL_DOMAIN_SFT 13
+#define AFE_CM0_1X_EN_SEL_DOMAIN_MASK 0x7
+#define AFE_CM0_1X_EN_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define AFE_CM0_1X_EN_SEL_FS_SFT 8
+#define AFE_CM0_1X_EN_SEL_FS_MASK 0x1f
+#define AFE_CM0_1X_EN_SEL_FS_MASK_SFT (0x1f << 8)
+#define AFE_CM0_OUTPUT_MUX_SFT 7
+#define AFE_CM0_OUTPUT_MUX_MASK 0x1
+#define AFE_CM0_OUTPUT_MUX_MASK_SFT (0x1 << 7)
+#define AFE_CM0_CH_NUM_SFT 2
+#define AFE_CM0_CH_NUM_MASK 0x1f
+#define AFE_CM0_CH_NUM_MASK_SFT (0x1f << 2)
+#define AFE_CM0_BYTE_SWAP_SFT 1
+#define AFE_CM0_BYTE_SWAP_MASK 0x1
+#define AFE_CM0_BYTE_SWAP_MASK_SFT (0x1 << 1)
+#define AFE_CM0_ON_SFT 0
+#define AFE_CM0_ON_MASK 0x1
+#define AFE_CM0_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_CM0_MON */
+#define AFE_CM0_BYPASS_MODE_MON_SFT 31
+#define AFE_CM0_BYPASS_MODE_MON_MASK 0x1
+#define AFE_CM0_BYPASS_MODE_MON_MASK_SFT (0x1 << 31)
+#define AFE_CM0_OUTPUT_CNT_MON_SFT 16
+#define AFE_CM0_OUTPUT_CNT_MON_MASK 0x7fff
+#define AFE_CM0_OUTPUT_CNT_MON_MASK_SFT (0x7fff << 16)
+#define AFE_CM0_CUR_CHSET_MON_SFT 5
+#define AFE_CM0_CUR_CHSET_MON_MASK 0xf
+#define AFE_CM0_CUR_CHSET_MON_MASK_SFT (0xf << 5)
+#define AFE_CM0_ODD_FLAG_MON_SFT 4
+#define AFE_CM0_ODD_FLAG_MON_MASK 0x1
+#define AFE_CM0_ODD_FLAG_MON_MASK_SFT (0x1 << 4)
+#define AFE_CM0_BYTE_SWAP_MON_SFT 1
+#define AFE_CM0_BYTE_SWAP_MON_MASK 0x1
+#define AFE_CM0_BYTE_SWAP_MON_MASK_SFT (0x1 << 1)
+#define AFE_CM0_ON_MON_SFT 0
+#define AFE_CM0_ON_MON_MASK 0x1
+#define AFE_CM0_ON_MON_MASK_SFT (0x1 << 0)
+
+/* AFE_CM0_IP_VERSION */
+#define AFE_CM0_IP_VERSION_SFT 0
+#define AFE_CM0_IP_VERSION_MASK 0xffffffff
+#define AFE_CM0_IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CM1_CON0 */
+#define AFE_CM1_BYPASS_MODE_SFT 31
+#define AFE_CM1_BYPASS_MODE_MASK 0x1
+#define AFE_CM1_BYPASS_MODE_MASK_SFT (0x1 << 31)
+#define AFE_CM1_UPDATE_CNT_SFT 16
+#define AFE_CM1_UPDATE_CNT_MASK 0x7fff
+#define AFE_CM1_UPDATE_CNT_MASK_SFT (0x7fff << 16)
+#define AFE_CM1_1X_EN_SEL_DOMAIN_SFT 13
+#define AFE_CM1_1X_EN_SEL_DOMAIN_MASK 0x7
+#define AFE_CM1_1X_EN_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define AFE_CM1_1X_EN_SEL_FS_SFT 8
+#define AFE_CM1_1X_EN_SEL_FS_MASK 0x1f
+#define AFE_CM1_1X_EN_SEL_FS_MASK_SFT (0x1f << 8)
+#define AFE_CM1_OUTPUT_MUX_SFT 7
+#define AFE_CM1_OUTPUT_MUX_MASK 0x1
+#define AFE_CM1_OUTPUT_MUX_MASK_SFT (0x1 << 7)
+#define AFE_CM1_CH_NUM_SFT 2
+#define AFE_CM1_CH_NUM_MASK 0x1f
+#define AFE_CM1_CH_NUM_MASK_SFT (0x1f << 2)
+#define AFE_CM1_BYTE_SWAP_SFT 1
+#define AFE_CM1_BYTE_SWAP_MASK 0x1
+#define AFE_CM1_BYTE_SWAP_MASK_SFT (0x1 << 1)
+#define AFE_CM1_ON_SFT 0
+#define AFE_CM1_ON_MASK 0x1
+#define AFE_CM1_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_CM1_MON */
+#define AFE_CM1_BYPASS_MODE_MON_SFT 31
+#define AFE_CM1_BYPASS_MODE_MON_MASK 0x1
+#define AFE_CM1_BYPASS_MODE_MON_MASK_SFT (0x1 << 31)
+#define AFE_CM1_OUTPUT_CNT_MON_SFT 16
+#define AFE_CM1_OUTPUT_CNT_MON_MASK 0x7fff
+#define AFE_CM1_OUTPUT_CNT_MON_MASK_SFT (0x7fff << 16)
+#define AFE_CM1_CUR_CHSET_MON_SFT 5
+#define AFE_CM1_CUR_CHSET_MON_MASK 0xf
+#define AFE_CM1_CUR_CHSET_MON_MASK_SFT (0xf << 5)
+#define AFE_CM1_ODD_FLAG_MON_SFT 4
+#define AFE_CM1_ODD_FLAG_MON_MASK 0x1
+#define AFE_CM1_ODD_FLAG_MON_MASK_SFT (0x1 << 4)
+#define AFE_CM1_BYTE_SWAP_MON_SFT 1
+#define AFE_CM1_BYTE_SWAP_MON_MASK 0x1
+#define AFE_CM1_BYTE_SWAP_MON_MASK_SFT (0x1 << 1)
+#define AFE_CM1_ON_MON_SFT 0
+#define AFE_CM1_ON_MON_MASK 0x1
+#define AFE_CM1_ON_MON_MASK_SFT (0x1 << 0)
+
+/* AFE_CM1_IP_VERSION */
+#define AFE_CM1_IP_VERSION_SFT 0
+#define AFE_CM1_IP_VERSION_MASK 0xffffffff
+#define AFE_CM1_IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_SRC_CON0 */
+#define ULCF_CFG_EN_CTL_SFT 31
+#define ULCF_CFG_EN_CTL_MASK 0x1
+#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)
+#define UL_DMIC_PHASE_SEL_CH1_SFT 27
+#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7
+#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27)
+#define UL_DMIC_PHASE_SEL_CH2_SFT 24
+#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7
+#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24)
+#define UL_DMIC_TWO_WIRE_CTL_SFT 23
+#define UL_DMIC_TWO_WIRE_CTL_MASK 0x1
+#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT (0x1 << 23)
+#define UL_MODE_3P25M_CH2_CTL_SFT 22
+#define UL_MODE_3P25M_CH2_CTL_MASK 0x1
+#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
+#define UL_MODE_3P25M_CH1_CTL_SFT 21
+#define UL_MODE_3P25M_CH1_CTL_MASK 0x1
+#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
+#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)
+#define UL_AP_DMIC_ON_SFT 16
+#define UL_AP_DMIC_ON_MASK 0x1
+#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16)
+#define DMIC_LOW_POWER_MODE_CTL_SFT 14
+#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
+#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
+#define UL_DISABLE_HW_CG_CTL_SFT 12
+#define UL_DISABLE_HW_CG_CTL_MASK 0x1
+#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
+#define AMIC_26M_SEL_CTL_SFT 11
+#define AMIC_26M_SEL_CTL_MASK 0x1
+#define AMIC_26M_SEL_CTL_MASK_SFT (0x1 << 11)
+#define UL_IIR_ON_TMP_CTL_SFT 10
+#define UL_IIR_ON_TMP_CTL_MASK 0x1
+#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
+#define UL_IIRMODE_CTL_SFT 7
+#define UL_IIRMODE_CTL_MASK 0x7
+#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)
+#define DIGMIC_4P33M_SEL_SFT 6
+#define DIGMIC_4P33M_SEL_MASK 0x1
+#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6)
+#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
+#define AMIC_6P5M_SEL_CTL_SFT 4
+#define AMIC_6P5M_SEL_CTL_MASK 0x1
+#define AMIC_6P5M_SEL_CTL_MASK_SFT (0x1 << 4)
+#define AMIC_1P625M_SEL_CTL_SFT 3
+#define AMIC_1P625M_SEL_CTL_MASK 0x1
+#define AMIC_1P625M_SEL_CTL_MASK_SFT (0x1 << 3)
+#define UL_LOOP_BACK_MODE_CTL_SFT 2
+#define UL_LOOP_BACK_MODE_CTL_MASK 0x1
+#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
+#define UL_SDM_3_LEVEL_CTL_SFT 1
+#define UL_SDM_3_LEVEL_CTL_MASK 0x1
+#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
+#define UL_SRC_ON_TMP_CTL_SFT 0
+#define UL_SRC_ON_TMP_CTL_MASK 0x1
+#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_UL0_SRC_CON1 */
+#define ADDA_UL_GAIN_VALUE_SFT 16
+#define ADDA_UL_GAIN_VALUE_MASK 0xffff
+#define ADDA_UL_GAIN_VALUE_MASK_SFT (0xffff << 16)
+#define ADDA_UL_POSTIVEGAIN_SFT 12
+#define ADDA_UL_POSTIVEGAIN_MASK 0x7
+#define ADDA_UL_POSTIVEGAIN_MASK_SFT (0x7 << 12)
+#define ADDA_UL_ODDTAP_MODE_SFT 11
+#define ADDA_UL_ODDTAP_MODE_MASK 0x1
+#define ADDA_UL_ODDTAP_MODE_MASK_SFT (0x1 << 11)
+#define ADDA_UL_HALF_TAP_NUM_SFT 5
+#define ADDA_UL_HALF_TAP_NUM_MASK 0x3f
+#define ADDA_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 5)
+#define FIFO_SOFT_RST_SFT 4
+#define FIFO_SOFT_RST_MASK 0x1
+#define FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
+#define FIFO_SOFT_RST_EN_SFT 3
+#define FIFO_SOFT_RST_EN_MASK 0x1
+#define FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 3)
+#define LR_SWAP_SFT 2
+#define LR_SWAP_MASK 0x1
+#define LR_SWAP_MASK_SFT (0x1 << 2)
+#define GAIN_MODE_SFT 0
+#define GAIN_MODE_MASK 0x3
+#define GAIN_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_ADDA_UL0_SRC_CON2 */
+#define C_DAC_EN_CTL_SFT 27
+#define C_DAC_EN_CTL_MASK 0x1
+#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
+#define C_MUTE_SW_CTL_SFT 26
+#define C_MUTE_SW_CTL_MASK 0x1
+#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
+#define C_AMP_DIV_CH2_CTL_SFT 21
+#define C_AMP_DIV_CH2_CTL_MASK 0x7
+#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)
+#define C_FREQ_DIV_CH2_CTL_SFT 16
+#define C_FREQ_DIV_CH2_CTL_MASK 0x1f
+#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)
+#define C_SINE_MODE_CH2_CTL_SFT 12
+#define C_SINE_MODE_CH2_CTL_MASK 0xf
+#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)
+#define C_AMP_DIV_CH1_CTL_SFT 9
+#define C_AMP_DIV_CH1_CTL_MASK 0x7
+#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)
+#define C_FREQ_DIV_CH1_CTL_SFT 4
+#define C_FREQ_DIV_CH1_CTL_MASK 0x1f
+#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)
+#define C_SINE_MODE_CH1_CTL_SFT 0
+#define C_SINE_MODE_CH1_CTL_MASK 0xf
+#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)
+
+/* AFE_ADDA_UL0_SRC_DEBUG */
+#define UL_SLT_CNT_FLAG_RESET_CTL_SFT 16
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 16)
+#define FIFO_DIGMIC_TESTIN_SFT 12
+#define FIFO_DIGMIC_TESTIN_MASK 0x3
+#define FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 12)
+#define FIFO_DIGMIC_WDATA_TESTEN_SFT 11
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 11)
+#define SLT_CNT_THD_CTL_SFT 0
+#define SLT_CNT_THD_CTL_MASK 0x7ff
+#define SLT_CNT_THD_CTL_MASK_SFT (0x7ff << 0)
+
+/* AFE_ADDA_UL0_SRC_DEBUG_MON0 */
+#define SLT_CNT_FLAG_CTL_SFT 16
+#define SLT_CNT_FLAG_CTL_MASK 0x1
+#define SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 16)
+#define SLT_COUNTER_CTL_SFT 0
+#define SLT_COUNTER_CTL_MASK 0x7ff
+#define SLT_COUNTER_CTL_MASK_SFT (0x7ff << 0)
+
+/* AFE_ADDA_UL0_SRC_MON1 */
+#define UL_VOICE_MODE_CTL_SFT 29
+#define UL_VOICE_MODE_CTL_MASK 0x7
+#define UL_VOICE_MODE_CTL_MASK_SFT (0x7 << 29)
+#define DATA_COMB_IN_CH2_SFT 24
+#define DATA_COMB_IN_CH2_MASK 0x1f
+#define DATA_COMB_IN_CH2_MASK_SFT (0x1f << 24)
+#define DATA_COMB_OUT_CH2_SFT 0
+#define DATA_COMB_OUT_CH2_MASK 0xffffff
+#define DATA_COMB_OUT_CH2_MASK_SFT (0xffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_02_01 */
+#define ADDA_IIR_COEF_02_01_SFT 0
+#define ADDA_IIR_COEF_02_01_MASK 0xffffffff
+#define ADDA_IIR_COEF_02_01_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_04_03 */
+#define ADDA_IIR_COEF_04_03_SFT 0
+#define ADDA_IIR_COEF_04_03_MASK 0xffffffff
+#define ADDA_IIR_COEF_04_03_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_06_05 */
+#define ADDA_IIR_COEF_06_05_SFT 0
+#define ADDA_IIR_COEF_06_05_MASK 0xffffffff
+#define ADDA_IIR_COEF_06_05_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_08_07 */
+#define ADDA_IIR_COEF_08_07_SFT 0
+#define ADDA_IIR_COEF_08_07_MASK 0xffffffff
+#define ADDA_IIR_COEF_08_07_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IIR_COEF_10_09 */
+#define ADDA_IIR_COEF_10_09_SFT 0
+#define ADDA_IIR_COEF_10_09_MASK 0xffffffff
+#define ADDA_IIR_COEF_10_09_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_02_01 */
+#define ADDA_ULCF_CFG_02_01_SFT 0
+#define ADDA_ULCF_CFG_02_01_MASK 0xffffffff
+#define ADDA_ULCF_CFG_02_01_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_04_03 */
+#define ADDA_ULCF_CFG_04_03_SFT 0
+#define ADDA_ULCF_CFG_04_03_MASK 0xffffffff
+#define ADDA_ULCF_CFG_04_03_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_06_05 */
+#define ADDA_ULCF_CFG_06_05_SFT 0
+#define ADDA_ULCF_CFG_06_05_MASK 0xffffffff
+#define ADDA_ULCF_CFG_06_05_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_08_07 */
+#define ADDA_ULCF_CFG_08_07_SFT 0
+#define ADDA_ULCF_CFG_08_07_MASK 0xffffffff
+#define ADDA_ULCF_CFG_08_07_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_10_09 */
+#define ADDA_ULCF_CFG_10_09_SFT 0
+#define ADDA_ULCF_CFG_10_09_MASK 0xffffffff
+#define ADDA_ULCF_CFG_10_09_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_12_11 */
+#define ADDA_ULCF_CFG_12_11_SFT 0
+#define ADDA_ULCF_CFG_12_11_MASK 0xffffffff
+#define ADDA_ULCF_CFG_12_11_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_14_13 */
+#define ADDA_ULCF_CFG_14_13_SFT 0
+#define ADDA_ULCF_CFG_14_13_MASK 0xffffffff
+#define ADDA_ULCF_CFG_14_13_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_16_15 */
+#define ADDA_ULCF_CFG_16_15_SFT 0
+#define ADDA_ULCF_CFG_16_15_MASK 0xffffffff
+#define ADDA_ULCF_CFG_16_15_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_18_17 */
+#define ADDA_ULCF_CFG_18_17_SFT 0
+#define ADDA_ULCF_CFG_18_17_MASK 0xffffffff
+#define ADDA_ULCF_CFG_18_17_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_20_19 */
+#define ADDA_ULCF_CFG_20_19_SFT 0
+#define ADDA_ULCF_CFG_20_19_MASK 0xffffffff
+#define ADDA_ULCF_CFG_20_19_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_22_21 */
+#define ADDA_ULCF_CFG_22_21_SFT 0
+#define ADDA_ULCF_CFG_22_21_MASK 0xffffffff
+#define ADDA_ULCF_CFG_22_21_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_24_23 */
+#define ADDA_ULCF_CFG_24_23_SFT 0
+#define ADDA_ULCF_CFG_24_23_MASK 0xffffffff
+#define ADDA_ULCF_CFG_24_23_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_26_25 */
+#define ADDA_ULCF_CFG_26_25_SFT 0
+#define ADDA_ULCF_CFG_26_25_MASK 0xffffffff
+#define ADDA_ULCF_CFG_26_25_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_28_27 */
+#define ADDA_ULCF_CFG_28_27_SFT 0
+#define ADDA_ULCF_CFG_28_27_MASK 0xffffffff
+#define ADDA_ULCF_CFG_28_27_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_30_29 */
+#define ADDA_ULCF_CFG_30_29_SFT 0
+#define ADDA_ULCF_CFG_30_29_MASK 0xffffffff
+#define ADDA_ULCF_CFG_30_29_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_ULCF_CFG_32_31 */
+#define ADDA_ULCF_CFG_32_31_SFT 0
+#define ADDA_ULCF_CFG_32_31_MASK 0xffffffff
+#define ADDA_ULCF_CFG_32_31_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_IP_VERSION */
+#define ADDA_ULCF_IP_VERSION_SFT 0
+#define ADDA_ULCF_IP_VERSION_MASK 0xffffffff
+#define ADDA_ULCF_IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_SRC_CON0 */
+#define ULCF_CFG_EN_CTL_SFT 31
+#define ULCF_CFG_EN_CTL_MASK 0x1
+#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)
+#define UL_DMIC_PHASE_SEL_CH1_SFT 27
+#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7
+#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27)
+#define UL_DMIC_PHASE_SEL_CH2_SFT 24
+#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7
+#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24)
+#define UL_DMIC_TWO_WIRE_CTL_SFT 23
+#define UL_DMIC_TWO_WIRE_CTL_MASK 0x1
+#define UL_DMIC_TWO_WIRE_CTL_MASK_SFT (0x1 << 23)
+#define UL_MODE_3P25M_CH2_CTL_SFT 22
+#define UL_MODE_3P25M_CH2_CTL_MASK 0x1
+#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
+#define UL_MODE_3P25M_CH1_CTL_SFT 21
+#define UL_MODE_3P25M_CH1_CTL_MASK 0x1
+#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
+#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7
+#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)
+#define UL_AP_DMIC_ON_SFT 16
+#define UL_AP_DMIC_ON_MASK 0x1
+#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16)
+#define DMIC_LOW_POWER_MODE_CTL_SFT 14
+#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
+#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
+#define UL_DISABLE_HW_CG_CTL_SFT 12
+#define UL_DISABLE_HW_CG_CTL_MASK 0x1
+#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
+#define AMIC_26M_SEL_CTL_SFT 11
+#define AMIC_26M_SEL_CTL_MASK 0x1
+#define AMIC_26M_SEL_CTL_MASK_SFT (0x1 << 11)
+#define UL_IIR_ON_TMP_CTL_SFT 10
+#define UL_IIR_ON_TMP_CTL_MASK 0x1
+#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
+#define UL_IIRMODE_CTL_SFT 7
+#define UL_IIRMODE_CTL_MASK 0x7
+#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)
+#define DIGMIC_4P33M_SEL_SFT 6
+#define DIGMIC_4P33M_SEL_MASK 0x1
+#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6)
+#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
+#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
+#define AMIC_6P5M_SEL_CTL_SFT 4
+#define AMIC_6P5M_SEL_CTL_MASK 0x1
+#define AMIC_6P5M_SEL_CTL_MASK_SFT (0x1 << 4)
+#define AMIC_1P625M_SEL_CTL_SFT 3
+#define AMIC_1P625M_SEL_CTL_MASK 0x1
+#define AMIC_1P625M_SEL_CTL_MASK_SFT (0x1 << 3)
+#define UL_LOOP_BACK_MODE_CTL_SFT 2
+#define UL_LOOP_BACK_MODE_CTL_MASK 0x1
+#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
+#define UL_SDM_3_LEVEL_CTL_SFT 1
+#define UL_SDM_3_LEVEL_CTL_MASK 0x1
+#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
+#define UL_SRC_ON_TMP_CTL_SFT 0
+#define UL_SRC_ON_TMP_CTL_MASK 0x1
+#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_UL1_SRC_CON1 */
+#define ADDA_UL_GAIN_VALUE_SFT 16
+#define ADDA_UL_GAIN_VALUE_MASK 0xffff
+#define ADDA_UL_GAIN_VALUE_MASK_SFT (0xffff << 16)
+#define ADDA_UL_POSTIVEGAIN_SFT 12
+#define ADDA_UL_POSTIVEGAIN_MASK 0x7
+#define ADDA_UL_POSTIVEGAIN_MASK_SFT (0x7 << 12)
+#define ADDA_UL_ODDTAP_MODE_SFT 11
+#define ADDA_UL_ODDTAP_MODE_MASK 0x1
+#define ADDA_UL_ODDTAP_MODE_MASK_SFT (0x1 << 11)
+#define ADDA_UL_HALF_TAP_NUM_SFT 5
+#define ADDA_UL_HALF_TAP_NUM_MASK 0x3f
+#define ADDA_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 5)
+#define FIFO_SOFT_RST_SFT 4
+#define FIFO_SOFT_RST_MASK 0x1
+#define FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
+#define FIFO_SOFT_RST_EN_SFT 3
+#define FIFO_SOFT_RST_EN_MASK 0x1
+#define FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 3)
+#define LR_SWAP_SFT 2
+#define LR_SWAP_MASK 0x1
+#define LR_SWAP_MASK_SFT (0x1 << 2)
+#define GAIN_MODE_SFT 0
+#define GAIN_MODE_MASK 0x3
+#define GAIN_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_ADDA_UL1_SRC_CON2 */
+#define C_DAC_EN_CTL_SFT 27
+#define C_DAC_EN_CTL_MASK 0x1
+#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
+#define C_MUTE_SW_CTL_SFT 26
+#define C_MUTE_SW_CTL_MASK 0x1
+#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
+#define C_AMP_DIV_CH2_CTL_SFT 21
+#define C_AMP_DIV_CH2_CTL_MASK 0x7
+#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)
+#define C_FREQ_DIV_CH2_CTL_SFT 16
+#define C_FREQ_DIV_CH2_CTL_MASK 0x1f
+#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)
+#define C_SINE_MODE_CH2_CTL_SFT 12
+#define C_SINE_MODE_CH2_CTL_MASK 0xf
+#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)
+#define C_AMP_DIV_CH1_CTL_SFT 9
+#define C_AMP_DIV_CH1_CTL_MASK 0x7
+#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)
+#define C_FREQ_DIV_CH1_CTL_SFT 4
+#define C_FREQ_DIV_CH1_CTL_MASK 0x1f
+#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)
+#define C_SINE_MODE_CH1_CTL_SFT 0
+#define C_SINE_MODE_CH1_CTL_MASK 0xf
+#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)
+
+/* AFE_ADDA_UL1_SRC_DEBUG */
+#define UL_SLT_CNT_FLAG_RESET_CTL_SFT 16
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1
+#define UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 16)
+#define FIFO_DIGMIC_TESTIN_SFT 12
+#define FIFO_DIGMIC_TESTIN_MASK 0x3
+#define FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 12)
+#define FIFO_DIGMIC_WDATA_TESTEN_SFT 11
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
+#define FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 11)
+#define SLT_CNT_THD_CTL_SFT 0
+#define SLT_CNT_THD_CTL_MASK 0x7ff
+#define SLT_CNT_THD_CTL_MASK_SFT (0x7ff << 0)
+
+/* AFE_ADDA_UL1_SRC_DEBUG_MON0 */
+#define SLT_CNT_FLAG_CTL_SFT 16
+#define SLT_CNT_FLAG_CTL_MASK 0x1
+#define SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 16)
+#define SLT_COUNTER_CTL_SFT 0
+#define SLT_COUNTER_CTL_MASK 0x7ff
+#define SLT_COUNTER_CTL_MASK_SFT (0x7ff << 0)
+
+/* AFE_ADDA_UL1_SRC_MON1 */
+#define UL_VOICE_MODE_CTL_SFT 29
+#define UL_VOICE_MODE_CTL_MASK 0x7
+#define UL_VOICE_MODE_CTL_MASK_SFT (0x7 << 29)
+#define DATA_COMB_IN_CH2_SFT 24
+#define DATA_COMB_IN_CH2_MASK 0x1f
+#define DATA_COMB_IN_CH2_MASK_SFT (0x1f << 24)
+#define DATA_COMB_OUT_CH2_SFT 0
+#define DATA_COMB_OUT_CH2_MASK 0xffffff
+#define DATA_COMB_OUT_CH2_MASK_SFT (0xffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_02_01 */
+#define ADDA_IIR_COEF_02_01_SFT 0
+#define ADDA_IIR_COEF_02_01_MASK 0xffffffff
+#define ADDA_IIR_COEF_02_01_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_04_03 */
+#define ADDA_IIR_COEF_04_03_SFT 0
+#define ADDA_IIR_COEF_04_03_MASK 0xffffffff
+#define ADDA_IIR_COEF_04_03_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_06_05 */
+#define ADDA_IIR_COEF_06_05_SFT 0
+#define ADDA_IIR_COEF_06_05_MASK 0xffffffff
+#define ADDA_IIR_COEF_06_05_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_08_07 */
+#define ADDA_IIR_COEF_08_07_SFT 0
+#define ADDA_IIR_COEF_08_07_MASK 0xffffffff
+#define ADDA_IIR_COEF_08_07_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IIR_COEF_10_09 */
+#define ADDA_IIR_COEF_10_09_SFT 0
+#define ADDA_IIR_COEF_10_09_MASK 0xffffffff
+#define ADDA_IIR_COEF_10_09_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_02_01 */
+#define ADDA_ULCF_CFG_02_01_SFT 0
+#define ADDA_ULCF_CFG_02_01_MASK 0xffffffff
+#define ADDA_ULCF_CFG_02_01_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_04_03 */
+#define ADDA_ULCF_CFG_04_03_SFT 0
+#define ADDA_ULCF_CFG_04_03_MASK 0xffffffff
+#define ADDA_ULCF_CFG_04_03_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_06_05 */
+#define ADDA_ULCF_CFG_06_05_SFT 0
+#define ADDA_ULCF_CFG_06_05_MASK 0xffffffff
+#define ADDA_ULCF_CFG_06_05_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_08_07 */
+#define ADDA_ULCF_CFG_08_07_SFT 0
+#define ADDA_ULCF_CFG_08_07_MASK 0xffffffff
+#define ADDA_ULCF_CFG_08_07_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_10_09 */
+#define ADDA_ULCF_CFG_10_09_SFT 0
+#define ADDA_ULCF_CFG_10_09_MASK 0xffffffff
+#define ADDA_ULCF_CFG_10_09_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_12_11 */
+#define ADDA_ULCF_CFG_12_11_SFT 0
+#define ADDA_ULCF_CFG_12_11_MASK 0xffffffff
+#define ADDA_ULCF_CFG_12_11_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_14_13 */
+#define ADDA_ULCF_CFG_14_13_SFT 0
+#define ADDA_ULCF_CFG_14_13_MASK 0xffffffff
+#define ADDA_ULCF_CFG_14_13_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_16_15 */
+#define ADDA_ULCF_CFG_16_15_SFT 0
+#define ADDA_ULCF_CFG_16_15_MASK 0xffffffff
+#define ADDA_ULCF_CFG_16_15_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_18_17 */
+#define ADDA_ULCF_CFG_18_17_SFT 0
+#define ADDA_ULCF_CFG_18_17_MASK 0xffffffff
+#define ADDA_ULCF_CFG_18_17_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_20_19 */
+#define ADDA_ULCF_CFG_20_19_SFT 0
+#define ADDA_ULCF_CFG_20_19_MASK 0xffffffff
+#define ADDA_ULCF_CFG_20_19_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_22_21 */
+#define ADDA_ULCF_CFG_22_21_SFT 0
+#define ADDA_ULCF_CFG_22_21_MASK 0xffffffff
+#define ADDA_ULCF_CFG_22_21_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_24_23 */
+#define ADDA_ULCF_CFG_24_23_SFT 0
+#define ADDA_ULCF_CFG_24_23_MASK 0xffffffff
+#define ADDA_ULCF_CFG_24_23_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_26_25 */
+#define ADDA_ULCF_CFG_26_25_SFT 0
+#define ADDA_ULCF_CFG_26_25_MASK 0xffffffff
+#define ADDA_ULCF_CFG_26_25_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_28_27 */
+#define ADDA_ULCF_CFG_28_27_SFT 0
+#define ADDA_ULCF_CFG_28_27_MASK 0xffffffff
+#define ADDA_ULCF_CFG_28_27_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_30_29 */
+#define ADDA_ULCF_CFG_30_29_SFT 0
+#define ADDA_ULCF_CFG_30_29_MASK 0xffffffff
+#define ADDA_ULCF_CFG_30_29_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_ULCF_CFG_32_31 */
+#define ADDA_ULCF_CFG_32_31_SFT 0
+#define ADDA_ULCF_CFG_32_31_MASK 0xffffffff
+#define ADDA_ULCF_CFG_32_31_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_IP_VERSION */
+#define ADDA_ULCF_IP_VERSION_SFT 0
+#define ADDA_ULCF_IP_VERSION_MASK 0xffffffff
+#define ADDA_ULCF_IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_PROXIMITY_CON0 */
+#define PROXIMITY_CH1_ON_SFT 12
+#define PROXIMITY_CH1_ON_MASK 0x1
+#define PROXIMITY_CH1_ON_MASK_SFT (0x1 << 12)
+#define PROXIMITY_CH1_SEL_SFT 8
+#define PROXIMITY_CH1_SEL_MASK 0xf
+#define PROXIMITY_CH1_SEL_MASK_SFT (0xf << 8)
+#define PROXIMITY_CH2_ON_SFT 4
+#define PROXIMITY_CH2_ON_MASK 0x1
+#define PROXIMITY_CH2_ON_MASK_SFT (0x1 << 4)
+#define PROXIMITY_CH2_SEL_SFT 0
+#define PROXIMITY_CH2_SEL_MASK 0xf
+#define PROXIMITY_CH2_SEL_MASK_SFT (0xf << 0)
+
+/* AFE_ADDA_ULSRC_PHASE_CON0 */
+#define DMIC1_PHASE_FCLK_SEL_SFT 30
+#define DMIC1_PHASE_FCLK_SEL_MASK 0x3
+#define DMIC1_PHASE_FCLK_SEL_MASK_SFT (0x3 << 30)
+#define DMIC0_PHASE_FCLK_SEL_SFT 28
+#define DMIC0_PHASE_FCLK_SEL_MASK 0x3
+#define DMIC0_PHASE_FCLK_SEL_MASK_SFT (0x3 << 28)
+#define UL3_PHASE_FCLK_SEL_SFT 26
+#define UL3_PHASE_FCLK_SEL_MASK 0x3
+#define UL3_PHASE_FCLK_SEL_MASK_SFT (0x3 << 26)
+#define UL2_PHASE_FCLK_SEL_SFT 24
+#define UL2_PHASE_FCLK_SEL_MASK 0x3
+#define UL2_PHASE_FCLK_SEL_MASK_SFT (0x3 << 24)
+#define UL1_PHASE_FCLK_SEL_SFT 22
+#define UL1_PHASE_FCLK_SEL_MASK 0x3
+#define UL1_PHASE_FCLK_SEL_MASK_SFT (0x3 << 22)
+#define UL0_PHASE_FCLK_SEL_SFT 20
+#define UL0_PHASE_FCLK_SEL_MASK 0x3
+#define UL0_PHASE_FCLK_SEL_MASK_SFT (0x3 << 20)
+#define UL_PHASE_SYNC_FCLK_2_ON_SFT 18
+#define UL_PHASE_SYNC_FCLK_2_ON_MASK 0x1
+#define UL_PHASE_SYNC_FCLK_2_ON_MASK_SFT (0x1 << 18)
+#define UL_PHASE_SYNC_FCLK_1_ON_SFT 17
+#define UL_PHASE_SYNC_FCLK_1_ON_MASK 0x1
+#define UL_PHASE_SYNC_FCLK_1_ON_MASK_SFT (0x1 << 17)
+#define UL_PHASE_SYNC_FCLK_0_ON_SFT 16
+#define UL_PHASE_SYNC_FCLK_0_ON_MASK 0x1
+#define UL_PHASE_SYNC_FCLK_0_ON_MASK_SFT (0x1 << 16)
+#define DMIC1_PHASE_HCLK_SEL_SFT 14
+#define DMIC1_PHASE_HCLK_SEL_MASK 0x3
+#define DMIC1_PHASE_HCLK_SEL_MASK_SFT (0x3 << 14)
+#define DMIC0_PHASE_HCLK_SEL_SFT 12
+#define DMIC0_PHASE_HCLK_SEL_MASK 0x3
+#define DMIC0_PHASE_HCLK_SEL_MASK_SFT (0x3 << 12)
+#define UL3_PHASE_HCLK_SEL_SFT 10
+#define UL3_PHASE_HCLK_SEL_MASK 0x3
+#define UL3_PHASE_HCLK_SEL_MASK_SFT (0x3 << 10)
+#define UL2_PHASE_HCLK_SEL_SFT 8
+#define UL2_PHASE_HCLK_SEL_MASK 0x3
+#define UL2_PHASE_HCLK_SEL_MASK_SFT (0x3 << 8)
+#define UL1_PHASE_HCLK_SEL_SFT 6
+#define UL1_PHASE_HCLK_SEL_MASK 0x3
+#define UL1_PHASE_HCLK_SEL_MASK_SFT (0x3 << 6)
+#define UL0_PHASE_HCLK_SEL_SFT 4
+#define UL0_PHASE_HCLK_SEL_MASK 0x3
+#define UL0_PHASE_HCLK_SEL_MASK_SFT (0x3 << 4)
+#define UL_PHASE_SYNC_HCLK_2_ON_SFT 2
+#define UL_PHASE_SYNC_HCLK_2_ON_MASK 0x1
+#define UL_PHASE_SYNC_HCLK_2_ON_MASK_SFT (0x1 << 2)
+#define UL_PHASE_SYNC_HCLK_1_ON_SFT 1
+#define UL_PHASE_SYNC_HCLK_1_ON_MASK 0x1
+#define UL_PHASE_SYNC_HCLK_1_ON_MASK_SFT (0x1 << 1)
+#define UL_PHASE_SYNC_HCLK_0_ON_SFT 0
+#define UL_PHASE_SYNC_HCLK_0_ON_MASK 0x1
+#define UL_PHASE_SYNC_HCLK_0_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_ULSRC_PHASE_CON1 */
+#define DMIC_CLK_PHASE_SYNC_SET_SFT 31
+#define DMIC_CLK_PHASE_SYNC_SET_MASK 0x1
+#define DMIC_CLK_PHASE_SYNC_SET_MASK_SFT (0x1 << 31)
+#define DMIC1_PHASE_SYNC_FCLK_SET_SFT 11
+#define DMIC1_PHASE_SYNC_FCLK_SET_MASK 0x1
+#define DMIC1_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 11)
+#define DMIC1_PHASE_SYNC_HCLK_SET_SFT 10
+#define DMIC1_PHASE_SYNC_HCLK_SET_MASK 0x1
+#define DMIC1_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 10)
+#define DMIC0_PHASE_SYNC_FCLK_SET_SFT 9
+#define DMIC0_PHASE_SYNC_FCLK_SET_MASK 0x1
+#define DMIC0_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 9)
+#define DMIC0_PHASE_SYNC_HCLK_SET_SFT 8
+#define DMIC0_PHASE_SYNC_HCLK_SET_MASK 0x1
+#define DMIC0_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 8)
+#define UL3_PHASE_SYNC_FCLK_SET_SFT 7
+#define UL3_PHASE_SYNC_FCLK_SET_MASK 0x1
+#define UL3_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 7)
+#define UL3_PHASE_SYNC_HCLK_SET_SFT 6
+#define UL3_PHASE_SYNC_HCLK_SET_MASK 0x1
+#define UL3_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 6)
+#define UL2_PHASE_SYNC_FCLK_SET_SFT 5
+#define UL2_PHASE_SYNC_FCLK_SET_MASK 0x1
+#define UL2_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 5)
+#define UL2_PHASE_SYNC_HCLK_SET_SFT 4
+#define UL2_PHASE_SYNC_HCLK_SET_MASK 0x1
+#define UL2_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 4)
+#define UL1_PHASE_SYNC_FCLK_SET_SFT 3
+#define UL1_PHASE_SYNC_FCLK_SET_MASK 0x1
+#define UL1_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 3)
+#define UL1_PHASE_SYNC_HCLK_SET_SFT 2
+#define UL1_PHASE_SYNC_HCLK_SET_MASK 0x1
+#define UL1_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 2)
+#define UL0_PHASE_SYNC_FCLK_SET_SFT 1
+#define UL0_PHASE_SYNC_FCLK_SET_MASK 0x1
+#define UL0_PHASE_SYNC_FCLK_SET_MASK_SFT (0x1 << 1)
+#define UL0_PHASE_SYNC_HCLK_SET_SFT 0
+#define UL0_PHASE_SYNC_HCLK_SET_MASK 0x1
+#define UL0_PHASE_SYNC_HCLK_SET_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_ULSRC_PHASE_CON2 */
+#define DMIC1_PHASE_SYNC_1X_EN_SEL_SFT 26
+#define DMIC1_PHASE_SYNC_1X_EN_SEL_MASK 0x3
+#define DMIC1_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 26)
+#define DMIC0_PHASE_SYNC_1X_EN_SEL_SFT 24
+#define DMIC0_PHASE_SYNC_1X_EN_SEL_MASK 0x3
+#define DMIC0_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 24)
+#define UL3_PHASE_SYNC_1X_EN_SEL_SFT 22
+#define UL3_PHASE_SYNC_1X_EN_SEL_MASK 0x3
+#define UL3_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 22)
+#define UL2_PHASE_SYNC_1X_EN_SEL_SFT 20
+#define UL2_PHASE_SYNC_1X_EN_SEL_MASK 0x3
+#define UL2_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 20)
+#define UL1_PHASE_SYNC_1X_EN_SEL_SFT 18
+#define UL1_PHASE_SYNC_1X_EN_SEL_MASK 0x3
+#define UL1_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 18)
+#define UL0_PHASE_SYNC_1X_EN_SEL_SFT 16
+#define UL0_PHASE_SYNC_1X_EN_SEL_MASK 0x3
+#define UL0_PHASE_SYNC_1X_EN_SEL_MASK_SFT (0x3 << 16)
+#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_SFT 5
+#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_MASK 0x1
+#define UL_PHASE_SYNC_FCLK_1X_EN_2_ON_MASK_SFT (0x1 << 5)
+#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_SFT 4
+#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_MASK 0x1
+#define UL_PHASE_SYNC_FCLK_1X_EN_1_ON_MASK_SFT (0x1 << 4)
+#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_SFT 3
+#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_MASK 0x1
+#define UL_PHASE_SYNC_FCLK_1X_EN_0_ON_MASK_SFT (0x1 << 3)
+#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_SFT 2
+#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_MASK 0x1
+#define UL_PHASE_SYNC_HCLK_1X_EN_2_ON_MASK_SFT (0x1 << 2)
+#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_SFT 1
+#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_MASK 0x1
+#define UL_PHASE_SYNC_HCLK_1X_EN_1_ON_MASK_SFT (0x1 << 1)
+#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_SFT 0
+#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_MASK 0x1
+#define UL_PHASE_SYNC_HCLK_1X_EN_0_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_ULSRC_PHASE_CON3 */
+#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_SFT 26
+#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
+#define DMIC1_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 26)
+#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_SFT 24
+#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
+#define DMIC0_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 24)
+#define UL3_PHASE_SYNC_SOFT_RST_SEL_SFT 22
+#define UL3_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
+#define UL3_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 22)
+#define UL2_PHASE_SYNC_SOFT_RST_SEL_SFT 20
+#define UL2_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
+#define UL2_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 20)
+#define UL1_PHASE_SYNC_SOFT_RST_SEL_SFT 18
+#define UL1_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
+#define UL1_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 18)
+#define UL0_PHASE_SYNC_SOFT_RST_SEL_SFT 16
+#define UL0_PHASE_SYNC_SOFT_RST_SEL_MASK 0x3
+#define UL0_PHASE_SYNC_SOFT_RST_SEL_MASK_SFT (0x3 << 16)
+#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_SFT 13
+#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
+#define DMIC1_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 13)
+#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_SFT 12
+#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
+#define DMIC0_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 12)
+#define UL3_PHASE_SYNC_CH1_FIFO_SEL_SFT 11
+#define UL3_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
+#define UL3_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 11)
+#define UL2_PHASE_SYNC_CH1_FIFO_SEL_SFT 10
+#define UL2_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
+#define UL2_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 10)
+#define UL1_PHASE_SYNC_CH1_FIFO_SEL_SFT 9
+#define UL1_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
+#define UL1_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 9)
+#define UL0_PHASE_SYNC_CH1_FIFO_SEL_SFT 8
+#define UL0_PHASE_SYNC_CH1_FIFO_SEL_MASK 0x1
+#define UL0_PHASE_SYNC_CH1_FIFO_SEL_MASK_SFT (0x1 << 8)
+#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_SFT 5
+#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_MASK 0x1
+#define UL_PHASE_SYNC_SOFT_RST_EN_2_ON_MASK_SFT (0x1 << 5)
+#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_SFT 4
+#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_MASK 0x1
+#define UL_PHASE_SYNC_SOFT_RST_EN_1_ON_MASK_SFT (0x1 << 4)
+#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_SFT 3
+#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_MASK 0x1
+#define UL_PHASE_SYNC_SOFT_RST_EN_0_ON_MASK_SFT (0x1 << 3)
+#define UL_PHASE_SYNC_SOFT_RST_2_ON_SFT 2
+#define UL_PHASE_SYNC_SOFT_RST_2_ON_MASK 0x1
+#define UL_PHASE_SYNC_SOFT_RST_2_ON_MASK_SFT (0x1 << 2)
+#define UL_PHASE_SYNC_SOFT_RST_1_ON_SFT 1
+#define UL_PHASE_SYNC_SOFT_RST_1_ON_MASK 0x1
+#define UL_PHASE_SYNC_SOFT_RST_1_ON_MASK_SFT (0x1 << 1)
+#define UL_PHASE_SYNC_SOFT_RST_0_ON_SFT 0
+#define UL_PHASE_SYNC_SOFT_RST_0_ON_MASK 0x1
+#define UL_PHASE_SYNC_SOFT_RST_0_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_MTKAIF_IPM_VER_MON */
+#define RG_MTKAIF_IPM_VER_MON_SFT 0
+#define RG_MTKAIF_IPM_VER_MON_MASK 0xffffffff
+#define RG_MTKAIF_IPM_VER_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_MTKAIF_MON_SEL */
+#define RG_MTKAIF_MON_SEL_SFT 0
+#define RG_MTKAIF_MON_SEL_MASK 0xff
+#define RG_MTKAIF_MON_SEL_MASK_SFT (0xff << 0)
+
+/* AFE_MTKAIF_MON */
+#define RG_MTKAIF_MON_SFT 0
+#define RG_MTKAIF_MON_MASK 0xffffffff
+#define RG_MTKAIF_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_MTKAIF0_CFG0 */
+#define RG_MTKAIF0_RXIF_CLKINV_SFT 31
+#define RG_MTKAIF0_RXIF_CLKINV_MASK 0x1
+#define RG_MTKAIF0_RXIF_CLKINV_MASK_SFT (0x1 << 31)
+#define RG_MTKAIF0_RXIF_BYPASS_SRC_SFT 17
+#define RG_MTKAIF0_RXIF_BYPASS_SRC_MASK 0x1
+#define RG_MTKAIF0_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)
+#define RG_MTKAIF0_RXIF_PROTOCOL2_SFT 16
+#define RG_MTKAIF0_RXIF_PROTOCOL2_MASK 0x1
+#define RG_MTKAIF0_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)
+#define RG_MTKAIF0_TXIF_NLE_DEBUG_SFT 8
+#define RG_MTKAIF0_TXIF_NLE_DEBUG_MASK 0x1
+#define RG_MTKAIF0_TXIF_NLE_DEBUG_MASK_SFT (0x1 << 8)
+#define RG_MTKAIF0_TXIF_BYPASS_SRC_SFT 5
+#define RG_MTKAIF0_TXIF_BYPASS_SRC_MASK 0x1
+#define RG_MTKAIF0_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)
+#define RG_MTKAIF0_TXIF_PROTOCOL2_SFT 4
+#define RG_MTKAIF0_TXIF_PROTOCOL2_MASK 0x1
+#define RG_MTKAIF0_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
+#define RG_MTKAIF0_TXIF_8TO5_SFT 2
+#define RG_MTKAIF0_TXIF_8TO5_MASK 0x1
+#define RG_MTKAIF0_TXIF_8TO5_MASK_SFT (0x1 << 2)
+#define RG_MTKAIF0_RXIF_8TO5_SFT 1
+#define RG_MTKAIF0_RXIF_8TO5_MASK 0x1
+#define RG_MTKAIF0_RXIF_8TO5_MASK_SFT (0x1 << 1)
+#define RG_MTKAIF0_TX2RX_LOOPBACK1_SFT 0
+#define RG_MTKAIF0_TX2RX_LOOPBACK1_MASK 0x1
+#define RG_MTKAIF0_TX2RX_LOOPBACK1_MASK_SFT (0x1 << 0)
+
+/* AFE_MTKAIF0_TX_CFG0 */
+#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_SFT 23
+#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_MASK 0x1
+#define RG_MTKAIF0_TXIF_NLE_FIFO_SWAP_MASK_SFT (0x1 << 23)
+#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_SFT 20
+#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_MASK 0x7
+#define RG_MTKAIF0_TXIF_NLE_FIFO_RSP_MASK_SFT (0x7 << 20)
+#define RG_MTKAIF0_TXIF_FIFO_SWAP_SFT 15
+#define RG_MTKAIF0_TXIF_FIFO_SWAP_MASK 0x1
+#define RG_MTKAIF0_TXIF_FIFO_SWAP_MASK_SFT (0x1 << 15)
+#define RG_MTKAIF0_TXIF_FIFO_RSP_SFT 12
+#define RG_MTKAIF0_TXIF_FIFO_RSP_MASK 0x7
+#define RG_MTKAIF0_TXIF_FIFO_RSP_MASK_SFT (0x7 << 12)
+#define RG_MTKAIF0_TXIF_SYNC_WORD1_SFT 4
+#define RG_MTKAIF0_TXIF_SYNC_WORD1_MASK 0x7
+#define RG_MTKAIF0_TXIF_SYNC_WORD1_MASK_SFT (0x7 << 4)
+#define RG_MTKAIF0_TXIF_SYNC_WORD0_SFT 0
+#define RG_MTKAIF0_TXIF_SYNC_WORD0_MASK 0x7
+#define RG_MTKAIF0_TXIF_SYNC_WORD0_MASK_SFT (0x7 << 0)
+
+/* AFE_MTKAIF0_RX_CFG0 */
+#define RG_MTKAIF0_RXIF_VOICE_MODE_SFT 20
+#define RG_MTKAIF0_RXIF_VOICE_MODE_MASK 0xf
+#define RG_MTKAIF0_RXIF_VOICE_MODE_MASK_SFT (0xf << 20)
+#define RG_MTKAIF0_RXIF_DETECT_ON_SFT 16
+#define RG_MTKAIF0_RXIF_DETECT_ON_MASK 0x1
+#define RG_MTKAIF0_RXIF_DETECT_ON_MASK_SFT (0x1 << 16)
+#define RG_MTKAIF0_RXIF_DATA_BIT_SFT 8
+#define RG_MTKAIF0_RXIF_DATA_BIT_MASK 0x7
+#define RG_MTKAIF0_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
+#define RG_MTKAIF0_RXIF_FIFO_RSP_SFT 4
+#define RG_MTKAIF0_RXIF_FIFO_RSP_MASK 0x7
+#define RG_MTKAIF0_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
+#define RG_MTKAIF0_RXIF_DATA_MODE_SFT 0
+#define RG_MTKAIF0_RXIF_DATA_MODE_MASK 0x1
+#define RG_MTKAIF0_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
+
+/* AFE_MTKAIF0_RX_CFG1 */
+#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_SFT 28
+#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
+#define RG_MTKAIF0_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 28)
+#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_SFT 16
+#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_MASK 0xfff
+#define RG_MTKAIF0_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 16)
+#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_SFT 12
+#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
+#define RG_MTKAIF0_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
+#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8
+#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
+#define RG_MTKAIF0_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
+#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_SFT 4
+#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_MASK 0xf
+#define RG_MTKAIF0_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
+
+/* AFE_MTKAIF0_RX_CFG2 */
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_SFT 27
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_MASK 0x1
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 27)
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_SFT 24
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_MASK 0x7
+#define RG_MTKAIF0_RXIF_SYNC_WORD1_MASK_SFT (0x7 << 24)
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_SFT 23
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_MASK 0x1
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_DISABLE_MASK_SFT (0x1 << 23)
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_SFT 20
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_MASK 0x7
+#define RG_MTKAIF0_RXIF_SYNC_WORD0_MASK_SFT (0x7 << 20)
+#define RG_MTKAIF0_RXIF_DELAY_CYCLE_SFT 12
+#define RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK 0xf
+#define RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)
+#define RG_MTKAIF0_RXIF_DELAY_DATA_SFT 8
+#define RG_MTKAIF0_RXIF_DELAY_DATA_MASK 0x1
+#define RG_MTKAIF0_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)
+
+/* AFE_MTKAIF1_CFG0 */
+#define RG_MTKAIF1_RXIF_CLKINV_ADC_SFT 31
+#define RG_MTKAIF1_RXIF_CLKINV_ADC_MASK 0x1
+#define RG_MTKAIF1_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)
+#define RG_MTKAIF1_RXIF_BYPASS_SRC_SFT 17
+#define RG_MTKAIF1_RXIF_BYPASS_SRC_MASK 0x1
+#define RG_MTKAIF1_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)
+#define RG_MTKAIF1_RXIF_PROTOCOL2_SFT 16
+#define RG_MTKAIF1_RXIF_PROTOCOL2_MASK 0x1
+#define RG_MTKAIF1_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)
+#define RG_MTKAIF1_TXIF_NLE_DEBUG_SFT 8
+#define RG_MTKAIF1_TXIF_NLE_DEBUG_MASK 0x1
+#define RG_MTKAIF1_TXIF_NLE_DEBUG_MASK_SFT (0x1 << 8)
+#define RG_MTKAIF1_TXIF_BYPASS_SRC_SFT 5
+#define RG_MTKAIF1_TXIF_BYPASS_SRC_MASK 0x1
+#define RG_MTKAIF1_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)
+#define RG_MTKAIF1_TXIF_PROTOCOL2_SFT 4
+#define RG_MTKAIF1_TXIF_PROTOCOL2_MASK 0x1
+#define RG_MTKAIF1_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
+#define RG_MTKAIF1_TXIF_8TO5_SFT 2
+#define RG_MTKAIF1_TXIF_8TO5_MASK 0x1
+#define RG_MTKAIF1_TXIF_8TO5_MASK_SFT (0x1 << 2)
+#define RG_MTKAIF1_RXIF_8TO5_SFT 1
+#define RG_MTKAIF1_RXIF_8TO5_MASK 0x1
+#define RG_MTKAIF1_RXIF_8TO5_MASK_SFT (0x1 << 1)
+#define RG_MTKAIF1_IF_LOOPBACK1_SFT 0
+#define RG_MTKAIF1_IF_LOOPBACK1_MASK 0x1
+#define RG_MTKAIF1_IF_LOOPBACK1_MASK_SFT (0x1 << 0)
+
+/* AFE_MTKAIF1_TX_CFG0 */
+#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_SFT 23
+#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_MASK 0x1
+#define RG_MTKAIF1_TXIF_NLE_FIFO_SWAP_MASK_SFT (0x1 << 23)
+#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_SFT 20
+#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_MASK 0x7
+#define RG_MTKAIF1_TXIF_NLE_FIFO_RSP_MASK_SFT (0x7 << 20)
+#define RG_MTKAIF1_TXIF_FIFO_SWAP_SFT 15
+#define RG_MTKAIF1_TXIF_FIFO_SWAP_MASK 0x1
+#define RG_MTKAIF1_TXIF_FIFO_SWAP_MASK_SFT (0x1 << 15)
+#define RG_MTKAIF1_TXIF_FIFO_RSP_SFT 12
+#define RG_MTKAIF1_TXIF_FIFO_RSP_MASK 0x7
+#define RG_MTKAIF1_TXIF_FIFO_RSP_MASK_SFT (0x7 << 12)
+#define RG_MTKAIF1_TXIF_SYNC_WORD1_SFT 4
+#define RG_MTKAIF1_TXIF_SYNC_WORD1_MASK 0x7
+#define RG_MTKAIF1_TXIF_SYNC_WORD1_MASK_SFT (0x7 << 4)
+#define RG_MTKAIF1_TXIF_SYNC_WORD0_SFT 0
+#define RG_MTKAIF1_TXIF_SYNC_WORD0_MASK 0x7
+#define RG_MTKAIF1_TXIF_SYNC_WORD0_MASK_SFT (0x7 << 0)
+
+/* AFE_MTKAIF1_RX_CFG0 */
+#define RG_MTKAIF1_RXIF_VOICE_MODE_SFT 20
+#define RG_MTKAIF1_RXIF_VOICE_MODE_MASK 0xf
+#define RG_MTKAIF1_RXIF_VOICE_MODE_MASK_SFT (0xf << 20)
+#define RG_MTKAIF1_RXIF_DETECT_ON_SFT 16
+#define RG_MTKAIF1_RXIF_DETECT_ON_MASK 0x1
+#define RG_MTKAIF1_RXIF_DETECT_ON_MASK_SFT (0x1 << 16)
+#define RG_MTKAIF1_RXIF_DATA_BIT_SFT 8
+#define RG_MTKAIF1_RXIF_DATA_BIT_MASK 0x7
+#define RG_MTKAIF1_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
+#define RG_MTKAIF1_RXIF_FIFO_RSP_SFT 4
+#define RG_MTKAIF1_RXIF_FIFO_RSP_MASK 0x7
+#define RG_MTKAIF1_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
+#define RG_MTKAIF1_RXIF_DATA_MODE_SFT 0
+#define RG_MTKAIF1_RXIF_DATA_MODE_MASK 0x1
+#define RG_MTKAIF1_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
+
+/* AFE_MTKAIF1_RX_CFG1 */
+#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_SFT 28
+#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
+#define RG_MTKAIF1_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 28)
+#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_SFT 16
+#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_MASK 0xfff
+#define RG_MTKAIF1_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 16)
+#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_SFT 12
+#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
+#define RG_MTKAIF1_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
+#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8
+#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
+#define RG_MTKAIF1_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
+#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_SFT 4
+#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_MASK 0xf
+#define RG_MTKAIF1_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
+
+/* AFE_MTKAIF1_RX_CFG2 */
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_SFT 27
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_MASK 0x1
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 27)
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_SFT 24
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_MASK 0x7
+#define RG_MTKAIF1_RXIF_SYNC_WORD1_MASK_SFT (0x7 << 24)
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_SFT 23
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_MASK 0x1
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_DISABLE_MASK_SFT (0x1 << 23)
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_SFT 20
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_MASK 0x7
+#define RG_MTKAIF1_RXIF_SYNC_WORD0_MASK_SFT (0x7 << 20)
+#define RG_MTKAIF1_RXIF_DELAY_CYCLE_SFT 12
+#define RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK 0xf
+#define RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)
+#define RG_MTKAIF1_RXIF_DELAY_DATA_SFT 8
+#define RG_MTKAIF1_RXIF_DELAY_DATA_MASK 0x1
+#define RG_MTKAIF1_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)
+
+/* AFE_AUD_PAD_TOP_CFG0 */
+#define AUD_PAD_TOP_FIFO_RSP_SFT 4
+#define AUD_PAD_TOP_FIFO_RSP_MASK 0xf
+#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT (0xf << 4)
+#define RG_RX_PROTOCOL2_SFT 3
+#define RG_RX_PROTOCOL2_MASK 0x1
+#define RG_RX_PROTOCOL2_MASK_SFT (0x1 << 3)
+#define RG_RX_FIFO_ON_SFT 0
+#define RG_RX_FIFO_ON_MASK 0x1
+#define RG_RX_FIFO_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_AUD_PAD_TOP_MON */
+#define AUD_PAD_TOP_MON_SFT 0
+#define AUD_PAD_TOP_MON_MASK 0xffff
+#define AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)
+
+/* AFE_ADDA_MTKAIFV4_TX_CFG0 */
+#define MTKAIFV4_TXIF_EN_SEL_SFT 12
+#define MTKAIFV4_TXIF_EN_SEL_MASK 0x1
+#define MTKAIFV4_TXIF_EN_SEL_MASK_SFT (0x1 << 12)
+#define MTKAIFV4_TXIF_V4_SFT 11
+#define MTKAIFV4_TXIF_V4_MASK 0x1
+#define MTKAIFV4_TXIF_V4_MASK_SFT (0x1 << 11)
+#define MTKAIFV4_ADDA6_OUT_EN_SEL_SFT 10
+#define MTKAIFV4_ADDA6_OUT_EN_SEL_MASK 0x1
+#define MTKAIFV4_ADDA6_OUT_EN_SEL_MASK_SFT (0x1 << 10)
+#define MTKAIFV4_ADDA_OUT_EN_SEL_SFT 9
+#define MTKAIFV4_ADDA_OUT_EN_SEL_MASK 0x1
+#define MTKAIFV4_ADDA_OUT_EN_SEL_MASK_SFT (0x1 << 9)
+#define MTKAIFV4_TXIF_INPUT_MODE_SFT 4
+#define MTKAIFV4_TXIF_INPUT_MODE_MASK 0x1f
+#define MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT (0x1f << 4)
+#define MTKAIFV4_TXIF_FOUR_CHANNEL_SFT 1
+#define MTKAIFV4_TXIF_FOUR_CHANNEL_MASK 0x1
+#define MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1)
+#define MTKAIFV4_TXIF_AFE_ON_SFT 0
+#define MTKAIFV4_TXIF_AFE_ON_MASK 0x1
+#define MTKAIFV4_TXIF_AFE_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA6_MTKAIFV4_TX_CFG0 */
+#define ADDA6_MTKAIFV4_TXIF_EN_SEL_SFT 12
+#define ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK 0x1
+#define ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK_SFT (0x1 << 12)
+#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_SFT 4
+#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK 0x1f
+#define ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT (0x1f << 4)
+#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT 1
+#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK 0x1
+#define ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1)
+#define ADDA6_MTKAIFV4_TXIF_AFE_ON_SFT 0
+#define ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK 0x1
+#define ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_MTKAIFV4_RX_CFG0 */
+#define MTKAIFV4_RXIF_CLKINV_SFT 31
+#define MTKAIFV4_RXIF_CLKINV_MASK 0x1
+#define MTKAIFV4_RXIF_CLKINV_MASK_SFT (0x1 << 31)
+#define MTKAIFV4_RXIF_LOOPBACK_MODE_SFT 28
+#define MTKAIFV4_RXIF_LOOPBACK_MODE_MASK 0x1
+#define MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT (0x1 << 28)
+#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_SFT 19
+#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_MASK 0x1
+#define MTKAIFV4_UL_CH7CH8_IN_EN_SEL_MASK_SFT (0x1 << 19)
+#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_SFT 18
+#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK 0x1
+#define MTKAIFV4_UL_CH5CH6_IN_EN_SEL_MASK_SFT (0x1 << 18)
+#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_SFT 17
+#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK 0x1
+#define MTKAIFV4_UL_CH3CH4_IN_EN_SEL_MASK_SFT (0x1 << 17)
+#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_SFT 16
+#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK 0x1
+#define MTKAIFV4_UL_CH1CH2_IN_EN_SEL_MASK_SFT (0x1 << 16)
+#define MTKAIFV4_RXIF_EN_SEL_SFT 12
+#define MTKAIFV4_RXIF_EN_SEL_MASK 0x1
+#define MTKAIFV4_RXIF_EN_SEL_MASK_SFT (0x1 << 12)
+#define MTKAIFV4_RXIF_INPUT_MODE_SFT 4
+#define MTKAIFV4_RXIF_INPUT_MODE_MASK 0x1f
+#define MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT (0x1f << 4)
+#define MTKAIFV4_RXIF_FOUR_CHANNEL_SFT 1
+#define MTKAIFV4_RXIF_FOUR_CHANNEL_MASK 0x1
+#define MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1)
+#define MTKAIFV4_RXIF_AFE_ON_SFT 0
+#define MTKAIFV4_RXIF_AFE_ON_MASK 0x1
+#define MTKAIFV4_RXIF_AFE_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_MTKAIFV4_RX_CFG1 */
+#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_SFT 17
+#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK 0xfff
+#define MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 17)
+#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT 12
+#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK 0x1f
+#define MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0x1f << 12)
+#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_SFT 8
+#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK 0xf
+#define MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
+#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT 4
+#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK 0xf
+#define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
+#define MTKAIFV4_RXIF_FIFO_RSP_SFT 1
+#define MTKAIFV4_RXIF_FIFO_RSP_MASK 0x7
+#define MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT (0x7 << 1)
+#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT 0
+#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK 0x1
+#define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA6_MTKAIFV4_RX_CFG0 */
+#define ADDA6_MTKAIFV4_RXIF_CLKINV_SFT 31
+#define ADDA6_MTKAIFV4_RXIF_CLKINV_MASK 0x1
+#define ADDA6_MTKAIFV4_RXIF_CLKINV_MASK_SFT (0x1 << 31)
+#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_SFT 28
+#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK 0x1
+#define ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT (0x1 << 28)
+#define ADDA6_MTKAIFV4_RXIF_EN_SEL_SFT 12
+#define ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK 0x1
+#define ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK_SFT (0x1 << 12)
+#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT 4
+#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK 0x1f
+#define ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT (0x1f << 4)
+#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT 1
+#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK 0x1
+#define ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1)
+#define ADDA6_MTKAIFV4_RXIF_AFE_ON_SFT 0
+#define ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK 0x1
+#define ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA6_MTKAIFV4_RX_CFG1 */
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_SFT 17
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK 0xfff
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 17)
+#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT 12
+#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK 0x1f
+#define ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0x1f << 12)
+#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_SFT 8
+#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK 0xf
+#define ADDA6_MTKAIFV4_RXIF_INVAILD_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT 4
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK 0xf
+#define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
+#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_SFT 1
+#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK 0x7
+#define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT (0x7 << 1)
+#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT 0
+#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK 0x1
+#define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT (0x1 << 0)
+
+/* AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG */
+#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_SFT 16
+#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_MASK 0xffff
+#define ADDA6_MTKAIFV4_TXIF_SYNCWORD_MASK_SFT (0xffff << 16)
+#define ADDA_MTKAIFV4_TXIF_SYNCWORD_SFT 0
+#define ADDA_MTKAIFV4_TXIF_SYNCWORD_MASK 0xffff
+#define ADDA_MTKAIFV4_TXIF_SYNCWORD_MASK_SFT (0xffff << 0)
+
+/* AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG */
+#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_SFT 16
+#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_MASK 0xffff
+#define ADDA6_MTKAIFV4_RXIF_SYNCWORD_MASK_SFT (0xffff << 16)
+#define ADDA_MTKAIFV4_RXIF_SYNCWORD_SFT 0
+#define ADDA_MTKAIFV4_RXIF_SYNCWORD_MASK 0xffff
+#define ADDA_MTKAIFV4_RXIF_SYNCWORD_MASK_SFT (0xffff << 0)
+
+/* AFE_ADDA_MTKAIFV4_MON0 */
+#define MTKAIFV4_TXIF_SDATA_OUT_SFT 23
+#define MTKAIFV4_TXIF_SDATA_OUT_MASK 0x1
+#define MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT (0x1 << 23)
+#define MTKAIFV4_RXIF_SDATA_IN_SFT 22
+#define MTKAIFV4_RXIF_SDATA_IN_MASK 0x1
+#define MTKAIFV4_RXIF_SDATA_IN_MASK_SFT (0x1 << 22)
+#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT 21
+#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
+#define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 21)
+#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_SFT 0
+#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK 0xfff
+#define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK_SFT (0xfff << 0)
+
+/* AFE_ADDA_MTKAIFV4_MON1 */
+#define MTKAIFV4_RXIF_OUT_CH4_SFT 24
+#define MTKAIFV4_RXIF_OUT_CH4_MASK 0xff
+#define MTKAIFV4_RXIF_OUT_CH4_MASK_SFT (0xff << 24)
+#define MTKAIFV4_RXIF_OUT_CH3_SFT 16
+#define MTKAIFV4_RXIF_OUT_CH3_MASK 0xff
+#define MTKAIFV4_RXIF_OUT_CH3_MASK_SFT (0xff << 16)
+#define MTKAIFV4_RXIF_OUT_CH2_SFT 8
+#define MTKAIFV4_RXIF_OUT_CH2_MASK 0xff
+#define MTKAIFV4_RXIF_OUT_CH2_MASK_SFT (0xff << 8)
+#define MTKAIFV4_RXIF_OUT_CH1_SFT 0
+#define MTKAIFV4_RXIF_OUT_CH1_MASK 0xff
+#define MTKAIFV4_RXIF_OUT_CH1_MASK_SFT (0xff << 0)
+
+/* AFE_ADDA6_MTKAIFV4_MON0 */
+#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_SFT 23
+#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK 0x1
+#define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT (0x1 << 23)
+#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_SFT 22
+#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_MASK 0x1
+#define ADDA6_MTKAIFV4_RXIF_SDATA_IN_MASK_SFT (0x1 << 22)
+#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT 21
+#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
+#define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 21)
+#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_SFT 0
+#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_MASK 0xfff
+#define ADDA6_MTKAIFV3P3_RXIF_ADC_FIFO_STATUS_MASK_SFT (0xfff << 0)
+
+/* ETDM_IN0_CON0 */
+/* ETDM_IN1_CON0 */
+#define REG_ETDM_IN_EN_SFT 0
+#define REG_ETDM_IN_EN_MASK 0x1
+#define REG_ETDM_IN_EN_MASK_SFT (0x1 << 0)
+#define REG_SYNC_MODE_SFT 1
+#define REG_SYNC_MODE_MASK 0x1
+#define REG_SYNC_MODE_MASK_SFT (0x1 << 1)
+#define REG_LSB_FIRST_SFT 3
+#define REG_LSB_FIRST_MASK 0x1
+#define REG_LSB_FIRST_MASK_SFT (0x1 << 3)
+#define REG_SOFT_RST_SFT 4
+#define REG_SOFT_RST_MASK 0x1
+#define REG_SOFT_RST_MASK_SFT (0x1 << 4)
+#define REG_SLAVE_MODE_SFT 5
+#define REG_SLAVE_MODE_MASK 0x1
+#define REG_SLAVE_MODE_MASK_SFT (0x1 << 5)
+#define REG_FMT_SFT 6
+#define REG_FMT_MASK 0x7
+#define REG_FMT_MASK_SFT (0x7 << 6)
+#define REG_LRCK_EDGE_SEL_SFT 10
+#define REG_LRCK_EDGE_SEL_MASK 0x1
+#define REG_LRCK_EDGE_SEL_MASK_SFT (0x1 << 10)
+#define REG_BIT_LENGTH_SFT 11
+#define REG_BIT_LENGTH_MASK 0x1f
+#define REG_BIT_LENGTH_MASK_SFT (0x1f << 11)
+#define REG_WORD_LENGTH_SFT 16
+#define REG_WORD_LENGTH_MASK 0x1f
+#define REG_WORD_LENGTH_MASK_SFT (0x1f << 16)
+#define REG_CH_NUM_SFT 23
+#define REG_CH_NUM_MASK 0x1f
+#define REG_CH_NUM_MASK_SFT (0x1f << 23)
+#define REG_RELATCH_1X_EN_DOMAIN_SEL_SFT 28
+#define REG_RELATCH_1X_EN_DOMAIN_SEL_MASK 0x7
+#define REG_RELATCH_1X_EN_DOMAIN_SEL_MASK_SFT (0x7 << 28)
+#define REG_VALID_TOGETHER_SFT 31
+#define REG_VALID_TOGETHER_MASK 0x1
+#define REG_VALID_TOGETHER_MASK_SFT (0x1 << 31)
+
+/* ETDM_IN0_CON1 */
+/* ETDM_IN1_CON1 */
+#define REG_INITIAL_COUNT_SFT 0
+#define REG_INITIAL_COUNT_MASK 0x1f
+#define REG_INITIAL_COUNT_MASK_SFT (0x1f << 0)
+#define REG_INITIAL_POINT_SFT 5
+#define REG_INITIAL_POINT_MASK 0x1f
+#define REG_INITIAL_POINT_MASK_SFT (0x1f << 5)
+#define REG_LRCK_AUTO_OFF_SFT 10
+#define REG_LRCK_AUTO_OFF_MASK 0x1
+#define REG_LRCK_AUTO_OFF_MASK_SFT (0x1 << 10)
+#define REG_BCK_AUTO_OFF_SFT 11
+#define REG_BCK_AUTO_OFF_MASK 0x1
+#define REG_BCK_AUTO_OFF_MASK_SFT (0x1 << 11)
+#define REG_INITIAL_LRCK_SFT 13
+#define REG_INITIAL_LRCK_MASK 0x1
+#define REG_INITIAL_LRCK_MASK_SFT (0x1 << 13)
+#define REG_NO_ALIGN_1X_EN_SFT 14
+#define REG_NO_ALIGN_1X_EN_MASK 0x1
+#define REG_NO_ALIGN_1X_EN_MASK_SFT (0x1 << 14)
+#define REG_LRCK_RESET_SFT 15
+#define REG_LRCK_RESET_MASK 0x1
+#define REG_LRCK_RESET_MASK_SFT (0x1 << 15)
+#define PINMUX_MCLK_CTRL_OE_SFT 16
+#define PINMUX_MCLK_CTRL_OE_MASK 0x1
+#define PINMUX_MCLK_CTRL_OE_MASK_SFT (0x1 << 16)
+#define REG_OUTPUT_CR_EN_SFT 18
+#define REG_OUTPUT_CR_EN_MASK 0x1
+#define REG_OUTPUT_CR_EN_MASK_SFT (0x1 << 18)
+#define REG_LR_ALIGN_SFT 19
+#define REG_LR_ALIGN_MASK 0x1
+#define REG_LR_ALIGN_MASK_SFT (0x1 << 19)
+#define REG_LRCK_WIDTH_SFT 20
+#define REG_LRCK_WIDTH_MASK 0x3ff
+#define REG_LRCK_WIDTH_MASK_SFT (0x3ff << 20)
+#define REG_DIRECT_INPUT_MASTER_BCK_SFT 30
+#define REG_DIRECT_INPUT_MASTER_BCK_MASK 0x1
+#define REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT (0x1 << 30)
+#define REG_LRCK_AUTO_MODE_SFT 31
+#define REG_LRCK_AUTO_MODE_MASK 0x1
+#define REG_LRCK_AUTO_MODE_MASK_SFT (0x1 << 31)
+
+/* ETDM_IN0_CON2 */
+/* ETDM_IN1_CON2 */
+#define REG_UPDATE_POINT_SFT 0
+#define REG_UPDATE_POINT_MASK 0x1f
+#define REG_UPDATE_POINT_MASK_SFT (0x1f << 0)
+#define REG_UPDATE_GAP_SFT 5
+#define REG_UPDATE_GAP_MASK 0x1f
+#define REG_UPDATE_GAP_MASK_SFT (0x1f << 5)
+#define REG_CLOCK_SOURCE_SEL_SFT 10
+#define REG_CLOCK_SOURCE_SEL_MASK 0x7
+#define REG_CLOCK_SOURCE_SEL_MASK_SFT (0x7 << 10)
+#define REG_CK_EN_SEL_AUTO_SFT 14
+#define REG_CK_EN_SEL_AUTO_MASK 0x1
+#define REG_CK_EN_SEL_AUTO_MASK_SFT (0x1 << 14)
+#define REG_MULTI_IP_TOTAL_CHNUM_SFT 15
+#define REG_MULTI_IP_TOTAL_CHNUM_MASK 0x1f
+#define REG_MULTI_IP_TOTAL_CHNUM_MASK_SFT (0x1f << 15)
+#define REG_MASK_AUTO_SFT 20
+#define REG_MASK_AUTO_MASK 0x1
+#define REG_MASK_AUTO_MASK_SFT (0x1 << 20)
+#define REG_MASK_NUM_SFT 21
+#define REG_MASK_NUM_MASK 0x1f
+#define REG_MASK_NUM_MASK_SFT (0x1f << 21)
+#define REG_UPDATE_POINT_AUTO_SFT 26
+#define REG_UPDATE_POINT_AUTO_MASK 0x1
+#define REG_UPDATE_POINT_AUTO_MASK_SFT (0x1 << 26)
+#define REG_SDATA_DELAY_0P5T_EN_SFT 27
+#define REG_SDATA_DELAY_0P5T_EN_MASK 0x1
+#define REG_SDATA_DELAY_0P5T_EN_MASK_SFT (0x1 << 27)
+#define REG_SDATA_DELAY_BCK_INV_SFT 28
+#define REG_SDATA_DELAY_BCK_INV_MASK 0x1
+#define REG_SDATA_DELAY_BCK_INV_MASK_SFT (0x1 << 28)
+#define REG_LRCK_DELAY_0P5T_EN_SFT 29
+#define REG_LRCK_DELAY_0P5T_EN_MASK 0x1
+#define REG_LRCK_DELAY_0P5T_EN_MASK_SFT (0x1 << 29)
+#define REG_LRCK_DELAY_BCK_INV_SFT 30
+#define REG_LRCK_DELAY_BCK_INV_MASK 0x1
+#define REG_LRCK_DELAY_BCK_INV_MASK_SFT (0x1 << 30)
+#define REG_MULTI_IP_MODE_SFT 31
+#define REG_MULTI_IP_MODE_MASK 0x1
+#define REG_MULTI_IP_MODE_MASK_SFT (0x1 << 31)
+
+/* ETDM_IN0_CON3 */
+/* ETDM_IN1_CON3 */
+#define REG_DISABLE_OUT_SFT 0
+#define REG_DISABLE_OUT_MASK 0xffff
+#define REG_DISABLE_OUT_MASK_SFT (0xffff << 0)
+#define REG_RJ_DATA_RIGHT_ALIGN_SFT 16
+#define REG_RJ_DATA_RIGHT_ALIGN_MASK 0x1
+#define REG_RJ_DATA_RIGHT_ALIGN_MASK_SFT (0x1 << 16)
+#define REG_MONITOR_SEL_SFT 17
+#define REG_MONITOR_SEL_MASK 0x3
+#define REG_MONITOR_SEL_MASK_SFT (0x3 << 17)
+#define REG_CNT_UPPER_LIMIT_SFT 19
+#define REG_CNT_UPPER_LIMIT_MASK 0x3f
+#define REG_CNT_UPPER_LIMIT_MASK_SFT (0x3f << 19)
+#define REG_COMPACT_SAMPLE_END_DIS_SFT 25
+#define REG_COMPACT_SAMPLE_END_DIS_MASK 0x1
+#define REG_COMPACT_SAMPLE_END_DIS_MASK_SFT (0x1 << 25)
+#define REG_FS_TIMING_SEL_SFT 26
+#define REG_FS_TIMING_SEL_MASK 0x1f
+#define REG_FS_TIMING_SEL_MASK_SFT (0x1f << 26)
+#define REG_SAMPLE_END_MODE_SFT 31
+#define REG_SAMPLE_END_MODE_MASK 0x1
+#define REG_SAMPLE_END_MODE_MASK_SFT (0x1 << 31)
+
+/* ETDM_IN0_CON4 */
+/* ETDM_IN1_CON4 */
+#define REG_ALWAYS_OPEN_1X_EN_SFT 31
+#define REG_ALWAYS_OPEN_1X_EN_MASK 0x1
+#define REG_ALWAYS_OPEN_1X_EN_MASK_SFT (0x1 << 31)
+#define REG_WAIT_LAST_SAMPLE_SFT 30
+#define REG_WAIT_LAST_SAMPLE_MASK 0x1
+#define REG_WAIT_LAST_SAMPLE_MASK_SFT (0x1 << 30)
+#define REG_SAMPLE_END_POINT_SFT 25
+#define REG_SAMPLE_END_POINT_MASK 0x1f
+#define REG_SAMPLE_END_POINT_MASK_SFT (0x1f << 25)
+#define REG_RELATCH_1X_EN_SEL_SFT 20
+#define REG_RELATCH_1X_EN_SEL_MASK 0x1f
+#define REG_RELATCH_1X_EN_SEL_MASK_SFT (0x1f << 20)
+#define REG_MASTER_WS_INV_SFT 19
+#define REG_MASTER_WS_INV_MASK 0x1
+#define REG_MASTER_WS_INV_MASK_SFT (0x1 << 19)
+#define REG_MASTER_BCK_INV_SFT 18
+#define REG_MASTER_BCK_INV_MASK 0x1
+#define REG_MASTER_BCK_INV_MASK_SFT (0x1 << 18)
+#define REG_SLAVE_LRCK_INV_SFT 17
+#define REG_SLAVE_LRCK_INV_MASK 0x1
+#define REG_SLAVE_LRCK_INV_MASK_SFT (0x1 << 17)
+#define REG_SLAVE_BCK_INV_SFT 16
+#define REG_SLAVE_BCK_INV_MASK 0x1
+#define REG_SLAVE_BCK_INV_MASK_SFT (0x1 << 16)
+#define REG_REPACK_CHNUM_SFT 12
+#define REG_REPACK_CHNUM_MASK 0xf
+#define REG_REPACK_CHNUM_MASK_SFT (0xf << 12)
+#define REG_ASYNC_RESET_SFT 11
+#define REG_ASYNC_RESET_MASK 0x1
+#define REG_ASYNC_RESET_MASK_SFT (0x1 << 11)
+#define REG_REPACK_WORD_LENGTH_SFT 9
+#define REG_REPACK_WORD_LENGTH_MASK 0x3
+#define REG_REPACK_WORD_LENGTH_MASK_SFT (0x3 << 9)
+#define REG_REPACK_AUTO_MODE_SFT 8
+#define REG_REPACK_AUTO_MODE_MASK 0x1
+#define REG_REPACK_AUTO_MODE_MASK_SFT (0x1 << 8)
+#define REG_REPACK_MODE_SFT 0
+#define REG_REPACK_MODE_MASK 0x3f
+#define REG_REPACK_MODE_MASK_SFT (0x3f << 0)
+
+/* ETDM_IN0_CON5 */
+/* ETDM_IN1_CON5 */
+#define REG_LR_SWAP_SFT 16
+#define REG_LR_SWAP_MASK 0xffff
+#define REG_LR_SWAP_MASK_SFT (0xffff << 16)
+#define REG_ODD_FLAG_EN_SFT 0
+#define REG_ODD_FLAG_EN_MASK 0xffff
+#define REG_ODD_FLAG_EN_MASK_SFT (0xffff << 0)
+
+/* ETDM_IN0_CON6 */
+/* ETDM_IN1_CON6 */
+#define LCH_DATA_REG_SFT 0
+#define LCH_DATA_REG_MASK 0xffffffff
+#define LCH_DATA_REG_MASK_SFT (0xffffffff << 0)
+
+/* ETDM_IN0_CON7 */
+/* ETDM_IN1_CON7 */
+#define RCH_DATA_REG_SFT 0
+#define RCH_DATA_REG_MASK 0xffffffff
+#define RCH_DATA_REG_MASK_SFT (0xffffffff << 0)
+
+/* ETDM_IN0_CON8 */
+/* ETDM_IN1_CON8 */
+#define REG_AFIFO_THRESHOLD_SFT 29
+#define REG_AFIFO_THRESHOLD_MASK 0x3
+#define REG_AFIFO_THRESHOLD_MASK_SFT (0x3 << 29)
+#define REG_CK_EN_SEL_MANUAL_SFT 16
+#define REG_CK_EN_SEL_MANUAL_MASK 0x3ff
+#define REG_CK_EN_SEL_MANUAL_MASK_SFT (0x3ff << 16)
+#define REG_AFIFO_SW_RESET_SFT 15
+#define REG_AFIFO_SW_RESET_MASK 0x1
+#define REG_AFIFO_SW_RESET_MASK_SFT (0x1 << 15)
+#define REG_AFIFO_RESET_SEL_SFT 14
+#define REG_AFIFO_RESET_SEL_MASK 0x1
+#define REG_AFIFO_RESET_SEL_MASK_SFT (0x1 << 14)
+#define REG_AFIFO_AUTO_RESET_DIS_SFT 9
+#define REG_AFIFO_AUTO_RESET_DIS_MASK 0x1
+#define REG_AFIFO_AUTO_RESET_DIS_MASK_SFT (0x1 << 9)
+#define REG_ETDM_USE_AFIFO_SFT 8
+#define REG_ETDM_USE_AFIFO_MASK 0x1
+#define REG_ETDM_USE_AFIFO_MASK_SFT (0x1 << 8)
+#define REG_AFIFO_CLOCK_DOMAIN_SEL_SFT 5
+#define REG_AFIFO_CLOCK_DOMAIN_SEL_MASK 0x7
+#define REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT (0x7 << 5)
+#define REG_AFIFO_MODE_SFT 0
+#define REG_AFIFO_MODE_MASK 0x1f
+#define REG_AFIFO_MODE_MASK_SFT (0x1f << 0)
+
+/* ETDM_IN0_CON9 */
+/* ETDM_IN1_CON9 */
+#define REG_OUT2LATCH_TIME_SFT 10
+#define REG_OUT2LATCH_TIME_MASK 0x1f
+#define REG_OUT2LATCH_TIME_MASK_SFT (0x1f << 10)
+#define REG_ALMOST_END_BIT_COUNT_SFT 5
+#define REG_ALMOST_END_BIT_COUNT_MASK 0x1f
+#define REG_ALMOST_END_BIT_COUNT_MASK_SFT (0x1f << 5)
+#define REG_ALMOST_END_CH_COUNT_SFT 0
+#define REG_ALMOST_END_CH_COUNT_MASK 0x1f
+#define REG_ALMOST_END_CH_COUNT_MASK_SFT (0x1f << 0)
+
+/* ETDM_IN0_MON */
+/* ETDM_IN1_MON */
+#define LRCK_INV_SFT 30
+#define LRCK_INV_MASK 0x1
+#define LRCK_INV_MASK_SFT (0x1 << 30)
+#define EN_SYNC_OUT_SFT 29
+#define EN_SYNC_OUT_MASK 0x1
+#define EN_SYNC_OUT_MASK_SFT (0x1 << 29)
+#define HOPPING_EN_SYNC_OUT_PRE_SFT 28
+#define HOPPING_EN_SYNC_OUT_PRE_MASK 0x1
+#define HOPPING_EN_SYNC_OUT_PRE_MASK_SFT (0x1 << 28)
+#define WFULL_SFT 27
+#define WFULL_MASK 0x1
+#define WFULL_MASK_SFT (0x1 << 27)
+#define REMPTY_SFT 26
+#define REMPTY_MASK 0x1
+#define REMPTY_MASK_SFT (0x1 << 26)
+#define ETDM_2X_CK_EN_SFT 25
+#define ETDM_2X_CK_EN_MASK 0x1
+#define ETDM_2X_CK_EN_MASK_SFT (0x1 << 25)
+#define ETDM_1X_CK_EN_SFT 24
+#define ETDM_1X_CK_EN_MASK 0x1
+#define ETDM_1X_CK_EN_MASK_SFT (0x1 << 24)
+#define SDATA0_SFT 23
+#define SDATA0_MASK 0x1
+#define SDATA0_MASK_SFT (0x1 << 23)
+#define CURRENT_STATUS_SFT 21
+#define CURRENT_STATUS_MASK 0x3
+#define CURRENT_STATUS_MASK_SFT (0x3 << 21)
+#define BIT_POINT_SFT 16
+#define BIT_POINT_MASK 0x1f
+#define BIT_POINT_MASK_SFT (0x1f << 16)
+#define BIT_CH_COUNT_SFT 10
+#define BIT_CH_COUNT_MASK 0x3f
+#define BIT_CH_COUNT_MASK_SFT (0x3f << 10)
+#define BIT_COUNT_SFT 5
+#define BIT_COUNT_MASK 0x1f
+#define BIT_COUNT_MASK_SFT (0x1f << 5)
+#define CH_COUNT_SFT 0
+#define CH_COUNT_MASK 0x1f
+#define CH_COUNT_MASK_SFT (0x1f << 0)
+
+/* ETDM_OUT0_CON0 */
+/* ETDM_OUT1_CON0 */
+/* ETDM_OUT4_CON0 */
+#define OUT_REG_ETDM_OUT_EN_SFT 0
+#define OUT_REG_ETDM_OUT_EN_MASK 0x1
+#define OUT_REG_ETDM_OUT_EN_MASK_SFT (0x1 << 0)
+#define OUT_REG_SYNC_MODE_SFT 1
+#define OUT_REG_SYNC_MODE_MASK 0x1
+#define OUT_REG_SYNC_MODE_MASK_SFT (0x1 << 1)
+#define OUT_REG_LSB_FIRST_SFT 3
+#define OUT_REG_LSB_FIRST_MASK 0x1
+#define OUT_REG_LSB_FIRST_MASK_SFT (0x1 << 3)
+#define OUT_REG_SOFT_RST_SFT 4
+#define OUT_REG_SOFT_RST_MASK 0x1
+#define OUT_REG_SOFT_RST_MASK_SFT (0x1 << 4)
+#define OUT_REG_SLAVE_MODE_SFT 5
+#define OUT_REG_SLAVE_MODE_MASK 0x1
+#define OUT_REG_SLAVE_MODE_MASK_SFT (0x1 << 5)
+#define OUT_REG_FMT_SFT 6
+#define OUT_REG_FMT_MASK 0x7
+#define OUT_REG_FMT_MASK_SFT (0x7 << 6)
+#define OUT_REG_LRCK_EDGE_SEL_SFT 10
+#define OUT_REG_LRCK_EDGE_SEL_MASK 0x1
+#define OUT_REG_LRCK_EDGE_SEL_MASK_SFT (0x1 << 10)
+#define OUT_REG_BIT_LENGTH_SFT 11
+#define OUT_REG_BIT_LENGTH_MASK 0x1f
+#define OUT_REG_BIT_LENGTH_MASK_SFT (0x1f << 11)
+#define OUT_REG_WORD_LENGTH_SFT 16
+#define OUT_REG_WORD_LENGTH_MASK 0x1f
+#define OUT_REG_WORD_LENGTH_MASK_SFT (0x1f << 16)
+#define OUT_REG_CH_NUM_SFT 23
+#define OUT_REG_CH_NUM_MASK 0x1f
+#define OUT_REG_CH_NUM_MASK_SFT (0x1f << 23)
+#define OUT_REG_RELATCH_DOMAIN_SEL_SFT 28
+#define OUT_REG_RELATCH_DOMAIN_SEL_MASK 0x7
+#define OUT_REG_RELATCH_DOMAIN_SEL_MASK_SFT (0x7 << 28)
+#define OUT_REG_VALID_TOGETHER_SFT 31
+#define OUT_REG_VALID_TOGETHER_MASK 0x1
+#define OUT_REG_VALID_TOGETHER_MASK_SFT (0x1 << 31)
+
+/* ETDM_OUT0_CON1 */
+/* ETDM_OUT1_CON1 */
+/* ETDM_OUT4_CON1 */
+#define OUT_REG_INITIAL_COUNT_SFT 0
+#define OUT_REG_INITIAL_COUNT_MASK 0x1f
+#define OUT_REG_INITIAL_COUNT_MASK_SFT (0x1f << 0)
+#define OUT_REG_INITIAL_POINT_SFT 5
+#define OUT_REG_INITIAL_POINT_MASK 0x1f
+#define OUT_REG_INITIAL_POINT_MASK_SFT (0x1f << 5)
+#define OUT_REG_LRCK_AUTO_OFF_SFT 10
+#define OUT_REG_LRCK_AUTO_OFF_MASK 0x1
+#define OUT_REG_LRCK_AUTO_OFF_MASK_SFT (0x1 << 10)
+#define OUT_REG_BCK_AUTO_OFF_SFT 11
+#define OUT_REG_BCK_AUTO_OFF_MASK 0x1
+#define OUT_REG_BCK_AUTO_OFF_MASK_SFT (0x1 << 11)
+#define OUT_REG_INITIAL_LRCK_SFT 13
+#define OUT_REG_INITIAL_LRCK_MASK 0x1
+#define OUT_REG_INITIAL_LRCK_MASK_SFT (0x1 << 13)
+#define OUT_REG_NO_ALIGN_1X_EN_SFT 14
+#define OUT_REG_NO_ALIGN_1X_EN_MASK 0x1
+#define OUT_REG_NO_ALIGN_1X_EN_MASK_SFT (0x1 << 14)
+#define OUT_REG_LRCK_RESET_SFT 15
+#define OUT_REG_LRCK_RESET_MASK 0x1
+#define OUT_REG_LRCK_RESET_MASK_SFT (0x1 << 15)
+#define OUT_PINMUX_MCLK_CTRL_OE_SFT 16
+#define OUT_PINMUX_MCLK_CTRL_OE_MASK 0x1
+#define OUT_PINMUX_MCLK_CTRL_OE_MASK_SFT (0x1 << 16)
+#define OUT_REG_OUTPUT_CR_EN_SFT 18
+#define OUT_REG_OUTPUT_CR_EN_MASK 0x1
+#define OUT_REG_OUTPUT_CR_EN_MASK_SFT (0x1 << 18)
+#define OUT_REG_LRCK_WIDTH_SFT 19
+#define OUT_REG_LRCK_WIDTH_MASK 0x3ff
+#define OUT_REG_LRCK_WIDTH_MASK_SFT (0x3ff << 19)
+#define OUT_REG_LRCK_AUTO_MODE_SFT 29
+#define OUT_REG_LRCK_AUTO_MODE_MASK 0x1
+#define OUT_REG_LRCK_AUTO_MODE_MASK_SFT (0x1 << 29)
+#define OUT_REG_DIRECT_INPUT_MASTER_BCK_SFT 30
+#define OUT_REG_DIRECT_INPUT_MASTER_BCK_MASK 0x1
+#define OUT_REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT (0x1 << 30)
+#define OUT_REG_16B_COMPACT_MODE_SFT 31
+#define OUT_REG_16B_COMPACT_MODE_MASK 0x1
+#define OUT_REG_16B_COMPACT_MODE_MASK_SFT (0x1 << 31)
+
+/* ETDM_OUT0_CON2 */
+/* ETDM_OUT1_CON2 */
+/* ETDM_OUT4_CON2 */
+#define OUT_REG_IN2LATCH_TIME_SFT 0
+#define OUT_REG_IN2LATCH_TIME_MASK 0x1f
+#define OUT_REG_IN2LATCH_TIME_MASK_SFT (0x1f << 0)
+#define OUT_REG_MASK_NUM_SFT 5
+#define OUT_REG_MASK_NUM_MASK 0x1f
+#define OUT_REG_MASK_NUM_MASK_SFT (0x1f << 5)
+#define OUT_REG_MASK_AUTO_SFT 10
+#define OUT_REG_MASK_AUTO_MASK 0x1
+#define OUT_REG_MASK_AUTO_MASK_SFT (0x1 << 10)
+#define OUT_REG_SDATA_SHIFT_SFT 11
+#define OUT_REG_SDATA_SHIFT_MASK 0x3
+#define OUT_REG_SDATA_SHIFT_MASK_SFT (0x3 << 11)
+#define OUT_REG_ALMOST_END_BIT_COUNT_SFT 13
+#define OUT_REG_ALMOST_END_BIT_COUNT_MASK 0x1f
+#define OUT_REG_ALMOST_END_BIT_COUNT_MASK_SFT (0x1f << 13)
+#define OUT_REG_SDATA_CON_SFT 18
+#define OUT_REG_SDATA_CON_MASK 0x3
+#define OUT_REG_SDATA_CON_MASK_SFT (0x3 << 18)
+#define OUT_REG_REDUNDANT_0_SFT 20
+#define OUT_REG_REDUNDANT_0_MASK 0x1
+#define OUT_REG_REDUNDANT_0_MASK_SFT (0x1 << 20)
+#define OUT_REG_SDATA_AUTO_OFF_SFT 21
+#define OUT_REG_SDATA_AUTO_OFF_MASK 0x1
+#define OUT_REG_SDATA_AUTO_OFF_MASK_SFT (0x1 << 21)
+#define OUT_REG_BCK_OFF_TIME_SFT 22
+#define OUT_REG_BCK_OFF_TIME_MASK 0x3
+#define OUT_REG_BCK_OFF_TIME_MASK_SFT (0x3 << 22)
+#define OUT_REG_MONITOR_SEL_SFT 24
+#define OUT_REG_MONITOR_SEL_MASK 0x3
+#define OUT_REG_MONITOR_SEL_MASK_SFT (0x3 << 24)
+#define OUT_REG_SHIFT_AUTO_SFT 26
+#define OUT_REG_SHIFT_AUTO_MASK 0x1
+#define OUT_REG_SHIFT_AUTO_MASK_SFT (0x1 << 26)
+#define OUT_REG_SDATA_DELAY_0P5T_EN_SFT 27
+#define OUT_REG_SDATA_DELAY_0P5T_EN_MASK 0x1
+#define OUT_REG_SDATA_DELAY_0P5T_EN_MASK_SFT (0x1 << 27)
+#define OUT_REG_SDATA_DELAY_BCK_INV_SFT 28
+#define OUT_REG_SDATA_DELAY_BCK_INV_MASK 0x1
+#define OUT_REG_SDATA_DELAY_BCK_INV_MASK_SFT (0x1 << 28)
+#define OUT_REG_LRCK_DELAY_0P5T_EN_SFT 29
+#define OUT_REG_LRCK_DELAY_0P5T_EN_MASK 0x1
+#define OUT_REG_LRCK_DELAY_0P5T_EN_MASK_SFT (0x1 << 29)
+#define OUT_REG_LRCK_DELAY_BCK_INV_SFT 30
+#define OUT_REG_LRCK_DELAY_BCK_INV_MASK 0x1
+#define OUT_REG_LRCK_DELAY_BCK_INV_MASK_SFT (0x1 << 30)
+#define OUT_REG_OFF_CR_EN_SFT 31
+#define OUT_REG_OFF_CR_EN_MASK 0x1
+#define OUT_REG_OFF_CR_EN_MASK_SFT (0x1 << 31)
+
+/* ETDM_OUT0_CON3 */
+/* ETDM_OUT1_CON3 */
+/* ETDM_OUT4_CON3 */
+#define OUT_REG_START_CH_PAIR0_SFT 0
+#define OUT_REG_START_CH_PAIR0_MASK 0xf
+#define OUT_REG_START_CH_PAIR0_MASK_SFT (0xf << 0)
+#define OUT_REG_START_CH_PAIR1_SFT 4
+#define OUT_REG_START_CH_PAIR1_MASK 0xf
+#define OUT_REG_START_CH_PAIR1_MASK_SFT (0xf << 4)
+#define OUT_REG_START_CH_PAIR2_SFT 8
+#define OUT_REG_START_CH_PAIR2_MASK 0xf
+#define OUT_REG_START_CH_PAIR2_MASK_SFT (0xf << 8)
+#define OUT_REG_START_CH_PAIR3_SFT 12
+#define OUT_REG_START_CH_PAIR3_MASK 0xf
+#define OUT_REG_START_CH_PAIR3_MASK_SFT (0xf << 12)
+#define OUT_REG_START_CH_PAIR4_SFT 16
+#define OUT_REG_START_CH_PAIR4_MASK 0xf
+#define OUT_REG_START_CH_PAIR4_MASK_SFT (0xf << 16)
+#define OUT_REG_START_CH_PAIR5_SFT 20
+#define OUT_REG_START_CH_PAIR5_MASK 0xf
+#define OUT_REG_START_CH_PAIR5_MASK_SFT (0xf << 20)
+#define OUT_REG_START_CH_PAIR6_SFT 24
+#define OUT_REG_START_CH_PAIR6_MASK 0xf
+#define OUT_REG_START_CH_PAIR6_MASK_SFT (0xf << 24)
+#define OUT_REG_START_CH_PAIR7_SFT 28
+#define OUT_REG_START_CH_PAIR7_MASK 0xf
+#define OUT_REG_START_CH_PAIR7_MASK_SFT (0xf << 28)
+
+/* ETDM_OUT0_CON4 */
+/* ETDM_OUT1_CON4 */
+/* ETDM_OUT4_CON4 */
+#define OUT_REG_FS_TIMING_SEL_SFT 0
+#define OUT_REG_FS_TIMING_SEL_MASK 0x1f
+#define OUT_REG_FS_TIMING_SEL_MASK_SFT (0x1f << 0)
+#define OUT_REG_CLOCK_SOURCE_SEL_SFT 6
+#define OUT_REG_CLOCK_SOURCE_SEL_MASK 0x7
+#define OUT_REG_CLOCK_SOURCE_SEL_MASK_SFT (0x7 << 6)
+#define OUT_REG_CK_EN_SEL_AUTO_SFT 10
+#define OUT_REG_CK_EN_SEL_AUTO_MASK 0x1
+#define OUT_REG_CK_EN_SEL_AUTO_MASK_SFT (0x1 << 10)
+#define OUT_REG_ASYNC_RESET_SFT 11
+#define OUT_REG_ASYNC_RESET_MASK 0x1
+#define OUT_REG_ASYNC_RESET_MASK_SFT (0x1 << 11)
+#define OUT_REG_CK_EN_SEL_MANUAL_SFT 14
+#define OUT_REG_CK_EN_SEL_MANUAL_MASK 0x3ff
+#define OUT_REG_CK_EN_SEL_MANUAL_MASK_SFT (0x3ff << 14)
+#define OUT_REG_RELATCH_EN_SEL_SFT 24
+#define OUT_REG_RELATCH_EN_SEL_MASK 0x1f
+#define OUT_REG_RELATCH_EN_SEL_MASK_SFT (0x1f << 24)
+#define OUT_REG_WAIT_LAST_SAMPLE_SFT 30
+#define OUT_REG_WAIT_LAST_SAMPLE_MASK 0x1
+#define OUT_REG_WAIT_LAST_SAMPLE_MASK_SFT (0x1 << 30)
+#define OUT_REG_ALWAYS_OPEN_1X_EN_SFT 31
+#define OUT_REG_ALWAYS_OPEN_1X_EN_MASK 0x1
+#define OUT_REG_ALWAYS_OPEN_1X_EN_MASK_SFT (0x1 << 31)
+
+/* ETDM_OUT0_CON5 */
+/* ETDM_OUT1_CON5 */
+/* ETDM_OUT4_CON5 */
+#define OUT_REG_REPACK_BITNUM_SFT 0
+#define OUT_REG_REPACK_BITNUM_MASK 0x3
+#define OUT_REG_REPACK_BITNUM_MASK_SFT (0x3 << 0)
+#define OUT_REG_REPACK_CHNUM_SFT 2
+#define OUT_REG_REPACK_CHNUM_MASK 0xf
+#define OUT_REG_REPACK_CHNUM_MASK_SFT (0xf << 2)
+#define OUT_REG_SLAVE_BCK_INV_SFT 7
+#define OUT_REG_SLAVE_BCK_INV_MASK 0x1
+#define OUT_REG_SLAVE_BCK_INV_MASK_SFT (0x1 << 7)
+#define OUT_REG_SLAVE_LRCK_INV_SFT 8
+#define OUT_REG_SLAVE_LRCK_INV_MASK 0x1
+#define OUT_REG_SLAVE_LRCK_INV_MASK_SFT (0x1 << 8)
+#define OUT_REG_MASTER_BCK_INV_SFT 9
+#define OUT_REG_MASTER_BCK_INV_MASK 0x1
+#define OUT_REG_MASTER_BCK_INV_MASK_SFT (0x1 << 9)
+#define OUT_REG_MASTER_WS_INV_SFT 10
+#define OUT_REG_MASTER_WS_INV_MASK 0x1
+#define OUT_REG_MASTER_WS_INV_MASK_SFT (0x1 << 10)
+#define OUT_REG_REPACK_24B_MSB_ALIGN_SFT 11
+#define OUT_REG_REPACK_24B_MSB_ALIGN_MASK 0x1
+#define OUT_REG_REPACK_24B_MSB_ALIGN_MASK_SFT (0x1 << 11)
+#define OUT_REG_LR_SWAP_SFT 16
+#define OUT_REG_LR_SWAP_MASK 0xffff
+#define OUT_REG_LR_SWAP_MASK_SFT (0xffff << 16)
+
+/* ETDM_OUT0_CON6 */
+/* ETDM_OUT1_CON6 */
+/* ETDM_OUT4_CON6 */
+#define OUT_LCH_DATA_REG_SFT 0
+#define OUT_LCH_DATA_REG_MASK 0xffffffff
+#define OUT_LCH_DATA_REG_MASK_SFT (0xffffffff << 0)
+
+/* ETDM_OUT0_CON7 */
+/* ETDM_OUT1_CON7 */
+/* ETDM_OUT4_CON7 */
+#define OUT_RCH_DATA_REG_SFT 0
+#define OUT_RCH_DATA_REG_MASK 0xffffffff
+#define OUT_RCH_DATA_REG_MASK_SFT (0xffffffff << 0)
+
+/* ETDM_OUT0_CON8 */
+/* ETDM_OUT1_CON8 */
+/* ETDM_OUT4_CON8 */
+#define OUT_REG_START_CH_PAIR8_SFT 0
+#define OUT_REG_START_CH_PAIR8_MASK 0xf
+#define OUT_REG_START_CH_PAIR8_MASK_SFT (0xf << 0)
+#define OUT_REG_START_CH_PAIR9_SFT 4
+#define OUT_REG_START_CH_PAIR9_MASK 0xf
+#define OUT_REG_START_CH_PAIR9_MASK_SFT (0xf << 4)
+#define OUT_REG_START_CH_PAIR10_SFT 8
+#define OUT_REG_START_CH_PAIR10_MASK 0xf
+#define OUT_REG_START_CH_PAIR10_MASK_SFT (0xf << 8)
+#define OUT_REG_START_CH_PAIR11_SFT 12
+#define OUT_REG_START_CH_PAIR11_MASK 0xf
+#define OUT_REG_START_CH_PAIR11_MASK_SFT (0xf << 12)
+#define OUT_REG_START_CH_PAIR12_SFT 16
+#define OUT_REG_START_CH_PAIR12_MASK 0xf
+#define OUT_REG_START_CH_PAIR12_MASK_SFT (0xf << 16)
+#define OUT_REG_START_CH_PAIR13_SFT 20
+#define OUT_REG_START_CH_PAIR13_MASK 0xf
+#define OUT_REG_START_CH_PAIR13_MASK_SFT (0xf << 20)
+#define OUT_REG_START_CH_PAIR14_SFT 24
+#define OUT_REG_START_CH_PAIR14_MASK 0xf
+#define OUT_REG_START_CH_PAIR14_MASK_SFT (0xf << 24)
+#define OUT_REG_START_CH_PAIR15_SFT 28
+#define OUT_REG_START_CH_PAIR15_MASK 0xf
+#define OUT_REG_START_CH_PAIR15_MASK_SFT (0xf << 28)
+
+/* ETDM_OUT0_CON9 */
+/* ETDM_OUT1_CON9 */
+/* ETDM_OUT4_CON9 */
+#define OUT_REG_AFIFO_THRESHOLD_SFT 29
+#define OUT_REG_AFIFO_THRESHOLD_MASK 0x3
+#define OUT_REG_AFIFO_THRESHOLD_MASK_SFT (0x3 << 29)
+#define OUT_REG_AFIFO_SW_RESET_SFT 15
+#define OUT_REG_AFIFO_SW_RESET_MASK 0x1
+#define OUT_REG_AFIFO_SW_RESET_MASK_SFT (0x1 << 15)
+#define OUT_REG_AFIFO_RESET_SEL_SFT 14
+#define OUT_REG_AFIFO_RESET_SEL_MASK 0x1
+#define OUT_REG_AFIFO_RESET_SEL_MASK_SFT (0x1 << 14)
+#define OUT_REG_AFIFO_AUTO_RESET_DIS_SFT 9
+#define OUT_REG_AFIFO_AUTO_RESET_DIS_MASK 0x1
+#define OUT_REG_AFIFO_AUTO_RESET_DIS_MASK_SFT (0x1 << 9)
+#define OUT_REG_ETDM_USE_AFIFO_SFT 8
+#define OUT_REG_ETDM_USE_AFIFO_MASK 0x1
+#define OUT_REG_ETDM_USE_AFIFO_MASK_SFT (0x1 << 8)
+#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_SFT 5
+#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK 0x7
+#define OUT_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT (0x7 << 5)
+#define OUT_REG_AFIFO_MODE_SFT 0
+#define OUT_REG_AFIFO_MODE_MASK 0x1f
+#define OUT_REG_AFIFO_MODE_MASK_SFT (0x1f << 0)
+
+/* ETDM_OUT0_MON */
+/* ETDM_OUT1_MON */
+/* ETDM_OUT4_MON */
+#define LRCK_INV_SFT 30
+#define LRCK_INV_MASK 0x1
+#define LRCK_INV_MASK_SFT (0x1 << 30)
+#define EN_SYNC_OUT_SFT 29
+#define EN_SYNC_OUT_MASK 0x1
+#define EN_SYNC_OUT_MASK_SFT (0x1 << 29)
+#define HOPPING_EN_SYNC_OUT_PRE_SFT 28
+#define HOPPING_EN_SYNC_OUT_PRE_MASK 0x1
+#define HOPPING_EN_SYNC_OUT_PRE_MASK_SFT (0x1 << 28)
+#define ETDM_2X_CK_EN_SFT 25
+#define ETDM_2X_CK_EN_MASK 0x1
+#define ETDM_2X_CK_EN_MASK_SFT (0x1 << 25)
+#define ETDM_1X_CK_EN_SFT 24
+#define ETDM_1X_CK_EN_MASK 0x1
+#define ETDM_1X_CK_EN_MASK_SFT (0x1 << 24)
+#define SDATA0_SFT 23
+#define SDATA0_MASK 0x1
+#define SDATA0_MASK_SFT (0x1 << 23)
+#define CURRENT_STATUS_SFT 21
+#define CURRENT_STATUS_MASK 0x3
+#define CURRENT_STATUS_MASK_SFT (0x3 << 21)
+#define BIT_POINT_SFT 16
+#define BIT_POINT_MASK 0x1f
+#define BIT_POINT_MASK_SFT (0x1f << 16)
+#define BIT_CH_COUNT_SFT 10
+#define BIT_CH_COUNT_MASK 0x3f
+#define BIT_CH_COUNT_MASK_SFT (0x3f << 10)
+#define BIT_COUNT_SFT 5
+#define BIT_COUNT_MASK 0x1f
+#define BIT_COUNT_MASK_SFT (0x1f << 5)
+#define CH_COUNT_SFT 0
+#define CH_COUNT_MASK 0x1f
+#define CH_COUNT_MASK_SFT (0x1f << 0)
+
+/* ETDM_0_3_COWORK_CON0 */
+#define ETDM_OUT0_DATA_SEL_SFT 0
+#define ETDM_OUT0_DATA_SEL_MASK 0xf
+#define ETDM_OUT0_DATA_SEL_MASK_SFT (0xf << 0)
+#define ETDM_OUT0_SYNC_SEL_SFT 4
+#define ETDM_OUT0_SYNC_SEL_MASK 0xf
+#define ETDM_OUT0_SYNC_SEL_MASK_SFT (0xf << 4)
+#define ETDM_OUT0_SLAVE_SEL_SFT 8
+#define ETDM_OUT0_SLAVE_SEL_MASK 0xf
+#define ETDM_OUT0_SLAVE_SEL_MASK_SFT (0xf << 8)
+#define ETDM_OUT1_DATA_SEL_SFT 12
+#define ETDM_OUT1_DATA_SEL_MASK 0xf
+#define ETDM_OUT1_DATA_SEL_MASK_SFT (0xf << 12)
+#define ETDM_OUT1_SYNC_SEL_SFT 16
+#define ETDM_OUT1_SYNC_SEL_MASK 0xf
+#define ETDM_OUT1_SYNC_SEL_MASK_SFT (0xf << 16)
+#define ETDM_OUT1_SLAVE_SEL_SFT 20
+#define ETDM_OUT1_SLAVE_SEL_MASK 0xf
+#define ETDM_OUT1_SLAVE_SEL_MASK_SFT (0xf << 20)
+#define ETDM_IN0_SLAVE_SEL_SFT 24
+#define ETDM_IN0_SLAVE_SEL_MASK 0xf
+#define ETDM_IN0_SLAVE_SEL_MASK_SFT (0xf << 24)
+#define ETDM_IN0_SYNC_SEL_SFT 28
+#define ETDM_IN0_SYNC_SEL_MASK 0xf
+#define ETDM_IN0_SYNC_SEL_MASK_SFT (0xf << 28)
+
+/* ETDM_0_3_COWORK_CON1 */
+#define ETDM_IN0_SDATA0_SEL_SFT 0
+#define ETDM_IN0_SDATA0_SEL_MASK 0xf
+#define ETDM_IN0_SDATA0_SEL_MASK_SFT (0xf << 0)
+#define ETDM_IN0_SDATA1_15_SEL_SFT 4
+#define ETDM_IN0_SDATA1_15_SEL_MASK 0xf
+#define ETDM_IN0_SDATA1_15_SEL_MASK_SFT (0xf << 4)
+#define ETDM_IN1_SLAVE_SEL_SFT 8
+#define ETDM_IN1_SLAVE_SEL_MASK 0xf
+#define ETDM_IN1_SLAVE_SEL_MASK_SFT (0xf << 8)
+#define ETDM_IN1_SYNC_SEL_SFT 12
+#define ETDM_IN1_SYNC_SEL_MASK 0xf
+#define ETDM_IN1_SYNC_SEL_MASK_SFT (0xf << 12)
+#define ETDM_IN1_SDATA0_SEL_SFT 16
+#define ETDM_IN1_SDATA0_SEL_MASK 0xf
+#define ETDM_IN1_SDATA0_SEL_MASK_SFT (0xf << 16)
+#define ETDM_IN1_SDATA1_15_SEL_SFT 20
+#define ETDM_IN1_SDATA1_15_SEL_MASK 0xf
+#define ETDM_IN1_SDATA1_15_SEL_MASK_SFT (0xf << 20)
+
+/* ETDM_4_7_COWORK_CON0 */
+#define ETDM_OUT4_DATA_SEL_SFT 0
+#define ETDM_OUT4_DATA_SEL_MASK 0xf
+#define ETDM_OUT4_DATA_SEL_MASK_SFT (0xf << 0)
+#define ETDM_OUT4_SYNC_SEL_SFT 4
+#define ETDM_OUT4_SYNC_SEL_MASK 0xf
+#define ETDM_OUT4_SYNC_SEL_MASK_SFT (0xf << 4)
+#define ETDM_OUT4_SLAVE_SEL_SFT 8
+#define ETDM_OUT4_SLAVE_SEL_MASK 0xf
+#define ETDM_OUT4_SLAVE_SEL_MASK_SFT (0xf << 8)
+
+/* AFE_DPTX_CON */
+#define DPTX_CHANNEL_ENABLE_SFT 8
+#define DPTX_CHANNEL_ENABLE_MASK 0xff
+#define DPTX_CHANNEL_ENABLE_MASK_SFT (0xff << 8)
+#define DPTX_REGISTER_MONITOR_SELECT_SFT 3
+#define DPTX_REGISTER_MONITOR_SELECT_MASK 0xf
+#define DPTX_REGISTER_MONITOR_SELECT_MASK_SFT (0xf << 3)
+#define DPTX_16BIT_SFT 2
+#define DPTX_16BIT_MASK 0x1
+#define DPTX_16BIT_MASK_SFT (0x1 << 2)
+#define DPTX_CHANNEL_NUMBER_SFT 1
+#define DPTX_CHANNEL_NUMBER_MASK 0x1
+#define DPTX_CHANNEL_NUMBER_MASK_SFT (0x1 << 1)
+#define DPTX_ON_SFT 0
+#define DPTX_ON_MASK 0x1
+#define DPTX_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_DPTX_MON */
+#define AFE_DPTX_MON0_SFT 0
+#define AFE_DPTX_MON0_MASK 0xffffffff
+#define AFE_DPTX_MON0_MASK_SFT (0xffffffff << 0)
+
+/* AFE_TDM_CON1 */
+#define TDM_EN_SFT 0
+#define TDM_EN_MASK 0x1
+#define TDM_EN_MASK_SFT (0x1 << 0)
+#define BCK_INVERSE_SFT 1
+#define BCK_INVERSE_MASK 0x1
+#define BCK_INVERSE_MASK_SFT (0x1 << 1)
+#define LRCK_INVERSE_SFT 2
+#define LRCK_INVERSE_MASK 0x1
+#define LRCK_INVERSE_MASK_SFT (0x1 << 2)
+#define DELAY_DATA_SFT 3
+#define DELAY_DATA_MASK 0x1
+#define DELAY_DATA_MASK_SFT (0x1 << 3)
+#define LEFT_ALIGN_SFT 4
+#define LEFT_ALIGN_MASK 0x1
+#define LEFT_ALIGN_MASK_SFT (0x1 << 4)
+#define TDM_LRCK_D0P5T_SFT 5
+#define TDM_LRCK_D0P5T_MASK 0x1
+#define TDM_LRCK_D0P5T_MASK_SFT (0x1 << 5)
+#define TDM_SDATA_D0P5T_SFT 6
+#define TDM_SDATA_D0P5T_MASK 0x1
+#define TDM_SDATA_D0P5T_MASK_SFT (0x1 << 6)
+#define WLEN_SFT 8
+#define WLEN_MASK 0x3
+#define WLEN_MASK_SFT (0x3 << 8)
+#define CHANNEL_NUM_SFT 10
+#define CHANNEL_NUM_MASK 0x3
+#define CHANNEL_NUM_MASK_SFT (0x3 << 10)
+#define CHANNEL_BCK_CYCLES_SFT 12
+#define CHANNEL_BCK_CYCLES_MASK 0x3
+#define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12)
+#define HDMI_CLK_INV_SEL_SFT 15
+#define HDMI_CLK_INV_SEL_MASK 0x1
+#define HDMI_CLK_INV_SEL_MASK_SFT (0x1 << 15)
+#define DAC_BIT_NUM_SFT 16
+#define DAC_BIT_NUM_MASK 0x1f
+#define DAC_BIT_NUM_MASK_SFT (0x1f << 16)
+#define LRCK_TDM_WIDTH_SFT 24
+#define LRCK_TDM_WIDTH_MASK 0xff
+#define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24)
+
+/* AFE_TDM_CON2 */
+#define ST_CH_PAIR_SOUT0_SFT 0
+#define ST_CH_PAIR_SOUT0_MASK 0x7
+#define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0)
+#define ST_CH_PAIR_SOUT1_SFT 4
+#define ST_CH_PAIR_SOUT1_MASK 0x7
+#define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4)
+#define ST_CH_PAIR_SOUT2_SFT 8
+#define ST_CH_PAIR_SOUT2_MASK 0x7
+#define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8)
+#define ST_CH_PAIR_SOUT3_SFT 12
+#define ST_CH_PAIR_SOUT3_MASK 0x7
+#define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12)
+#define TDM_FIX_VALUE_SEL_SFT 16
+#define TDM_FIX_VALUE_SEL_MASK 0x1
+#define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16)
+#define TDM_I2S_LOOPBACK_SFT 20
+#define TDM_I2S_LOOPBACK_MASK 0x1
+#define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20)
+#define TDM_I2S_LOOPBACK_CH_SFT 21
+#define TDM_I2S_LOOPBACK_CH_MASK 0x3
+#define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21)
+#define TDM_USE_SINEGEN_INPUT_SFT 23
+#define TDM_USE_SINEGEN_INPUT_MASK 0x1
+#define TDM_USE_SINEGEN_INPUT_MASK_SFT (0x1 << 23)
+#define TDM_FIX_VALUE_SFT 24
+#define TDM_FIX_VALUE_MASK 0xff
+#define TDM_FIX_VALUE_MASK_SFT (0xff << 24)
+
+/* AFE_TDM_CON3 */
+#define TDM_OUT_SEL_DOMAIN_SFT 29
+#define TDM_OUT_SEL_DOMAIN_MASK 0x7
+#define TDM_OUT_SEL_DOMAIN_MASK_SFT (0x7 << 29)
+#define TDM_OUT_SEL_FS_SFT 24
+#define TDM_OUT_SEL_FS_MASK 0x1f
+#define TDM_OUT_SEL_FS_MASK_SFT (0x1f << 24)
+#define TDM_OUT_MON_SEL_SFT 3
+#define TDM_OUT_MON_SEL_MASK 0x1
+#define TDM_OUT_MON_SEL_MASK_SFT (0x1 << 3)
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_SFT 2
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 2)
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_SFT 1
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_MASK 0x1
+#define RG_TDM_OUT_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 1)
+#define TDM_UPDATE_EN_SEL_SFT 0
+#define TDM_UPDATE_EN_SEL_MASK 0x1
+#define TDM_UPDATE_EN_SEL_MASK_SFT (0x1 << 0)
+
+/* AFE_TDM_OUT_MON */
+#define AFE_TDM_OUT_MON_SFT 0
+#define AFE_TDM_OUT_MON_MASK 0xffffffff
+#define AFE_TDM_OUT_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_HDMI_CONN0 */
+#define HDMI_O_7_SFT 21
+#define HDMI_O_7_MASK 0x7
+#define HDMI_O_7_MASK_SFT (0x7 << 21)
+#define HDMI_O_6_SFT 18
+#define HDMI_O_6_MASK 0x7
+#define HDMI_O_6_MASK_SFT (0x7 << 18)
+#define HDMI_O_5_SFT 15
+#define HDMI_O_5_MASK 0x7
+#define HDMI_O_5_MASK_SFT (0x7 << 15)
+#define HDMI_O_4_SFT 12
+#define HDMI_O_4_MASK 0x7
+#define HDMI_O_4_MASK_SFT (0x7 << 12)
+#define HDMI_O_3_SFT 9
+#define HDMI_O_3_MASK 0x7
+#define HDMI_O_3_MASK_SFT (0x7 << 9)
+#define HDMI_O_2_SFT 6
+#define HDMI_O_2_MASK 0x7
+#define HDMI_O_2_MASK_SFT (0x7 << 6)
+#define HDMI_O_1_SFT 3
+#define HDMI_O_1_MASK 0x7
+#define HDMI_O_1_MASK_SFT (0x7 << 3)
+#define HDMI_O_0_SFT 0
+#define HDMI_O_0_MASK 0x7
+#define HDMI_O_0_MASK_SFT (0x7 << 0)
+
+/* AFE_TDM_TOP_IP_VERSION */
+#define AFE_TDM_TOP_IP_VERSION_SFT 0
+#define AFE_TDM_TOP_IP_VERSION_MASK 0xffffffff
+#define AFE_TDM_TOP_IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+/* AFE_HDMI_OUT_BASE_MSB */
+#define AFE_HDMI_OUT_BASE_MSB_SFT 0
+#define AFE_HDMI_OUT_BASE_MSB_MASK 0x1ff
+#define AFE_HDMI_OUT_BASE_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_HDMI_OUT_BASE */
+#define AFE_HDMI_OUT_BASE_SFT 4
+#define AFE_HDMI_OUT_BASE_MASK 0xfffffff
+#define AFE_HDMI_OUT_BASE_MASK_SFT (0xfffffff << 4)
+
+/* AFE_HDMI_OUT_CUR_MSB */
+#define AFE_HDMI_OUT_CUR_MSB_SFT 0
+#define AFE_HDMI_OUT_CUR_MSB_MASK 0x1ff
+#define AFE_HDMI_OUT_CUR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_HDMI_OUT_CUR */
+#define AFE_HDMI_OUT_CUR_SFT 0
+#define AFE_HDMI_OUT_CUR_MASK 0xffffffff
+#define AFE_HDMI_OUT_CUR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_HDMI_OUT_END_MSB */
+#define AFE_HDMI_OUT_END_MSB_SFT 0
+#define AFE_HDMI_OUT_END_MSB_MASK 0x1ff
+#define AFE_HDMI_OUT_END_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_HDMI_OUT_END */
+#define AFE_HDMI_OUT_END_SFT 4
+#define AFE_HDMI_OUT_END_MASK 0xfffffff
+#define AFE_HDMI_OUT_END_MASK_SFT (0xfffffff << 4)
+#define AFE_HDMI_OUT_END_LSB_SFT 0
+#define AFE_HDMI_OUT_END_LSB_MASK 0xf
+#define AFE_HDMI_OUT_END_LSB_MASK_SFT (0xf << 0)
+
+/* AFE_HDMI_OUT_CON0 */
+#define HDMI_OUT_ON_SFT 28
+#define HDMI_OUT_ON_MASK 0x1
+#define HDMI_OUT_ON_MASK_SFT (0x1 << 28)
+#define HDMI_CH_NUM_SFT 24
+#define HDMI_CH_NUM_MASK 0xf
+#define HDMI_CH_NUM_MASK_SFT (0xf << 24)
+#define HDMI_OUT_ONE_HEART_SEL_SFT 22
+#define HDMI_OUT_ONE_HEART_SEL_MASK 0x3
+#define HDMI_OUT_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define HDMI_OUT_MINLEN_SFT 20
+#define HDMI_OUT_MINLEN_MASK 0x3
+#define HDMI_OUT_MINLEN_MASK_SFT (0x3 << 20)
+#define HDMI_OUT_MAXLEN_SFT 16
+#define HDMI_OUT_MAXLEN_MASK 0x3
+#define HDMI_OUT_MAXLEN_MASK_SFT (0x3 << 16)
+#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_SFT 15
+#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
+#define HDMI_OUT_PBUF_SIZE_SFT 12
+#define HDMI_OUT_PBUF_SIZE_MASK 0x3
+#define HDMI_OUT_PBUF_SIZE_MASK_SFT (0x3 << 12)
+#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_SFT 7
+#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_MASK 0x1
+#define HDMI_OUT_SW_CLEAR_HDMI_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define HDMI_OUT_NORMAL_MODE_SFT 5
+#define HDMI_OUT_NORMAL_MODE_MASK 0x1
+#define HDMI_OUT_NORMAL_MODE_MASK_SFT (0x1 << 5)
+#define HDMI_OUT_HALIGN_SFT 4
+#define HDMI_OUT_HALIGN_MASK 0x1
+#define HDMI_OUT_HALIGN_MASK_SFT (0x1 << 4)
+#define HDMI_OUT_HD_MODE_SFT 0
+#define HDMI_OUT_HD_MODE_MASK 0x3
+#define HDMI_OUT_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_CBIP_CFG0 */
+#define CBIP_TOP_SLV_MUX_WAY_EN_SFT 16
+#define CBIP_TOP_SLV_MUX_WAY_EN_MASK 0xffff
+#define CBIP_TOP_SLV_MUX_WAY_EN_MASK_SFT (0xffff << 16)
+#define RESERVED_04_SFT 15
+#define RESERVED_04_MASK 0x1
+#define RESERVED_04_MASK_SFT (0x1 << 15)
+#define CBIP_ASYNC_MST_RG_FIFO_THRE_SFT 13
+#define CBIP_ASYNC_MST_RG_FIFO_THRE_MASK 0x3
+#define CBIP_ASYNC_MST_RG_FIFO_THRE_MASK_SFT (0x3 << 13)
+#define CBIP_ASYNC_MST_POSTWRITE_DIS_SFT 12
+#define CBIP_ASYNC_MST_POSTWRITE_DIS_MASK 0x1
+#define CBIP_ASYNC_MST_POSTWRITE_DIS_MASK_SFT (0x1 << 12)
+#define RESERVED_03_SFT 11
+#define RESERVED_03_MASK 0x1
+#define RESERVED_03_MASK_SFT (0x1 << 11)
+#define CBIP_ASYNC_SLV_RG_FIFO_THRE_SFT 9
+#define CBIP_ASYNC_SLV_RG_FIFO_THRE_MASK 0x3
+#define CBIP_ASYNC_SLV_RG_FIFO_THRE_MASK_SFT (0x3 << 9)
+#define CBIP_ASYNC_SLV_POSTWRITE_DIS_SFT 8
+#define CBIP_ASYNC_SLV_POSTWRITE_DIS_MASK 0x1
+#define CBIP_ASYNC_SLV_POSTWRITE_DIS_MASK_SFT (0x1 << 8)
+#define AUDIOSYS_BUSY_SFT 7
+#define AUDIOSYS_BUSY_MASK 0x1
+#define AUDIOSYS_BUSY_MASK_SFT (0x1 << 7)
+#define CBIP_SLV_DECODER_ERR_FLAG_EN_SFT 6
+#define CBIP_SLV_DECODER_ERR_FLAG_EN_MASK 0x1
+#define CBIP_SLV_DECODER_ERR_FLAG_EN_MASK_SFT (0x1 << 6)
+#define CBIP_SLV_DECODER_SLAVE_WAY_EN_SFT 5
+#define CBIP_SLV_DECODER_SLAVE_WAY_EN_MASK 0x1
+#define CBIP_SLV_DECODER_SLAVE_WAY_EN_MASK_SFT (0x1 << 5)
+#define APB_R2T_SFT 3
+#define APB_R2T_MASK 0x1
+#define APB_R2T_MASK_SFT (0x1 << 3)
+#define APB_W2T_SFT 2
+#define APB_W2T_MASK 0x1
+#define APB_W2T_MASK_SFT (0x1 << 2)
+#define AHB_IDLE_EN_INT_SFT 1
+#define AHB_IDLE_EN_INT_MASK 0x1
+#define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 1)
+#define AHB_IDLE_EN_EXT_SFT 0
+#define AHB_IDLE_EN_EXT_MASK 0x1
+#define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 0)
+
+/* AFE_CBIP_SLV_DECODER_MON0 */
+#define CBIP_SLV_DECODER_ERR_DOMAIN_SFT 4
+#define CBIP_SLV_DECODER_ERR_DOMAIN_MASK 0x1
+#define CBIP_SLV_DECODER_ERR_DOMAIN_MASK_SFT (0x1 << 4)
+#define CBIP_SLV_DECODER_ERR_ID_SFT 3
+#define CBIP_SLV_DECODER_ERR_ID_MASK 0x1
+#define CBIP_SLV_DECODER_ERR_ID_MASK_SFT (0x1 << 3)
+#define CBIP_SLV_DECODER_ERR_RW_SFT 2
+#define CBIP_SLV_DECODER_ERR_RW_MASK 0x1
+#define CBIP_SLV_DECODER_ERR_RW_MASK_SFT (0x1 << 2)
+#define CBIP_SLV_DECODER_ERR_DECERR_SFT 1
+#define CBIP_SLV_DECODER_ERR_DECERR_MASK 0x1
+#define CBIP_SLV_DECODER_ERR_DECERR_MASK_SFT (0x1 << 1)
+#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_SFT 0
+#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_MASK 0x1
+#define CBIP_SLV_DECODER_CTRL_UPDATE_STATUS_MASK_SFT (0x1 << 0)
+
+/* AFE_CBIP_SLV_DECODER_MON1 */
+#define CBIP_SLV_DECODER_ERR_ADDR_SFT 0
+#define CBIP_SLV_DECODER_ERR_ADDR_MASK 0xffffffff
+#define CBIP_SLV_DECODER_ERR_ADDR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CBIP_SLV_MUX_MON_CFG */
+#define CBIP_SLV_MUX_ERR_FLAG_EN_SFT 3
+#define CBIP_SLV_MUX_ERR_FLAG_EN_MASK 0x1
+#define CBIP_SLV_MUX_ERR_FLAG_EN_MASK_SFT (0x1 << 3)
+#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_SFT 2
+#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_MASK 0x1
+#define CBIP_SLV_MUX_REG_SLAVE_WAY_EN_MASK_SFT (0x1 << 2)
+#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_SFT 0
+#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_MASK 0x3
+#define CBIP_SLV_MUX_REG_LAYER_WAY_EN_MASK_SFT (0x3 << 0)
+
+/* AFE_CBIP_SLV_MUX_MON0 */
+#define CBIP_SLV_MUX_ERR_DOMAIN_SFT 8
+#define CBIP_SLV_MUX_ERR_DOMAIN_MASK 0x1
+#define CBIP_SLV_MUX_ERR_DOMAIN_MASK_SFT (0x1 << 8)
+#define CBIP_SLV_MUX_ERR_ID_SFT 7
+#define CBIP_SLV_MUX_ERR_ID_MASK 0x1
+#define CBIP_SLV_MUX_ERR_ID_MASK_SFT (0x1 << 7)
+#define CBIP_SLV_MUX_ERR_RD_SFT 6
+#define CBIP_SLV_MUX_ERR_RD_MASK 0x1
+#define CBIP_SLV_MUX_ERR_RD_MASK_SFT (0x1 << 6)
+#define CBIP_SLV_MUX_ERR_WR_SFT 5
+#define CBIP_SLV_MUX_ERR_WR_MASK 0x1
+#define CBIP_SLV_MUX_ERR_WR_MASK_SFT (0x1 << 5)
+#define CBIP_SLV_MUX_ERR_EN_SLV_SFT 4
+#define CBIP_SLV_MUX_ERR_EN_SLV_MASK 0x1
+#define CBIP_SLV_MUX_ERR_EN_SLV_MASK_SFT (0x1 << 4)
+#define CBIP_SLV_MUX_ERR_EN_MST_SFT 2
+#define CBIP_SLV_MUX_ERR_EN_MST_MASK 0x3
+#define CBIP_SLV_MUX_ERR_EN_MST_MASK_SFT (0x3 << 2)
+#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_SFT 0
+#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_MASK 0x3
+#define CBIP_SLV_MUX_CTRL_UPDATE_STATUS_MASK_SFT (0x3 << 0)
+
+/* AFE_CBIP_SLV_MUX_MON1 */
+#define CBIP_SLV_MUX_ERR_ADDR_SFT 0
+#define CBIP_SLV_MUX_ERR_ADDR_MASK 0xffffffff
+#define CBIP_SLV_MUX_ERR_ADDR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_MEMIF_CON0 */
+#define CPU_COMPACT_MODE_SFT 2
+#define CPU_COMPACT_MODE_MASK 0x1
+#define CPU_COMPACT_MODE_MASK_SFT (0x1 << 2)
+#define CPU_HD_ALIGN_SFT 1
+#define CPU_HD_ALIGN_MASK 0x1
+#define CPU_HD_ALIGN_MASK_SFT (0x1 << 1)
+#define SYSRAM_SIGN_SFT 0
+#define SYSRAM_SIGN_MASK 0x1
+#define SYSRAM_SIGN_MASK_SFT (0x1 << 0)
+
+/* AFE_MEMIF_ONE_HEART */
+#define DL_ONE_HEART_ON_2_SFT 2
+#define DL_ONE_HEART_ON_2_MASK 0x1
+#define DL_ONE_HEART_ON_2_MASK_SFT (0x1 << 2)
+#define DL_ONE_HEART_ON_1_SFT 1
+#define DL_ONE_HEART_ON_1_MASK 0x1
+#define DL_ONE_HEART_ON_1_MASK_SFT (0x1 << 1)
+#define DL_ONE_HEART_ON_0_SFT 0
+#define DL_ONE_HEART_ON_0_MASK 0x1
+#define DL_ONE_HEART_ON_0_MASK_SFT (0x1 << 0)
+
+/* AFE_DL0_BASE_MSB */
+#define DL0_BASE_ADDR_MSB_SFT 0
+#define DL0_BASE_ADDR_MSB_MASK 0x1ff
+#define DL0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL0_BASE */
+#define DL0_BASE_ADDR_SFT 4
+#define DL0_BASE_ADDR_MASK 0xfffffff
+#define DL0_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL0_CUR_MSB */
+#define DL0_CUR_PTR_MSB_SFT 0
+#define DL0_CUR_PTR_MSB_MASK 0x1ff
+#define DL0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL0_CUR */
+#define DL0_CUR_PTR_SFT 0
+#define DL0_CUR_PTR_MASK 0xffffffff
+#define DL0_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL0_END_MSB */
+#define DL0_END_ADDR_MSB_SFT 0
+#define DL0_END_ADDR_MSB_MASK 0x1ff
+#define DL0_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL0_END */
+#define DL0_END_ADDR_SFT 4
+#define DL0_END_ADDR_MASK 0xfffffff
+#define DL0_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL0_RCH_MON */
+#define DL0_RCH_DATA_SFT 0
+#define DL0_RCH_DATA_MASK 0xffffffff
+#define DL0_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL0_LCH_MON */
+#define DL0_LCH_DATA_SFT 0
+#define DL0_LCH_DATA_MASK 0xffffffff
+#define DL0_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL0_CON0 */
+#define DL0_ON_SFT 28
+#define DL0_ON_MASK 0x1
+#define DL0_ON_MASK_SFT (0x1 << 28)
+#define DL0_ONE_HEART_SEL_SFT 22
+#define DL0_ONE_HEART_SEL_MASK 0x3
+#define DL0_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL0_MINLEN_SFT 20
+#define DL0_MINLEN_MASK 0x3
+#define DL0_MINLEN_MASK_SFT (0x3 << 20)
+#define DL0_MAXLEN_SFT 16
+#define DL0_MAXLEN_MASK 0x3
+#define DL0_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL0_SEL_DOMAIN_SFT 13
+#define DL0_SEL_DOMAIN_MASK 0x7
+#define DL0_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL0_SEL_FS_SFT 8
+#define DL0_SEL_FS_MASK 0x1f
+#define DL0_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL0_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL0_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL0_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL0_PBUF_SIZE_SFT 5
+#define DL0_PBUF_SIZE_MASK 0x3
+#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL0_MONO_SFT 4
+#define DL0_MONO_MASK 0x1
+#define DL0_MONO_MASK_SFT (0x1 << 4)
+#define DL0_NORMAL_MODE_SFT 3
+#define DL0_NORMAL_MODE_MASK 0x1
+#define DL0_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL0_HALIGN_SFT 2
+#define DL0_HALIGN_MASK 0x1
+#define DL0_HALIGN_MASK_SFT (0x1 << 2)
+#define DL0_HD_MODE_SFT 0
+#define DL0_HD_MODE_MASK 0x3
+#define DL0_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL0_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL1_BASE_MSB */
+#define DL1_BASE_ADDR_MSB_SFT 0
+#define DL1_BASE_ADDR_MSB_MASK 0x1ff
+#define DL1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL1_BASE */
+#define DL1_BASE_ADDR_SFT 4
+#define DL1_BASE_ADDR_MASK 0xfffffff
+#define DL1_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL1_CUR_MSB */
+#define DL1_CUR_PTR_MSB_SFT 0
+#define DL1_CUR_PTR_MSB_MASK 0x1ff
+#define DL1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL1_CUR */
+#define DL1_CUR_PTR_SFT 0
+#define DL1_CUR_PTR_MASK 0xffffffff
+#define DL1_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL1_END_MSB */
+#define DL1_END_ADDR_MSB_SFT 0
+#define DL1_END_ADDR_MSB_MASK 0x1ff
+#define DL1_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL1_END */
+#define DL1_END_ADDR_SFT 4
+#define DL1_END_ADDR_MASK 0xfffffff
+#define DL1_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL1_RCH_MON */
+#define DL1_RCH_DATA_SFT 0
+#define DL1_RCH_DATA_MASK 0xffffffff
+#define DL1_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL1_LCH_MON */
+#define DL1_LCH_DATA_SFT 0
+#define DL1_LCH_DATA_MASK 0xffffffff
+#define DL1_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL1_CON0 */
+#define DL1_ON_SFT 28
+#define DL1_ON_MASK 0x1
+#define DL1_ON_MASK_SFT (0x1 << 28)
+#define DL1_ONE_HEART_SEL_SFT 22
+#define DL1_ONE_HEART_SEL_MASK 0x3
+#define DL1_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL1_MINLEN_SFT 20
+#define DL1_MINLEN_MASK 0x3
+#define DL1_MINLEN_MASK_SFT (0x3 << 20)
+#define DL1_MAXLEN_SFT 16
+#define DL1_MAXLEN_MASK 0x3
+#define DL1_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL1_SEL_DOMAIN_SFT 13
+#define DL1_SEL_DOMAIN_MASK 0x7
+#define DL1_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL1_SEL_FS_SFT 8
+#define DL1_SEL_FS_MASK 0x1f
+#define DL1_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL1_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL1_PBUF_SIZE_SFT 5
+#define DL1_PBUF_SIZE_MASK 0x3
+#define DL1_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL1_MONO_SFT 4
+#define DL1_MONO_MASK 0x1
+#define DL1_MONO_MASK_SFT (0x1 << 4)
+#define DL1_NORMAL_MODE_SFT 3
+#define DL1_NORMAL_MODE_MASK 0x1
+#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL1_HALIGN_SFT 2
+#define DL1_HALIGN_MASK 0x1
+#define DL1_HALIGN_MASK_SFT (0x1 << 2)
+#define DL1_HD_MODE_SFT 0
+#define DL1_HD_MODE_MASK 0x3
+#define DL1_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL1_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL2_BASE_MSB */
+#define DL2_BASE__ADDR_MSB_SFT 0
+#define DL2_BASE__ADDR_MSB_MASK 0x1ff
+#define DL2_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL2_BASE */
+#define DL2_BASE_ADDR_SFT 4
+#define DL2_BASE_ADDR_MASK 0xfffffff
+#define DL2_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL2_CUR_MSB */
+#define DL2_CUR_PTR_MSB_SFT 0
+#define DL2_CUR_PTR_MSB_MASK 0x1ff
+#define DL2_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL2_CUR */
+#define DL2_CUR_PTR_SFT 0
+#define DL2_CUR_PTR_MASK 0xffffffff
+#define DL2_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL2_END_MSB */
+#define DL2_END_ADDR_MSB_SFT 0
+#define DL2_END_ADDR_MSB_MASK 0x1ff
+#define DL2_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL2_END */
+#define DL2_END_ADDR_SFT 4
+#define DL2_END_ADDR_MASK 0xfffffff
+#define DL2_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL2_RCH_MON */
+#define DL2_RCH_DATA_SFT 0
+#define DL2_RCH_DATA_MASK 0xffffffff
+#define DL2_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL2_LCH_MON */
+#define DL2_LCH_DATA_SFT 0
+#define DL2_LCH_DATA_MASK 0xffffffff
+#define DL2_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL2_CON0 */
+#define DL2_ON_SFT 28
+#define DL2_ON_MASK 0x1
+#define DL2_ON_MASK_SFT (0x1 << 28)
+#define DL2_ONE_HEART_SEL_SFT 22
+#define DL2_ONE_HEART_SEL_MASK 0x3
+#define DL2_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL2_MINLEN_SFT 20
+#define DL2_MINLEN_MASK 0x3
+#define DL2_MINLEN_MASK_SFT (0x3 << 20)
+#define DL2_MAXLEN_SFT 16
+#define DL2_MAXLEN_MASK 0x3
+#define DL2_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL2_SEL_DOMAIN_SFT 13
+#define DL2_SEL_DOMAIN_MASK 0x7
+#define DL2_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL2_SEL_FS_SFT 8
+#define DL2_SEL_FS_MASK 0x1f
+#define DL2_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL2_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL2_PBUF_SIZE_SFT 5
+#define DL2_PBUF_SIZE_MASK 0x3
+#define DL2_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL2_MONO_SFT 4
+#define DL2_MONO_MASK 0x1
+#define DL2_MONO_MASK_SFT (0x1 << 4)
+#define DL2_NORMAL_MODE_SFT 3
+#define DL2_NORMAL_MODE_MASK 0x1
+#define DL2_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL2_HALIGN_SFT 2
+#define DL2_HALIGN_MASK 0x1
+#define DL2_HALIGN_MASK_SFT (0x1 << 2)
+#define DL2_HD_MODE_SFT 0
+#define DL2_HD_MODE_MASK 0x3
+#define DL2_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL2_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL3_BASE_MSB */
+#define DL3_BASE__ADDR_MSB_SFT 0
+#define DL3_BASE__ADDR_MSB_MASK 0x1ff
+#define DL3_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL3_BASE */
+#define DL3_BASE_ADDR_SFT 4
+#define DL3_BASE_ADDR_MASK 0xfffffff
+#define DL3_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL3_CUR_MSB */
+#define DL3_CUR_PTR_MSB_SFT 0
+#define DL3_CUR_PTR_MSB_MASK 0x1ff
+#define DL3_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL3_CUR */
+#define DL3_CUR_PTR_SFT 0
+#define DL3_CUR_PTR_MASK 0xffffffff
+#define DL3_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL3_END_MSB */
+#define DL3_END_ADDR_MSB_SFT 0
+#define DL3_END_ADDR_MSB_MASK 0x1ff
+#define DL3_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL3_END */
+#define DL3_END_ADDR_SFT 4
+#define DL3_END_ADDR_MASK 0xfffffff
+#define DL3_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL3_RCH_MON */
+#define DL3_RCH_DATA_SFT 0
+#define DL3_RCH_DATA_MASK 0xffffffff
+#define DL3_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL3_LCH_MON */
+#define DL3_LCH_DATA_SFT 0
+#define DL3_LCH_DATA_MASK 0xffffffff
+#define DL3_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL3_CON0 */
+#define DL3_ON_SFT 28
+#define DL3_ON_MASK 0x1
+#define DL3_ON_MASK_SFT (0x1 << 28)
+#define DL3_ONE_HEART_SEL_SFT 22
+#define DL3_ONE_HEART_SEL_MASK 0x3
+#define DL3_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL3_MINLEN_SFT 20
+#define DL3_MINLEN_MASK 0x3
+#define DL3_MINLEN_MASK_SFT (0x3 << 20)
+#define DL3_MAXLEN_SFT 16
+#define DL3_MAXLEN_MASK 0x3
+#define DL3_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL3_SEL_DOMAIN_SFT 13
+#define DL3_SEL_DOMAIN_MASK 0x7
+#define DL3_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL3_SEL_FS_SFT 8
+#define DL3_SEL_FS_MASK 0x1f
+#define DL3_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL3_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL3_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL3_PBUF_SIZE_SFT 5
+#define DL3_PBUF_SIZE_MASK 0x3
+#define DL3_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL3_MONO_SFT 4
+#define DL3_MONO_MASK 0x1
+#define DL3_MONO_MASK_SFT (0x1 << 4)
+#define DL3_NORMAL_MODE_SFT 3
+#define DL3_NORMAL_MODE_MASK 0x1
+#define DL3_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL3_HALIGN_SFT 2
+#define DL3_HALIGN_MASK 0x1
+#define DL3_HALIGN_MASK_SFT (0x1 << 2)
+#define DL3_HD_MODE_SFT 0
+#define DL3_HD_MODE_MASK 0x3
+#define DL3_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL3_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL4_BASE_MSB */
+#define DL4_BASE__ADDR_MSB_SFT 0
+#define DL4_BASE__ADDR_MSB_MASK 0x1ff
+#define DL4_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL4_BASE */
+#define DL4_BASE_ADDR_SFT 4
+#define DL4_BASE_ADDR_MASK 0xfffffff
+#define DL4_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL4_CUR_MSB */
+#define DL4_CUR_PTR_MSB_SFT 0
+#define DL4_CUR_PTR_MSB_MASK 0x1ff
+#define DL4_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL4_CUR */
+#define DL4_CUR_PTR_SFT 0
+#define DL4_CUR_PTR_MASK 0xffffffff
+#define DL4_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL4_END_MSB */
+#define DL4_END_ADDR_MSB_SFT 0
+#define DL4_END_ADDR_MSB_MASK 0x1ff
+#define DL4_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL4_END */
+#define DL4_END_ADDR_SFT 4
+#define DL4_END_ADDR_MASK 0xfffffff
+#define DL4_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL4_RCH_MON */
+#define DL4_RCH_DATA_SFT 0
+#define DL4_RCH_DATA_MASK 0xffffffff
+#define DL4_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL4_LCH_MON */
+#define DL4_LCH_DATA_SFT 0
+#define DL4_LCH_DATA_MASK 0xffffffff
+#define DL4_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL4_CON0 */
+#define DL4_ON_SFT 28
+#define DL4_ON_MASK 0x1
+#define DL4_ON_MASK_SFT (0x1 << 28)
+#define DL4_ONE_HEART_SEL_SFT 22
+#define DL4_ONE_HEART_SEL_MASK 0x3
+#define DL4_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL4_MINLEN_SFT 20
+#define DL4_MINLEN_MASK 0x3
+#define DL4_MINLEN_MASK_SFT (0x3 << 20)
+#define DL4_MAXLEN_SFT 16
+#define DL4_MAXLEN_MASK 0x3
+#define DL4_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL4_SEL_DOMAIN_SFT 13
+#define DL4_SEL_DOMAIN_MASK 0x7
+#define DL4_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL4_SEL_FS_SFT 8
+#define DL4_SEL_FS_MASK 0x1f
+#define DL4_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL4_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL4_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL4_PBUF_SIZE_SFT 5
+#define DL4_PBUF_SIZE_MASK 0x3
+#define DL4_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL4_MONO_SFT 4
+#define DL4_MONO_MASK 0x1
+#define DL4_MONO_MASK_SFT (0x1 << 4)
+#define DL4_NORMAL_MODE_SFT 3
+#define DL4_NORMAL_MODE_MASK 0x1
+#define DL4_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL4_HALIGN_SFT 2
+#define DL4_HALIGN_MASK 0x1
+#define DL4_HALIGN_MASK_SFT (0x1 << 2)
+#define DL4_HD_MODE_SFT 0
+#define DL4_HD_MODE_MASK 0x3
+#define DL4_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL4_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL5_BASE_MSB */
+#define DL5_BASE__ADDR_MSB_SFT 0
+#define DL5_BASE__ADDR_MSB_MASK 0x1ff
+#define DL5_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL5_BASE */
+#define DL5_BASE_ADDR_SFT 4
+#define DL5_BASE_ADDR_MASK 0xfffffff
+#define DL5_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL5_CUR_MSB */
+#define DL5_CUR_PTR_MSB_SFT 0
+#define DL5_CUR_PTR_MSB_MASK 0x1ff
+#define DL5_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL5_CUR */
+#define DL5_CUR_PTR_SFT 0
+#define DL5_CUR_PTR_MASK 0xffffffff
+#define DL5_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL5_END_MSB */
+#define DL5_END_ADDR_MSB_SFT 0
+#define DL5_END_ADDR_MSB_MASK 0x1ff
+#define DL5_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL5_END */
+#define DL5_END_ADDR_SFT 4
+#define DL5_END_ADDR_MASK 0xfffffff
+#define DL5_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL5_RCH_MON */
+#define DL5_RCH_DATA_SFT 0
+#define DL5_RCH_DATA_MASK 0xffffffff
+#define DL5_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL5_LCH_MON */
+#define DL5_LCH_DATA_SFT 0
+#define DL5_LCH_DATA_MASK 0xffffffff
+#define DL5_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL5_CON0 */
+#define DL5_ON_SFT 28
+#define DL5_ON_MASK 0x1
+#define DL5_ON_MASK_SFT (0x1 << 28)
+#define DL5_ONE_HEART_SEL_SFT 22
+#define DL5_ONE_HEART_SEL_MASK 0x3
+#define DL5_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL5_MINLEN_SFT 20
+#define DL5_MINLEN_MASK 0x3
+#define DL5_MINLEN_MASK_SFT (0x3 << 20)
+#define DL5_MAXLEN_SFT 16
+#define DL5_MAXLEN_MASK 0x3
+#define DL5_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL5_SEL_DOMAIN_SFT 13
+#define DL5_SEL_DOMAIN_MASK 0x7
+#define DL5_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL5_SEL_FS_SFT 8
+#define DL5_SEL_FS_MASK 0x1f
+#define DL5_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL5_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL5_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL5_PBUF_SIZE_SFT 5
+#define DL5_PBUF_SIZE_MASK 0x3
+#define DL5_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL5_MONO_SFT 4
+#define DL5_MONO_MASK 0x1
+#define DL5_MONO_MASK_SFT (0x1 << 4)
+#define DL5_NORMAL_MODE_SFT 3
+#define DL5_NORMAL_MODE_MASK 0x1
+#define DL5_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL5_HALIGN_SFT 2
+#define DL5_HALIGN_MASK 0x1
+#define DL5_HALIGN_MASK_SFT (0x1 << 2)
+#define DL5_HD_MODE_SFT 0
+#define DL5_HD_MODE_MASK 0x3
+#define DL5_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL5_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL6_BASE_MSB */
+#define DL6_BASE__ADDR_MSB_SFT 0
+#define DL6_BASE__ADDR_MSB_MASK 0x1ff
+#define DL6_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL6_BASE */
+#define DL6_BASE_ADDR_SFT 4
+#define DL6_BASE_ADDR_MASK 0xfffffff
+#define DL6_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL6_CUR_MSB */
+#define DL6_CUR_PTR_MSB_SFT 0
+#define DL6_CUR_PTR_MSB_MASK 0x1ff
+#define DL6_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL6_CUR */
+#define DL6_CUR_PTR_SFT 0
+#define DL6_CUR_PTR_MASK 0xffffffff
+#define DL6_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL6_END_MSB */
+#define DL6_END_ADDR_MSB_SFT 0
+#define DL6_END_ADDR_MSB_MASK 0x1ff
+#define DL6_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL6_END */
+#define DL6_END_ADDR_SFT 4
+#define DL6_END_ADDR_MASK 0xfffffff
+#define DL6_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL6_RCH_MON */
+#define DL6_RCH_DATA_SFT 0
+#define DL6_RCH_DATA_MASK 0xffffffff
+#define DL6_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL6_LCH_MON */
+#define DL6_LCH_DATA_SFT 0
+#define DL6_LCH_DATA_MASK 0xffffffff
+#define DL6_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL6_CON0 */
+#define DL6_ON_SFT 28
+#define DL6_ON_MASK 0x1
+#define DL6_ON_MASK_SFT (0x1 << 28)
+#define DL6_ONE_HEART_SEL_SFT 22
+#define DL6_ONE_HEART_SEL_MASK 0x3
+#define DL6_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL6_MINLEN_SFT 20
+#define DL6_MINLEN_MASK 0x3
+#define DL6_MINLEN_MASK_SFT (0x3 << 20)
+#define DL6_MAXLEN_SFT 16
+#define DL6_MAXLEN_MASK 0x3
+#define DL6_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL6_SEL_DOMAIN_SFT 13
+#define DL6_SEL_DOMAIN_MASK 0x7
+#define DL6_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL6_SEL_FS_SFT 8
+#define DL6_SEL_FS_MASK 0x1f
+#define DL6_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL6_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL6_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL6_PBUF_SIZE_SFT 5
+#define DL6_PBUF_SIZE_MASK 0x3
+#define DL6_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL6_MONO_SFT 4
+#define DL6_MONO_MASK 0x1
+#define DL6_MONO_MASK_SFT (0x1 << 4)
+#define DL6_NORMAL_MODE_SFT 3
+#define DL6_NORMAL_MODE_MASK 0x1
+#define DL6_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL6_HALIGN_SFT 2
+#define DL6_HALIGN_MASK 0x1
+#define DL6_HALIGN_MASK_SFT (0x1 << 2)
+#define DL6_HD_MODE_SFT 0
+#define DL6_HD_MODE_MASK 0x3
+#define DL6_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL6_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL7_BASE_MSB */
+#define DL7_BASE__ADDR_MSB_SFT 0
+#define DL7_BASE__ADDR_MSB_MASK 0x1ff
+#define DL7_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL7_BASE */
+#define DL7_BASE_ADDR_SFT 4
+#define DL7_BASE_ADDR_MASK 0xfffffff
+#define DL7_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL7_CUR_MSB */
+#define DL7_CUR_PTR_MSB_SFT 0
+#define DL7_CUR_PTR_MSB_MASK 0x1ff
+#define DL7_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL7_CUR */
+#define DL7_CUR_PTR_SFT 0
+#define DL7_CUR_PTR_MASK 0xffffffff
+#define DL7_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL7_END_MSB */
+#define DL7_END_ADDR_MSB_SFT 0
+#define DL7_END_ADDR_MSB_MASK 0x1ff
+#define DL7_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL7_END */
+#define DL7_END_ADDR_SFT 4
+#define DL7_END_ADDR_MASK 0xfffffff
+#define DL7_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL7_RCH_MON */
+#define DL7_RCH_DATA_SFT 0
+#define DL7_RCH_DATA_MASK 0xffffffff
+#define DL7_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL7_LCH_MON */
+#define DL7_LCH_DATA_SFT 0
+#define DL7_LCH_DATA_MASK 0xffffffff
+#define DL7_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL7_CON0 */
+#define DL7_ON_SFT 28
+#define DL7_ON_MASK 0x1
+#define DL7_ON_MASK_SFT (0x1 << 28)
+#define DL7_ONE_HEART_SEL_SFT 22
+#define DL7_ONE_HEART_SEL_MASK 0x3
+#define DL7_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL7_MINLEN_SFT 20
+#define DL7_MINLEN_MASK 0x3
+#define DL7_MINLEN_MASK_SFT (0x3 << 20)
+#define DL7_MAXLEN_SFT 16
+#define DL7_MAXLEN_MASK 0x3
+#define DL7_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL7_SEL_DOMAIN_SFT 13
+#define DL7_SEL_DOMAIN_MASK 0x7
+#define DL7_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL7_SEL_FS_SFT 8
+#define DL7_SEL_FS_MASK 0x1f
+#define DL7_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL7_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL7_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL7_PBUF_SIZE_SFT 5
+#define DL7_PBUF_SIZE_MASK 0x3
+#define DL7_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL7_MONO_SFT 4
+#define DL7_MONO_MASK 0x1
+#define DL7_MONO_MASK_SFT (0x1 << 4)
+#define DL7_NORMAL_MODE_SFT 3
+#define DL7_NORMAL_MODE_MASK 0x1
+#define DL7_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL7_HALIGN_SFT 2
+#define DL7_HALIGN_MASK 0x1
+#define DL7_HALIGN_MASK_SFT (0x1 << 2)
+#define DL7_HD_MODE_SFT 0
+#define DL7_HD_MODE_MASK 0x3
+#define DL7_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL7_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL8_BASE_MSB */
+#define DL8_BASE__ADDR_MSB_SFT 0
+#define DL8_BASE__ADDR_MSB_MASK 0x1ff
+#define DL8_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL8_BASE */
+#define DL8_BASE_ADDR_SFT 4
+#define DL8_BASE_ADDR_MASK 0xfffffff
+#define DL8_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL8_CUR_MSB */
+#define DL8_CUR_PTR_MSB_SFT 0
+#define DL8_CUR_PTR_MSB_MASK 0x1ff
+#define DL8_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL8_CUR */
+#define DL8_CUR_PTR_SFT 0
+#define DL8_CUR_PTR_MASK 0xffffffff
+#define DL8_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL8_END_MSB */
+#define DL8_END_ADDR_MSB_SFT 0
+#define DL8_END_ADDR_MSB_MASK 0x1ff
+#define DL8_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL8_END */
+#define DL8_END_ADDR_SFT 4
+#define DL8_END_ADDR_MASK 0xfffffff
+#define DL8_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL8_RCH_MON */
+#define DL8_RCH_DATA_SFT 0
+#define DL8_RCH_DATA_MASK 0xffffffff
+#define DL8_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL8_LCH_MON */
+#define DL8_LCH_DATA_SFT 0
+#define DL8_LCH_DATA_MASK 0xffffffff
+#define DL8_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL8_CON0 */
+#define DL8_ON_SFT 28
+#define DL8_ON_MASK 0x1
+#define DL8_ON_MASK_SFT (0x1 << 28)
+#define DL8_ONE_HEART_SEL_SFT 22
+#define DL8_ONE_HEART_SEL_MASK 0x3
+#define DL8_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL8_MINLEN_SFT 20
+#define DL8_MINLEN_MASK 0x3
+#define DL8_MINLEN_MASK_SFT (0x3 << 20)
+#define DL8_MAXLEN_SFT 16
+#define DL8_MAXLEN_MASK 0x3
+#define DL8_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL8_SEL_DOMAIN_SFT 13
+#define DL8_SEL_DOMAIN_MASK 0x7
+#define DL8_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL8_SEL_FS_SFT 8
+#define DL8_SEL_FS_MASK 0x1f
+#define DL8_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL8_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL8_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL8_PBUF_SIZE_SFT 5
+#define DL8_PBUF_SIZE_MASK 0x3
+#define DL8_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL8_MONO_SFT 4
+#define DL8_MONO_MASK 0x1
+#define DL8_MONO_MASK_SFT (0x1 << 4)
+#define DL8_NORMAL_MODE_SFT 3
+#define DL8_NORMAL_MODE_MASK 0x1
+#define DL8_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL8_HALIGN_SFT 2
+#define DL8_HALIGN_MASK 0x1
+#define DL8_HALIGN_MASK_SFT (0x1 << 2)
+#define DL8_HD_MODE_SFT 0
+#define DL8_HD_MODE_MASK 0x3
+#define DL8_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL8_MON0 */
+#define RESERVED_01_SFT 20
+#define RESERVED_01_MASK 0xfff
+#define RESERVED_01_MASK_SFT (0xfff << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_EMPTY_SFT 18
+#define BUF_EMPTY_MASK 0x1
+#define BUF_EMPTY_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_DL_24CH_BASE_MSB */
+#define DL_24CH_BASE__ADDR_MSB_SFT 0
+#define DL_24CH_BASE__ADDR_MSB_MASK 0x1ff
+#define DL_24CH_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL_24CH_BASE */
+#define DL_24CH_BASE_ADDR_SFT 4
+#define DL_24CH_BASE_ADDR_MASK 0xfffffff
+#define DL_24CH_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL_24CH_CUR_MSB */
+#define DL_24CH_CUR_PTR_MSB_SFT 0
+#define DL_24CH_CUR_PTR_MSB_MASK 0x1ff
+#define DL_24CH_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL_24CH_CUR */
+#define DL_24CH_CUR_PTR_SFT 0
+#define DL_24CH_CUR_PTR_MASK 0xffffffff
+#define DL_24CH_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_END_MSB */
+#define DL_24CH_END_ADDR_MSB_SFT 0
+#define DL_24CH_END_ADDR_MSB_MASK 0x1ff
+#define DL_24CH_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL_24CH_END */
+#define DL_24CH_END_ADDR_SFT 4
+#define DL_24CH_END_ADDR_MASK 0xfffffff
+#define DL_24CH_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL_24CH_CON0 */
+#define DL_24CH_ON_SFT 31
+#define DL_24CH_ON_MASK 0x1
+#define DL_24CH_ON_MASK_SFT (0x1 << 31)
+#define DL_24CH_NUM_SFT 24
+#define DL_24CH_NUM_MASK 0x3f
+#define DL_24CH_NUM_MASK_SFT (0x3f << 24)
+#define DL_24CH_ONE_HEART_SEL_SFT 22
+#define DL_24CH_ONE_HEART_SEL_MASK 0x3
+#define DL_24CH_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL_24CH_MINLEN_SFT 20
+#define DL_24CH_MINLEN_MASK 0x3
+#define DL_24CH_MINLEN_MASK_SFT (0x3 << 20)
+#define DL_24CH_MAXLEN_SFT 16
+#define DL_24CH_MAXLEN_MASK 0x3
+#define DL_24CH_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL_24CH_SEL_DOMAIN_SFT 13
+#define DL_24CH_SEL_DOMAIN_MASK 0x7
+#define DL_24CH_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL_24CH_SEL_FS_SFT 8
+#define DL_24CH_SEL_FS_MASK 0x1f
+#define DL_24CH_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL_24CH_BUF_EMPTY_CLR_SFT 7
+#define DL_24CH_BUF_EMPTY_CLR_MASK 0x1
+#define DL_24CH_BUF_EMPTY_CLR_MASK_SFT (0x1 << 7)
+#define DL_24CH_PBUF_SIZE_SFT 5
+#define DL_24CH_PBUF_SIZE_MASK 0x3
+#define DL_24CH_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL_24CH_HANG_CLR_SFT 4
+#define DL_24CH_HANG_CLR_MASK 0x1
+#define DL_24CH_HANG_CLR_MASK_SFT (0x1 << 4)
+#define DL_24CH_NORMAL_MODE_SFT 3
+#define DL_24CH_NORMAL_MODE_MASK 0x1
+#define DL_24CH_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL_24CH_HALIGN_SFT 2
+#define DL_24CH_HALIGN_MASK 0x1
+#define DL_24CH_HALIGN_MASK_SFT (0x1 << 2)
+#define DL_24CH_HD_MODE_SFT 0
+#define DL_24CH_HD_MODE_MASK 0x3
+#define DL_24CH_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL23_BASE_MSB */
+#define DL23_BASE__ADDR_MSB_SFT 0
+#define DL23_BASE__ADDR_MSB_MASK 0x1ff
+#define DL23_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL23_BASE */
+#define DL23_BASE_ADDR_SFT 4
+#define DL23_BASE_ADDR_MASK 0xfffffff
+#define DL23_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL23_CUR_MSB */
+#define DL23_CUR_PTR_MSB_SFT 0
+#define DL23_CUR_PTR_MSB_MASK 0x1ff
+#define DL23_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL23_CUR */
+#define DL23_CUR_PTR_SFT 0
+#define DL23_CUR_PTR_MASK 0xffffffff
+#define DL23_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL23_END_MSB */
+#define DL23_END_ADDR_MSB_SFT 0
+#define DL23_END_ADDR_MSB_MASK 0x1ff
+#define DL23_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL23_END */
+#define DL23_END_ADDR_SFT 4
+#define DL23_END_ADDR_MASK 0xfffffff
+#define DL23_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL23_RCH_MON */
+#define DL23_RCH_DATA_SFT 0
+#define DL23_RCH_DATA_MASK 0xffffffff
+#define DL23_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL23_LCH_MON */
+#define DL23_LCH_DATA_SFT 0
+#define DL23_LCH_DATA_MASK 0xffffffff
+#define DL23_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL23_CON0 */
+#define DL23_ON_SFT 28
+#define DL23_ON_MASK 0x1
+#define DL23_ON_MASK_SFT (0x1 << 28)
+#define DL23_ONE_HEART_SEL_SFT 22
+#define DL23_ONE_HEART_SEL_MASK 0x3
+#define DL23_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL23_MINLEN_SFT 20
+#define DL23_MINLEN_MASK 0x3
+#define DL23_MINLEN_MASK_SFT (0x3 << 20)
+#define DL23_MAXLEN_SFT 16
+#define DL23_MAXLEN_MASK 0x3
+#define DL23_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL23_SEL_DOMAIN_SFT 13
+#define DL23_SEL_DOMAIN_MASK 0x7
+#define DL23_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL23_SEL_FS_SFT 8
+#define DL23_SEL_FS_MASK 0x1f
+#define DL23_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL23_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL23_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL23_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL23_PBUF_SIZE_SFT 5
+#define DL23_PBUF_SIZE_MASK 0x3
+#define DL23_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL23_MONO_SFT 4
+#define DL23_MONO_MASK 0x1
+#define DL23_MONO_MASK_SFT (0x1 << 4)
+#define DL23_NORMAL_MODE_SFT 3
+#define DL23_NORMAL_MODE_MASK 0x1
+#define DL23_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL23_HALIGN_SFT 2
+#define DL23_HALIGN_MASK 0x1
+#define DL23_HALIGN_MASK_SFT (0x1 << 2)
+#define DL23_HD_MODE_SFT 0
+#define DL23_HD_MODE_MASK 0x3
+#define DL23_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL24_BASE_MSB */
+#define DL24_BASE__ADDR_MSB_SFT 0
+#define DL24_BASE__ADDR_MSB_MASK 0x1ff
+#define DL24_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL24_BASE */
+#define DL24_BASE_ADDR_SFT 4
+#define DL24_BASE_ADDR_MASK 0xfffffff
+#define DL24_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL24_CUR_MSB */
+#define DL24_CUR_PTR_MSB_SFT 0
+#define DL24_CUR_PTR_MSB_MASK 0x1ff
+#define DL24_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL24_CUR */
+#define DL24_CUR_PTR_SFT 0
+#define DL24_CUR_PTR_MASK 0xffffffff
+#define DL24_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL24_END_MSB */
+#define DL24_END_ADDR_MSB_SFT 0
+#define DL24_END_ADDR_MSB_MASK 0x1ff
+#define DL24_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL24_END */
+#define DL24_END_ADDR_SFT 4
+#define DL24_END_ADDR_MASK 0xfffffff
+#define DL24_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL24_RCH_MON */
+#define DL24_RCH_DATA_SFT 0
+#define DL24_RCH_DATA_MASK 0xffffffff
+#define DL24_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL24_LCH_MON */
+#define DL24_LCH_DATA_SFT 0
+#define DL24_LCH_DATA_MASK 0xffffffff
+#define DL24_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL24_CON0 */
+#define DL24_ON_SFT 28
+#define DL24_ON_MASK 0x1
+#define DL24_ON_MASK_SFT (0x1 << 28)
+#define DL24_ONE_HEART_SEL_SFT 22
+#define DL24_ONE_HEART_SEL_MASK 0x3
+#define DL24_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL24_MINLEN_SFT 20
+#define DL24_MINLEN_MASK 0x3
+#define DL24_MINLEN_MASK_SFT (0x3 << 20)
+#define DL24_MAXLEN_SFT 16
+#define DL24_MAXLEN_MASK 0x3
+#define DL24_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL24_SEL_DOMAIN_SFT 13
+#define DL24_SEL_DOMAIN_MASK 0x7
+#define DL24_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL24_SEL_FS_SFT 8
+#define DL24_SEL_FS_MASK 0x1f
+#define DL24_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL24_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL24_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL24_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL24_PBUF_SIZE_SFT 5
+#define DL24_PBUF_SIZE_MASK 0x3
+#define DL24_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL24_MONO_SFT 4
+#define DL24_MONO_MASK 0x1
+#define DL24_MONO_MASK_SFT (0x1 << 4)
+#define DL24_NORMAL_MODE_SFT 3
+#define DL24_NORMAL_MODE_MASK 0x1
+#define DL24_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL24_HALIGN_SFT 2
+#define DL24_HALIGN_MASK 0x1
+#define DL24_HALIGN_MASK_SFT (0x1 << 2)
+#define DL24_HD_MODE_SFT 0
+#define DL24_HD_MODE_MASK 0x3
+#define DL24_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_DL25_BASE_MSB */
+#define DL25_BASE__ADDR_MSB_SFT 0
+#define DL25_BASE__ADDR_MSB_MASK 0x1ff
+#define DL25_BASE__ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL25_BASE */
+#define DL25_BASE_ADDR_SFT 4
+#define DL25_BASE_ADDR_MASK 0xfffffff
+#define DL25_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL25_CUR_MSB */
+#define DL25_CUR_PTR_MSB_SFT 0
+#define DL25_CUR_PTR_MSB_MASK 0x1ff
+#define DL25_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL25_CUR */
+#define DL25_CUR_PTR_SFT 0
+#define DL25_CUR_PTR_MASK 0xffffffff
+#define DL25_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL25_END_MSB */
+#define DL25_END_ADDR_MSB_SFT 0
+#define DL25_END_ADDR_MSB_MASK 0x1ff
+#define DL25_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_DL25_END */
+#define DL25_END_ADDR_SFT 4
+#define DL25_END_ADDR_MASK 0xfffffff
+#define DL25_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_DL25_RCH_MON */
+#define DL25_RCH_DATA_SFT 0
+#define DL25_RCH_DATA_MASK 0xffffffff
+#define DL25_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL25_LCH_MON */
+#define DL25_LCH_DATA_SFT 0
+#define DL25_LCH_DATA_MASK 0xffffffff
+#define DL25_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL25_CON0 */
+#define DL25_ON_SFT 28
+#define DL25_ON_MASK 0x1
+#define DL25_ON_MASK_SFT (0x1 << 28)
+#define DL25_ONE_HEART_SEL_SFT 22
+#define DL25_ONE_HEART_SEL_MASK 0x3
+#define DL25_ONE_HEART_SEL_MASK_SFT (0x3 << 22)
+#define DL25_MINLEN_SFT 20
+#define DL25_MINLEN_MASK 0x3
+#define DL25_MINLEN_MASK_SFT (0x3 << 20)
+#define DL25_MAXLEN_SFT 16
+#define DL25_MAXLEN_MASK 0x3
+#define DL25_MAXLEN_MASK_SFT (0x3 << 16)
+#define DL25_SEL_DOMAIN_SFT 13
+#define DL25_SEL_DOMAIN_MASK 0x7
+#define DL25_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define DL25_SEL_FS_SFT 8
+#define DL25_SEL_FS_MASK 0x1f
+#define DL25_SEL_FS_MASK_SFT (0x1f << 8)
+#define DL25_SW_CLEAR_BUF_EMPTY_SFT 7
+#define DL25_SW_CLEAR_BUF_EMPTY_MASK 0x1
+#define DL25_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 7)
+#define DL25_PBUF_SIZE_SFT 5
+#define DL25_PBUF_SIZE_MASK 0x3
+#define DL25_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL25_MONO_SFT 4
+#define DL25_MONO_MASK 0x1
+#define DL25_MONO_MASK_SFT (0x1 << 4)
+#define DL25_NORMAL_MODE_SFT 3
+#define DL25_NORMAL_MODE_MASK 0x1
+#define DL25_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define DL25_HALIGN_SFT 2
+#define DL25_HALIGN_MASK 0x1
+#define DL25_HALIGN_MASK_SFT (0x1 << 2)
+#define DL25_HD_MODE_SFT 0
+#define DL25_HD_MODE_MASK 0x3
+#define DL25_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL0_BASE_MSB */
+#define VUL0_BASE_ADDR_MSB_SFT 0
+#define VUL0_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL0_BASE */
+#define VUL0_BASE_ADDR_SFT 4
+#define VUL0_BASE_ADDR_MASK 0xfffffff
+#define VUL0_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL0_CUR_MSB */
+#define VUL0_CUR_PTR_MSB_SFT 0
+#define VUL0_CUR_PTR_MSB_MASK 0x1ff
+#define VUL0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL0_CUR */
+#define VUL0_CUR_PTR_SFT 0
+#define VUL0_CUR_PTR_MASK 0xffffffff
+#define VUL0_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL0_END_MSB */
+#define VUL0_END_ADDR_MSB_SFT 0
+#define VUL0_END_ADDR_MSB_MASK 0x1ff
+#define VUL0_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL0_END */
+#define VUL0_END_ADDR_SFT 4
+#define VUL0_END_ADDR_MASK 0xfffffff
+#define VUL0_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL0_RCH_MON */
+#define VUL0_RCH_DATA_SFT 0
+#define VUL0_RCH_DATA_MASK 0xffffffff
+#define VUL0_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL0_LCH_MON */
+#define VUL0_LCH_DATA_SFT 0
+#define VUL0_LCH_DATA_MASK 0xffffffff
+#define VUL0_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL0_CON0 */
+#define VUL0_ON_SFT 28
+#define VUL0_ON_MASK 0x1
+#define VUL0_ON_MASK_SFT (0x1 << 28)
+#define VUL0_MINLEN_SFT 20
+#define VUL0_MINLEN_MASK 0x3
+#define VUL0_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL0_MAXLEN_SFT 16
+#define VUL0_MAXLEN_MASK 0x3
+#define VUL0_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL0_SEL_DOMAIN_SFT 13
+#define VUL0_SEL_DOMAIN_MASK 0x7
+#define VUL0_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL0_SEL_FS_SFT 8
+#define VUL0_SEL_FS_MASK 0x1f
+#define VUL0_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL0_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL0_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL0_WR_SIGN_SFT 6
+#define VUL0_WR_SIGN_MASK 0x1
+#define VUL0_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL0_R_MONO_SFT 5
+#define VUL0_R_MONO_MASK 0x1
+#define VUL0_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL0_MONO_SFT 4
+#define VUL0_MONO_MASK 0x1
+#define VUL0_MONO_MASK_SFT (0x1 << 4)
+#define VUL0_NORMAL_MODE_SFT 3
+#define VUL0_NORMAL_MODE_MASK 0x1
+#define VUL0_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL0_HALIGN_SFT 2
+#define VUL0_HALIGN_MASK 0x1
+#define VUL0_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL0_HD_MODE_SFT 0
+#define VUL0_HD_MODE_MASK 0x3
+#define VUL0_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL1_BASE_MSB */
+#define VUL1_BASE_ADDR_MSB_SFT 0
+#define VUL1_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL1_BASE */
+#define VUL1_BASE_ADDR_SFT 4
+#define VUL1_BASE_ADDR_MASK 0xfffffff
+#define VUL1_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL1_CUR_MSB */
+#define VUL1_CUR_PTR_MSB_SFT 0
+#define VUL1_CUR_PTR_MSB_MASK 0x1ff
+#define VUL1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL1_CUR */
+#define VUL1_CUR_PTR_SFT 0
+#define VUL1_CUR_PTR_MASK 0xffffffff
+#define VUL1_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL1_END_MSB */
+#define VUL1_END_ADDR_MSB_SFT 0
+#define VUL1_END_ADDR_MSB_MASK 0x1ff
+#define VUL1_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL1_END */
+#define VUL1_END_ADDR_SFT 4
+#define VUL1_END_ADDR_MASK 0xfffffff
+#define VUL1_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL1_RCH_MON */
+#define VUL1_RCH_DATA_SFT 0
+#define VUL1_RCH_DATA_MASK 0xffffffff
+#define VUL1_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL1_LCH_MON */
+#define VUL1_LCH_DATA_SFT 0
+#define VUL1_LCH_DATA_MASK 0xffffffff
+#define VUL1_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL1_CON0 */
+#define VUL1_ON_SFT 28
+#define VUL1_ON_MASK 0x1
+#define VUL1_ON_MASK_SFT (0x1 << 28)
+#define VUL1_MINLEN_SFT 20
+#define VUL1_MINLEN_MASK 0x3
+#define VUL1_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL1_MAXLEN_SFT 16
+#define VUL1_MAXLEN_MASK 0x3
+#define VUL1_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL1_SEL_DOMAIN_SFT 13
+#define VUL1_SEL_DOMAIN_MASK 0x7
+#define VUL1_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL1_SEL_FS_SFT 8
+#define VUL1_SEL_FS_MASK 0x1f
+#define VUL1_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL1_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL1_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL1_WR_SIGN_SFT 6
+#define VUL1_WR_SIGN_MASK 0x1
+#define VUL1_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL1_R_MONO_SFT 5
+#define VUL1_R_MONO_MASK 0x1
+#define VUL1_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL1_MONO_SFT 4
+#define VUL1_MONO_MASK 0x1
+#define VUL1_MONO_MASK_SFT (0x1 << 4)
+#define VUL1_NORMAL_MODE_SFT 3
+#define VUL1_NORMAL_MODE_MASK 0x1
+#define VUL1_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL1_HALIGN_SFT 2
+#define VUL1_HALIGN_MASK 0x1
+#define VUL1_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL1_HD_MODE_SFT 0
+#define VUL1_HD_MODE_MASK 0x3
+#define VUL1_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL1_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL2_BASE_MSB */
+#define VUL2_BASE_ADDR_MSB_SFT 0
+#define VUL2_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL2_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL2_BASE */
+#define VUL2_BASE_ADDR_SFT 4
+#define VUL2_BASE_ADDR_MASK 0xfffffff
+#define VUL2_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL2_CUR_MSB */
+#define VUL2_CUR_PTR_MSB_SFT 0
+#define VUL2_CUR_PTR_MSB_MASK 0x1ff
+#define VUL2_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL2_CUR */
+#define VUL2_CUR_PTR_SFT 0
+#define VUL2_CUR_PTR_MASK 0xffffffff
+#define VUL2_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL2_END_MSB */
+#define VUL2_END_ADDR_MSB_SFT 0
+#define VUL2_END_ADDR_MSB_MASK 0x1ff
+#define VUL2_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL2_END */
+#define VUL2_END_ADDR_SFT 4
+#define VUL2_END_ADDR_MASK 0xfffffff
+#define VUL2_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL2_RCH_MON */
+#define VUL2_RCH_DATA_SFT 0
+#define VUL2_RCH_DATA_MASK 0xffffffff
+#define VUL2_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL2_LCH_MON */
+#define VUL2_LCH_DATA_SFT 0
+#define VUL2_LCH_DATA_MASK 0xffffffff
+#define VUL2_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL2_CON0 */
+#define VUL2_ON_SFT 28
+#define VUL2_ON_MASK 0x1
+#define VUL2_ON_MASK_SFT (0x1 << 28)
+#define VUL2_MINLEN_SFT 20
+#define VUL2_MINLEN_MASK 0x3
+#define VUL2_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL2_MAXLEN_SFT 16
+#define VUL2_MAXLEN_MASK 0x3
+#define VUL2_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL2_SEL_DOMAIN_SFT 13
+#define VUL2_SEL_DOMAIN_MASK 0x7
+#define VUL2_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL2_SEL_FS_SFT 8
+#define VUL2_SEL_FS_MASK 0x1f
+#define VUL2_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL2_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL2_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL2_WR_SIGN_SFT 6
+#define VUL2_WR_SIGN_MASK 0x1
+#define VUL2_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL2_R_MONO_SFT 5
+#define VUL2_R_MONO_MASK 0x1
+#define VUL2_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL2_MONO_SFT 4
+#define VUL2_MONO_MASK 0x1
+#define VUL2_MONO_MASK_SFT (0x1 << 4)
+#define VUL2_NORMAL_MODE_SFT 3
+#define VUL2_NORMAL_MODE_MASK 0x1
+#define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL2_HALIGN_SFT 2
+#define VUL2_HALIGN_MASK 0x1
+#define VUL2_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL2_HD_MODE_SFT 0
+#define VUL2_HD_MODE_MASK 0x3
+#define VUL2_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL2_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL3_BASE_MSB */
+#define VUL3_BASE_ADDR_MSB_SFT 0
+#define VUL3_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL3_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL3_BASE */
+#define VUL3_BASE_ADDR_SFT 4
+#define VUL3_BASE_ADDR_MASK 0xfffffff
+#define VUL3_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL3_CUR_MSB */
+#define VUL3_CUR_PTR_MSB_SFT 0
+#define VUL3_CUR_PTR_MSB_MASK 0x1ff
+#define VUL3_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL3_CUR */
+#define VUL3_CUR_PTR_SFT 0
+#define VUL3_CUR_PTR_MASK 0xffffffff
+#define VUL3_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL3_END_MSB */
+#define VUL3_END_ADDR_MSB_SFT 0
+#define VUL3_END_ADDR_MSB_MASK 0x1ff
+#define VUL3_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL3_END */
+#define VUL3_END_ADDR_SFT 4
+#define VUL3_END_ADDR_MASK 0xfffffff
+#define VUL3_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL3_RCH_MON */
+#define VUL3_RCH_DATA_SFT 0
+#define VUL3_RCH_DATA_MASK 0xffffffff
+#define VUL3_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL3_LCH_MON */
+#define VUL3_LCH_DATA_SFT 0
+#define VUL3_LCH_DATA_MASK 0xffffffff
+#define VUL3_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL3_CON0 */
+#define VUL3_ON_SFT 28
+#define VUL3_ON_MASK 0x1
+#define VUL3_ON_MASK_SFT (0x1 << 28)
+#define VUL3_MINLEN_SFT 20
+#define VUL3_MINLEN_MASK 0x3
+#define VUL3_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL3_MAXLEN_SFT 16
+#define VUL3_MAXLEN_MASK 0x3
+#define VUL3_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL3_SEL_DOMAIN_SFT 13
+#define VUL3_SEL_DOMAIN_MASK 0x7
+#define VUL3_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL3_SEL_FS_SFT 8
+#define VUL3_SEL_FS_MASK 0x1f
+#define VUL3_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL3_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL3_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL3_WR_SIGN_SFT 6
+#define VUL3_WR_SIGN_MASK 0x1
+#define VUL3_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL3_R_MONO_SFT 5
+#define VUL3_R_MONO_MASK 0x1
+#define VUL3_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL3_MONO_SFT 4
+#define VUL3_MONO_MASK 0x1
+#define VUL3_MONO_MASK_SFT (0x1 << 4)
+#define VUL3_NORMAL_MODE_SFT 3
+#define VUL3_NORMAL_MODE_MASK 0x1
+#define VUL3_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL3_HALIGN_SFT 2
+#define VUL3_HALIGN_MASK 0x1
+#define VUL3_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL3_HD_MODE_SFT 0
+#define VUL3_HD_MODE_MASK 0x3
+#define VUL3_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL3_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL4_BASE_MSB */
+#define VUL4_BASE_ADDR_MSB_SFT 0
+#define VUL4_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL4_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL4_BASE */
+#define VUL4_BASE_ADDR_SFT 4
+#define VUL4_BASE_ADDR_MASK 0xfffffff
+#define VUL4_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL4_CUR_MSB */
+#define VUL4_CUR_PTR_MSB_SFT 0
+#define VUL4_CUR_PTR_MSB_MASK 0x1ff
+#define VUL4_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL4_CUR */
+#define VUL4_CUR_PTR_SFT 0
+#define VUL4_CUR_PTR_MASK 0xffffffff
+#define VUL4_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL4_END_MSB */
+#define VUL4_END_ADDR_MSB_SFT 0
+#define VUL4_END_ADDR_MSB_MASK 0x1ff
+#define VUL4_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL4_END */
+#define VUL4_END_ADDR_SFT 4
+#define VUL4_END_ADDR_MASK 0xfffffff
+#define VUL4_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL4_RCH_MON */
+#define VUL4_RCH_DATA_SFT 0
+#define VUL4_RCH_DATA_MASK 0xffffffff
+#define VUL4_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL4_LCH_MON */
+#define VUL4_LCH_DATA_SFT 0
+#define VUL4_LCH_DATA_MASK 0xffffffff
+#define VUL4_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL4_CON0 */
+#define VUL4_ON_SFT 28
+#define VUL4_ON_MASK 0x1
+#define VUL4_ON_MASK_SFT (0x1 << 28)
+#define VUL4_MINLEN_SFT 20
+#define VUL4_MINLEN_MASK 0x3
+#define VUL4_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL4_MAXLEN_SFT 16
+#define VUL4_MAXLEN_MASK 0x3
+#define VUL4_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL4_SEL_DOMAIN_SFT 13
+#define VUL4_SEL_DOMAIN_MASK 0x7
+#define VUL4_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL4_SEL_FS_SFT 8
+#define VUL4_SEL_FS_MASK 0x1f
+#define VUL4_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL4_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL4_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL4_WR_SIGN_SFT 6
+#define VUL4_WR_SIGN_MASK 0x1
+#define VUL4_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL4_R_MONO_SFT 5
+#define VUL4_R_MONO_MASK 0x1
+#define VUL4_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL4_MONO_SFT 4
+#define VUL4_MONO_MASK 0x1
+#define VUL4_MONO_MASK_SFT (0x1 << 4)
+#define VUL4_NORMAL_MODE_SFT 3
+#define VUL4_NORMAL_MODE_MASK 0x1
+#define VUL4_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL4_HALIGN_SFT 2
+#define VUL4_HALIGN_MASK 0x1
+#define VUL4_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL4_HD_MODE_SFT 0
+#define VUL4_HD_MODE_MASK 0x3
+#define VUL4_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL4_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL5_BASE_MSB */
+#define VUL5_BASE_ADDR_MSB_SFT 0
+#define VUL5_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL5_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL5_BASE */
+#define VUL5_BASE_ADDR_SFT 4
+#define VUL5_BASE_ADDR_MASK 0xfffffff
+#define VUL5_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL5_CUR_MSB */
+#define VUL5_CUR_PTR_MSB_SFT 0
+#define VUL5_CUR_PTR_MSB_MASK 0x1ff
+#define VUL5_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL5_CUR */
+#define VUL5_CUR_PTR_SFT 0
+#define VUL5_CUR_PTR_MASK 0xffffffff
+#define VUL5_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL5_END_MSB */
+#define VUL5_END_ADDR_MSB_SFT 0
+#define VUL5_END_ADDR_MSB_MASK 0x1ff
+#define VUL5_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL5_END */
+#define VUL5_END_ADDR_SFT 4
+#define VUL5_END_ADDR_MASK 0xfffffff
+#define VUL5_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL5_RCH_MON */
+#define VUL5_RCH_DATA_SFT 0
+#define VUL5_RCH_DATA_MASK 0xffffffff
+#define VUL5_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL5_LCH_MON */
+#define VUL5_LCH_DATA_SFT 0
+#define VUL5_LCH_DATA_MASK 0xffffffff
+#define VUL5_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL5_CON0 */
+#define VUL5_ON_SFT 28
+#define VUL5_ON_MASK 0x1
+#define VUL5_ON_MASK_SFT (0x1 << 28)
+#define VUL5_MINLEN_SFT 20
+#define VUL5_MINLEN_MASK 0x3
+#define VUL5_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL5_MAXLEN_SFT 16
+#define VUL5_MAXLEN_MASK 0x3
+#define VUL5_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL5_SEL_DOMAIN_SFT 13
+#define VUL5_SEL_DOMAIN_MASK 0x7
+#define VUL5_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL5_SEL_FS_SFT 8
+#define VUL5_SEL_FS_MASK 0x1f
+#define VUL5_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL5_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL5_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL5_WR_SIGN_SFT 6
+#define VUL5_WR_SIGN_MASK 0x1
+#define VUL5_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL5_R_MONO_SFT 5
+#define VUL5_R_MONO_MASK 0x1
+#define VUL5_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL5_MONO_SFT 4
+#define VUL5_MONO_MASK 0x1
+#define VUL5_MONO_MASK_SFT (0x1 << 4)
+#define VUL5_NORMAL_MODE_SFT 3
+#define VUL5_NORMAL_MODE_MASK 0x1
+#define VUL5_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL5_HALIGN_SFT 2
+#define VUL5_HALIGN_MASK 0x1
+#define VUL5_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL5_HD_MODE_SFT 0
+#define VUL5_HD_MODE_MASK 0x3
+#define VUL5_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL5_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL6_BASE_MSB */
+#define VUL6_BASE_ADDR_MSB_SFT 0
+#define VUL6_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL6_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL6_BASE */
+#define VUL6_BASE_ADDR_SFT 4
+#define VUL6_BASE_ADDR_MASK 0xfffffff
+#define VUL6_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL6_CUR_MSB */
+#define VUL6_CUR_PTR_MSB_SFT 0
+#define VUL6_CUR_PTR_MSB_MASK 0x1ff
+#define VUL6_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL6_CUR */
+#define VUL6_CUR_PTR_SFT 0
+#define VUL6_CUR_PTR_MASK 0xffffffff
+#define VUL6_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL6_END_MSB */
+#define VUL6_END_ADDR_MSB_SFT 0
+#define VUL6_END_ADDR_MSB_MASK 0x1ff
+#define VUL6_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL6_END */
+#define VUL6_END_ADDR_SFT 4
+#define VUL6_END_ADDR_MASK 0xfffffff
+#define VUL6_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL6_RCH_MON */
+#define VUL6_RCH_DATA_SFT 0
+#define VUL6_RCH_DATA_MASK 0xffffffff
+#define VUL6_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL6_LCH_MON */
+#define VUL6_LCH_DATA_SFT 0
+#define VUL6_LCH_DATA_MASK 0xffffffff
+#define VUL6_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL6_CON0 */
+#define VUL6_ON_SFT 28
+#define VUL6_ON_MASK 0x1
+#define VUL6_ON_MASK_SFT (0x1 << 28)
+#define VUL6_MINLEN_SFT 20
+#define VUL6_MINLEN_MASK 0x3
+#define VUL6_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL6_MAXLEN_SFT 16
+#define VUL6_MAXLEN_MASK 0x3
+#define VUL6_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL6_SEL_DOMAIN_SFT 13
+#define VUL6_SEL_DOMAIN_MASK 0x7
+#define VUL6_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL6_SEL_FS_SFT 8
+#define VUL6_SEL_FS_MASK 0x1f
+#define VUL6_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL6_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL6_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL6_WR_SIGN_SFT 6
+#define VUL6_WR_SIGN_MASK 0x1
+#define VUL6_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL6_R_MONO_SFT 5
+#define VUL6_R_MONO_MASK 0x1
+#define VUL6_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL6_MONO_SFT 4
+#define VUL6_MONO_MASK 0x1
+#define VUL6_MONO_MASK_SFT (0x1 << 4)
+#define VUL6_NORMAL_MODE_SFT 3
+#define VUL6_NORMAL_MODE_MASK 0x1
+#define VUL6_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL6_HALIGN_SFT 2
+#define VUL6_HALIGN_MASK 0x1
+#define VUL6_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL6_HD_MODE_SFT 0
+#define VUL6_HD_MODE_MASK 0x3
+#define VUL6_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL6_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL7_BASE_MSB */
+#define VUL7_BASE_ADDR_MSB_SFT 0
+#define VUL7_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL7_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL7_BASE */
+#define VUL7_BASE_ADDR_SFT 4
+#define VUL7_BASE_ADDR_MASK 0xfffffff
+#define VUL7_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL7_CUR_MSB */
+#define VUL7_CUR_PTR_MSB_SFT 0
+#define VUL7_CUR_PTR_MSB_MASK 0x1ff
+#define VUL7_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL7_CUR */
+#define VUL7_CUR_PTR_SFT 0
+#define VUL7_CUR_PTR_MASK 0xffffffff
+#define VUL7_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL7_END_MSB */
+#define VUL7_END_ADDR_MSB_SFT 0
+#define VUL7_END_ADDR_MSB_MASK 0x1ff
+#define VUL7_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL7_END */
+#define VUL7_END_ADDR_SFT 4
+#define VUL7_END_ADDR_MASK 0xfffffff
+#define VUL7_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL7_RCH_MON */
+#define VUL7_RCH_DATA_SFT 0
+#define VUL7_RCH_DATA_MASK 0xffffffff
+#define VUL7_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL7_LCH_MON */
+#define VUL7_LCH_DATA_SFT 0
+#define VUL7_LCH_DATA_MASK 0xffffffff
+#define VUL7_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL7_CON0 */
+#define VUL7_ON_SFT 28
+#define VUL7_ON_MASK 0x1
+#define VUL7_ON_MASK_SFT (0x1 << 28)
+#define VUL7_MINLEN_SFT 20
+#define VUL7_MINLEN_MASK 0x3
+#define VUL7_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL7_MAXLEN_SFT 16
+#define VUL7_MAXLEN_MASK 0x3
+#define VUL7_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL7_SEL_DOMAIN_SFT 13
+#define VUL7_SEL_DOMAIN_MASK 0x7
+#define VUL7_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL7_SEL_FS_SFT 8
+#define VUL7_SEL_FS_MASK 0x1f
+#define VUL7_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL7_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL7_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL7_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL7_WR_SIGN_SFT 6
+#define VUL7_WR_SIGN_MASK 0x1
+#define VUL7_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL7_R_MONO_SFT 5
+#define VUL7_R_MONO_MASK 0x1
+#define VUL7_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL7_MONO_SFT 4
+#define VUL7_MONO_MASK 0x1
+#define VUL7_MONO_MASK_SFT (0x1 << 4)
+#define VUL7_NORMAL_MODE_SFT 3
+#define VUL7_NORMAL_MODE_MASK 0x1
+#define VUL7_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL7_HALIGN_SFT 2
+#define VUL7_HALIGN_MASK 0x1
+#define VUL7_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL7_HD_MODE_SFT 0
+#define VUL7_HD_MODE_MASK 0x3
+#define VUL7_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL7_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL8_BASE_MSB */
+#define VUL8_BASE_ADDR_MSB_SFT 0
+#define VUL8_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL8_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL8_BASE */
+#define VUL8_BASE_ADDR_SFT 4
+#define VUL8_BASE_ADDR_MASK 0xfffffff
+#define VUL8_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL8_CUR_MSB */
+#define VUL8_CUR_PTR_MSB_SFT 0
+#define VUL8_CUR_PTR_MSB_MASK 0x1ff
+#define VUL8_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL8_CUR */
+#define VUL8_CUR_PTR_SFT 0
+#define VUL8_CUR_PTR_MASK 0xffffffff
+#define VUL8_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL8_END_MSB */
+#define VUL8_END_ADDR_MSB_SFT 0
+#define VUL8_END_ADDR_MSB_MASK 0x1ff
+#define VUL8_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL8_END */
+#define VUL8_END_ADDR_SFT 4
+#define VUL8_END_ADDR_MASK 0xfffffff
+#define VUL8_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL8_RCH_MON */
+#define VUL8_RCH_DATA_SFT 0
+#define VUL8_RCH_DATA_MASK 0xffffffff
+#define VUL8_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL8_LCH_MON */
+#define VUL8_LCH_DATA_SFT 0
+#define VUL8_LCH_DATA_MASK 0xffffffff
+#define VUL8_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL8_CON0 */
+#define VUL8_ON_SFT 28
+#define VUL8_ON_MASK 0x1
+#define VUL8_ON_MASK_SFT (0x1 << 28)
+#define VUL8_MINLEN_SFT 20
+#define VUL8_MINLEN_MASK 0x3
+#define VUL8_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL8_MAXLEN_SFT 16
+#define VUL8_MAXLEN_MASK 0x3
+#define VUL8_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL8_SEL_DOMAIN_SFT 13
+#define VUL8_SEL_DOMAIN_MASK 0x7
+#define VUL8_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL8_SEL_FS_SFT 8
+#define VUL8_SEL_FS_MASK 0x1f
+#define VUL8_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL8_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL8_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL8_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL8_WR_SIGN_SFT 6
+#define VUL8_WR_SIGN_MASK 0x1
+#define VUL8_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL8_R_MONO_SFT 5
+#define VUL8_R_MONO_MASK 0x1
+#define VUL8_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL8_MONO_SFT 4
+#define VUL8_MONO_MASK 0x1
+#define VUL8_MONO_MASK_SFT (0x1 << 4)
+#define VUL8_NORMAL_MODE_SFT 3
+#define VUL8_NORMAL_MODE_MASK 0x1
+#define VUL8_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL8_HALIGN_SFT 2
+#define VUL8_HALIGN_MASK 0x1
+#define VUL8_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL8_HD_MODE_SFT 0
+#define VUL8_HD_MODE_MASK 0x3
+#define VUL8_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL8_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL9_BASE_MSB */
+#define VUL9_BASE_ADDR_MSB_SFT 0
+#define VUL9_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL9_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL9_BASE */
+#define VUL9_BASE_ADDR_SFT 4
+#define VUL9_BASE_ADDR_MASK 0xfffffff
+#define VUL9_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL9_CUR_MSB */
+#define VUL9_CUR_PTR_MSB_SFT 0
+#define VUL9_CUR_PTR_MSB_MASK 0x1ff
+#define VUL9_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL9_CUR */
+#define VUL9_CUR_PTR_SFT 0
+#define VUL9_CUR_PTR_MASK 0xffffffff
+#define VUL9_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL9_END_MSB */
+#define VUL9_END_ADDR_MSB_SFT 0
+#define VUL9_END_ADDR_MSB_MASK 0x1ff
+#define VUL9_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL9_END */
+#define VUL9_END_ADDR_SFT 4
+#define VUL9_END_ADDR_MASK 0xfffffff
+#define VUL9_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL9_RCH_MON */
+#define VUL9_RCH_DATA_SFT 0
+#define VUL9_RCH_DATA_MASK 0xffffffff
+#define VUL9_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL9_LCH_MON */
+#define VUL9_LCH_DATA_SFT 0
+#define VUL9_LCH_DATA_MASK 0xffffffff
+#define VUL9_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL9_CON0 */
+#define VUL9_ON_SFT 28
+#define VUL9_ON_MASK 0x1
+#define VUL9_ON_MASK_SFT (0x1 << 28)
+#define VUL9_MINLEN_SFT 20
+#define VUL9_MINLEN_MASK 0x3
+#define VUL9_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL9_MAXLEN_SFT 16
+#define VUL9_MAXLEN_MASK 0x3
+#define VUL9_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL9_SEL_DOMAIN_SFT 13
+#define VUL9_SEL_DOMAIN_MASK 0x7
+#define VUL9_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL9_SEL_FS_SFT 8
+#define VUL9_SEL_FS_MASK 0x1f
+#define VUL9_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL9_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL9_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL9_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL9_WR_SIGN_SFT 6
+#define VUL9_WR_SIGN_MASK 0x1
+#define VUL9_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL9_R_MONO_SFT 5
+#define VUL9_R_MONO_MASK 0x1
+#define VUL9_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL9_MONO_SFT 4
+#define VUL9_MONO_MASK 0x1
+#define VUL9_MONO_MASK_SFT (0x1 << 4)
+#define VUL9_NORMAL_MODE_SFT 3
+#define VUL9_NORMAL_MODE_MASK 0x1
+#define VUL9_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL9_HALIGN_SFT 2
+#define VUL9_HALIGN_MASK 0x1
+#define VUL9_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL9_HD_MODE_SFT 0
+#define VUL9_HD_MODE_MASK 0x3
+#define VUL9_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL9_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL10_BASE_MSB */
+#define VUL10_BASE_ADDR_MSB_SFT 0
+#define VUL10_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL10_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL10_BASE */
+#define VUL10_BASE_ADDR_SFT 4
+#define VUL10_BASE_ADDR_MASK 0xfffffff
+#define VUL10_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL10_CUR_MSB */
+#define VUL10_CUR_PTR_MSB_SFT 0
+#define VUL10_CUR_PTR_MSB_MASK 0x1ff
+#define VUL10_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL10_CUR */
+#define VUL10_CUR_PTR_SFT 0
+#define VUL10_CUR_PTR_MASK 0xffffffff
+#define VUL10_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL10_END_MSB */
+#define VUL10_END_ADDR_MSB_SFT 0
+#define VUL10_END_ADDR_MSB_MASK 0x1ff
+#define VUL10_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL10_END */
+#define VUL10_END_ADDR_SFT 4
+#define VUL10_END_ADDR_MASK 0xfffffff
+#define VUL10_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL10_RCH_MON */
+#define VUL10_RCH_DATA_SFT 0
+#define VUL10_RCH_DATA_MASK 0xffffffff
+#define VUL10_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL10_LCH_MON */
+#define VUL10_LCH_DATA_SFT 0
+#define VUL10_LCH_DATA_MASK 0xffffffff
+#define VUL10_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL10_CON0 */
+#define VUL10_ON_SFT 28
+#define VUL10_ON_MASK 0x1
+#define VUL10_ON_MASK_SFT (0x1 << 28)
+#define VUL10_MINLEN_SFT 20
+#define VUL10_MINLEN_MASK 0x3
+#define VUL10_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL10_MAXLEN_SFT 16
+#define VUL10_MAXLEN_MASK 0x3
+#define VUL10_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL10_SEL_DOMAIN_SFT 13
+#define VUL10_SEL_DOMAIN_MASK 0x7
+#define VUL10_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL10_SEL_FS_SFT 8
+#define VUL10_SEL_FS_MASK 0x1f
+#define VUL10_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL10_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL10_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL10_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL10_WR_SIGN_SFT 6
+#define VUL10_WR_SIGN_MASK 0x1
+#define VUL10_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL10_R_MONO_SFT 5
+#define VUL10_R_MONO_MASK 0x1
+#define VUL10_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL10_MONO_SFT 4
+#define VUL10_MONO_MASK 0x1
+#define VUL10_MONO_MASK_SFT (0x1 << 4)
+#define VUL10_NORMAL_MODE_SFT 3
+#define VUL10_NORMAL_MODE_MASK 0x1
+#define VUL10_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL10_HALIGN_SFT 2
+#define VUL10_HALIGN_MASK 0x1
+#define VUL10_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL10_HD_MODE_SFT 0
+#define VUL10_HD_MODE_MASK 0x3
+#define VUL10_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL10_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL24_BASE_MSB */
+#define VUL24_BASE_ADDR_MSB_SFT 0
+#define VUL24_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL24_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL24_BASE */
+#define VUL24_BASE_ADDR_SFT 4
+#define VUL24_BASE_ADDR_MASK 0xfffffff
+#define VUL24_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL24_CUR_MSB */
+#define VUL24_CUR_PTR_MSB_SFT 0
+#define VUL24_CUR_PTR_MSB_MASK 0x1ff
+#define VUL24_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL24_CUR */
+#define VUL24_CUR_PTR_SFT 0
+#define VUL24_CUR_PTR_MASK 0xffffffff
+#define VUL24_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL24_END_MSB */
+#define VUL24_END_ADDR_MSB_SFT 0
+#define VUL24_END_ADDR_MSB_MASK 0x1ff
+#define VUL24_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL24_END */
+#define VUL24_END_ADDR_SFT 4
+#define VUL24_END_ADDR_MASK 0xfffffff
+#define VUL24_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL24_CON0 */
+#define OUT_ON_USE_VUL24_SFT 29
+#define OUT_ON_USE_VUL24_MASK 0x1
+#define OUT_ON_USE_VUL24_MASK_SFT (0x1 << 29)
+#define VUL24_ON_SFT 28
+#define VUL24_ON_MASK 0x1
+#define VUL24_ON_MASK_SFT (0x1 << 28)
+#define VUL24_MINLEN_SFT 20
+#define VUL24_MINLEN_MASK 0x3
+#define VUL24_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL24_MAXLEN_SFT 16
+#define VUL24_MAXLEN_MASK 0x3
+#define VUL24_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL24_SEL_DOMAIN_SFT 13
+#define VUL24_SEL_DOMAIN_MASK 0x7
+#define VUL24_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL24_SEL_FS_SFT 8
+#define VUL24_SEL_FS_MASK 0x1f
+#define VUL24_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL24_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL24_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL24_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL24_WR_SIGN_SFT 6
+#define VUL24_WR_SIGN_MASK 0x1
+#define VUL24_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL24_R_MONO_SFT 5
+#define VUL24_R_MONO_MASK 0x1
+#define VUL24_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL24_MONO_SFT 4
+#define VUL24_MONO_MASK 0x1
+#define VUL24_MONO_MASK_SFT (0x1 << 4)
+#define VUL24_NORMAL_MODE_SFT 3
+#define VUL24_NORMAL_MODE_MASK 0x1
+#define VUL24_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL24_HALIGN_SFT 2
+#define VUL24_HALIGN_MASK 0x1
+#define VUL24_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL24_HD_MODE_SFT 0
+#define VUL24_HD_MODE_MASK 0x3
+#define VUL24_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL24_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL25_BASE_MSB */
+#define VUL25_BASE_ADDR_MSB_SFT 0
+#define VUL25_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL25_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL25_BASE */
+#define VUL25_BASE_ADDR_SFT 4
+#define VUL25_BASE_ADDR_MASK 0xfffffff
+#define VUL25_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL25_CUR_MSB */
+#define VUL25_CUR_PTR_MSB_SFT 0
+#define VUL25_CUR_PTR_MSB_MASK 0x1ff
+#define VUL25_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL25_CUR */
+#define VUL25_CUR_PTR_SFT 0
+#define VUL25_CUR_PTR_MASK 0xffffffff
+#define VUL25_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL25_END_MSB */
+#define VUL25_END_ADDR_MSB_SFT 0
+#define VUL25_END_ADDR_MSB_MASK 0x1ff
+#define VUL25_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL25_END */
+#define VUL25_END_ADDR_SFT 4
+#define VUL25_END_ADDR_MASK 0xfffffff
+#define VUL25_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL25_CON0 */
+#define OUT_ON_USE_VUL25_SFT 29
+#define OUT_ON_USE_VUL25_MASK 0x1
+#define OUT_ON_USE_VUL25_MASK_SFT (0x1 << 29)
+#define VUL25_ON_SFT 28
+#define VUL25_ON_MASK 0x1
+#define VUL25_ON_MASK_SFT (0x1 << 28)
+#define VUL25_MINLEN_SFT 20
+#define VUL25_MINLEN_MASK 0x3
+#define VUL25_MINLEN_MASK_SFT (0x3 << 20)
+#define VUL25_MAXLEN_SFT 16
+#define VUL25_MAXLEN_MASK 0x3
+#define VUL25_MAXLEN_MASK_SFT (0x3 << 16)
+#define VUL25_SEL_DOMAIN_SFT 13
+#define VUL25_SEL_DOMAIN_MASK 0x7
+#define VUL25_SEL_DOMAIN_MASK_SFT (0x7 << 13)
+#define VUL25_SEL_FS_SFT 8
+#define VUL25_SEL_FS_MASK 0x1f
+#define VUL25_SEL_FS_MASK_SFT (0x1f << 8)
+#define VUL25_SW_CLEAR_BUF_FULL_SFT 7
+#define VUL25_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL25_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 7)
+#define VUL25_WR_SIGN_SFT 6
+#define VUL25_WR_SIGN_MASK 0x1
+#define VUL25_WR_SIGN_MASK_SFT (0x1 << 6)
+#define VUL25_R_MONO_SFT 5
+#define VUL25_R_MONO_MASK 0x1
+#define VUL25_R_MONO_MASK_SFT (0x1 << 5)
+#define VUL25_MONO_SFT 4
+#define VUL25_MONO_MASK 0x1
+#define VUL25_MONO_MASK_SFT (0x1 << 4)
+#define VUL25_NORMAL_MODE_SFT 3
+#define VUL25_NORMAL_MODE_MASK 0x1
+#define VUL25_NORMAL_MODE_MASK_SFT (0x1 << 3)
+#define VUL25_HALIGN_SFT 2
+#define VUL25_HALIGN_MASK 0x1
+#define VUL25_HALIGN_MASK_SFT (0x1 << 2)
+#define VUL25_HD_MODE_SFT 0
+#define VUL25_HD_MODE_MASK 0x3
+#define VUL25_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL25_MON0 */
+#define MEM_HW_WEN_SFT 20
+#define MEM_HW_WEN_MASK 0xf
+#define MEM_HW_WEN_MASK_SFT (0xf << 20)
+#define MEM_REQ_PENDING_SFT 19
+#define MEM_REQ_PENDING_MASK 0x1
+#define MEM_REQ_PENDING_MASK_SFT (0x1 << 19)
+#define BUF_FULL_SFT 18
+#define BUF_FULL_MASK 0x1
+#define BUF_FULL_MASK_SFT (0x1 << 18)
+#define ENABLE_SYNC_MEM_SFT 17
+#define ENABLE_SYNC_MEM_MASK 0x1
+#define ENABLE_SYNC_MEM_MASK_SFT (0x1 << 17)
+#define ENABLE_SYNC_AGENT_SFT 16
+#define ENABLE_SYNC_AGENT_MASK 0x1
+#define ENABLE_SYNC_AGENT_MASK_SFT (0x1 << 16)
+#define RESERVED_02_SFT 6
+#define RESERVED_02_MASK 0x3ff
+#define RESERVED_02_MASK_SFT (0x3ff << 6)
+#define MEM_ADDR_DIFF_SFT 0
+#define MEM_ADDR_DIFF_MASK 0x3f
+#define MEM_ADDR_DIFF_MASK_SFT (0x3f << 0)
+
+/* AFE_VUL_CM0_BASE_MSB */
+#define VUL_CM0_BASE_ADDR_MSB_SFT 0
+#define VUL_CM0_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL_CM0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL_CM0_BASE */
+#define VUL_CM0_BASE_ADDR_SFT 4
+#define VUL_CM0_BASE_ADDR_MASK 0xfffffff
+#define VUL_CM0_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL_CM0_CUR_MSB */
+#define VUL_CM0_CUR_PTR_MSB_SFT 0
+#define VUL_CM0_CUR_PTR_MSB_MASK 0x1ff
+#define VUL_CM0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL_CM0_CUR */
+#define VUL_CM0_CUR_PTR_SFT 0
+#define VUL_CM0_CUR_PTR_MASK 0xffffffff
+#define VUL_CM0_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL_CM0_END_MSB */
+#define VUL_CM0_END_ADDR_MSB_SFT 0
+#define VUL_CM0_END_ADDR_MSB_MASK 0x1ff
+#define VUL_CM0_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL_CM0_END */
+#define VUL_CM0_END_ADDR_SFT 4
+#define VUL_CM0_END_ADDR_MASK 0xfffffff
+#define VUL_CM0_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL_CM0_CON0 */
+#define VUL_CM0_ON_SFT 28
+#define VUL_CM0_ON_MASK 0x1
+#define VUL_CM0_ON_MASK_SFT (0x1 << 28)
+#define VUL_CM0_REG_CH_SHIFT_MODE_SFT 26
+#define VUL_CM0_REG_CH_SHIFT_MODE_MASK 0x1
+#define VUL_CM0_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26)
+#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_SFT 25
+#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_MASK 0x1
+#define VUL_CM0_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25)
+#define VUL_CM0_SW_CLEAR_BUF_FULL_SFT 24
+#define VUL_CM0_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL_CM0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24)
+#define VUL_CM0_ULTRA_TH_SFT 20
+#define VUL_CM0_ULTRA_TH_MASK 0xf
+#define VUL_CM0_ULTRA_TH_MASK_SFT (0xf << 20)
+#define VUL_CM0_NORMAL_MODE_SFT 17
+#define VUL_CM0_NORMAL_MODE_MASK 0x1
+#define VUL_CM0_NORMAL_MODE_MASK_SFT (0x1 << 17)
+#define VUL_CM0_ODD_USE_EVEN_SFT 16
+#define VUL_CM0_ODD_USE_EVEN_MASK 0x1
+#define VUL_CM0_ODD_USE_EVEN_MASK_SFT (0x1 << 16)
+#define VUL_CM0_AXI_REQ_MAXLEN_SFT 12
+#define VUL_CM0_AXI_REQ_MAXLEN_MASK 0x3
+#define VUL_CM0_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12)
+#define VUL_CM0_AXI_REQ_MINLEN_SFT 8
+#define VUL_CM0_AXI_REQ_MINLEN_MASK 0x3
+#define VUL_CM0_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8)
+#define VUL_CM0_HALIGN_SFT 7
+#define VUL_CM0_HALIGN_MASK 0x1
+#define VUL_CM0_HALIGN_MASK_SFT (0x1 << 7)
+#define VUL_CM0_SIGN_EXT_SFT 6
+#define VUL_CM0_SIGN_EXT_MASK 0x1
+#define VUL_CM0_SIGN_EXT_MASK_SFT (0x1 << 6)
+#define VUL_CM0_HD_MODE_SFT 4
+#define VUL_CM0_HD_MODE_MASK 0x3
+#define VUL_CM0_HD_MODE_MASK_SFT (0x3 << 4)
+#define VUL_CM0_MAKE_EXTRA_UPDATE_SFT 3
+#define VUL_CM0_MAKE_EXTRA_UPDATE_MASK 0x1
+#define VUL_CM0_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3)
+#define VUL_CM0_AGENT_FREE_RUN_SFT 2
+#define VUL_CM0_AGENT_FREE_RUN_MASK 0x1
+#define VUL_CM0_AGENT_FREE_RUN_MASK_SFT (0x1 << 2)
+#define VUL_CM0_USE_INT_ODD_SFT 1
+#define VUL_CM0_USE_INT_ODD_MASK 0x1
+#define VUL_CM0_USE_INT_ODD_MASK_SFT (0x1 << 1)
+#define VUL_CM0_INT_ODD_FLAG_SFT 0
+#define VUL_CM0_INT_ODD_FLAG_MASK 0x1
+#define VUL_CM0_INT_ODD_FLAG_MASK_SFT (0x1 << 0)
+
+/* AFE_VUL_CM1_BASE_MSB */
+#define VUL_CM1_BASE_ADDR_MSB_SFT 0
+#define VUL_CM1_BASE_ADDR_MSB_MASK 0x1ff
+#define VUL_CM1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL_CM1_BASE */
+#define VUL_CM1_BASE_ADDR_SFT 4
+#define VUL_CM1_BASE_ADDR_MASK 0xfffffff
+#define VUL_CM1_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL_CM1_CUR_MSB */
+#define VUL_CM1_CUR_PTR_MSB_SFT 0
+#define VUL_CM1_CUR_PTR_MSB_MASK 0x1ff
+#define VUL_CM1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL_CM1_CUR */
+#define VUL_CM1_CUR_PTR_SFT 0
+#define VUL_CM1_CUR_PTR_MASK 0xffffffff
+#define VUL_CM1_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL_CM1_END_MSB */
+#define VUL_CM1_END_ADDR_MSB_SFT 0
+#define VUL_CM1_END_ADDR_MSB_MASK 0x1ff
+#define VUL_CM1_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_VUL_CM1_END */
+#define VUL_CM1_END_ADDR_SFT 4
+#define VUL_CM1_END_ADDR_MASK 0xfffffff
+#define VUL_CM1_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_VUL_CM1_CON0 */
+#define VUL_CM1_ON_SFT 28
+#define VUL_CM1_ON_MASK 0x1
+#define VUL_CM1_ON_MASK_SFT (0x1 << 28)
+#define VUL_CM1_REG_CH_SHIFT_MODE_SFT 26
+#define VUL_CM1_REG_CH_SHIFT_MODE_MASK 0x1
+#define VUL_CM1_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26)
+#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_SFT 25
+#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_MASK 0x1
+#define VUL_CM1_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25)
+#define VUL_CM1_SW_CLEAR_BUF_FULL_SFT 24
+#define VUL_CM1_SW_CLEAR_BUF_FULL_MASK 0x1
+#define VUL_CM1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24)
+#define VUL_CM1_ULTRA_TH_SFT 20
+#define VUL_CM1_ULTRA_TH_MASK 0xf
+#define VUL_CM1_ULTRA_TH_MASK_SFT (0xf << 20)
+#define VUL_CM1_NORMAL_MODE_SFT 17
+#define VUL_CM1_NORMAL_MODE_MASK 0x1
+#define VUL_CM1_NORMAL_MODE_MASK_SFT (0x1 << 17)
+#define VUL_CM1_ODD_USE_EVEN_SFT 16
+#define VUL_CM1_ODD_USE_EVEN_MASK 0x1
+#define VUL_CM1_ODD_USE_EVEN_MASK_SFT (0x1 << 16)
+#define VUL_CM1_AXI_REQ_MAXLEN_SFT 12
+#define VUL_CM1_AXI_REQ_MAXLEN_MASK 0x3
+#define VUL_CM1_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12)
+#define VUL_CM1_AXI_REQ_MINLEN_SFT 8
+#define VUL_CM1_AXI_REQ_MINLEN_MASK 0x3
+#define VUL_CM1_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8)
+#define VUL_CM1_HALIGN_SFT 7
+#define VUL_CM1_HALIGN_MASK 0x1
+#define VUL_CM1_HALIGN_MASK_SFT (0x1 << 7)
+#define VUL_CM1_SIGN_EXT_SFT 6
+#define VUL_CM1_SIGN_EXT_MASK 0x1
+#define VUL_CM1_SIGN_EXT_MASK_SFT (0x1 << 6)
+#define VUL_CM1_HD_MODE_SFT 4
+#define VUL_CM1_HD_MODE_MASK 0x3
+#define VUL_CM1_HD_MODE_MASK_SFT (0x3 << 4)
+#define VUL_CM1_MAKE_EXTRA_UPDATE_SFT 3
+#define VUL_CM1_MAKE_EXTRA_UPDATE_MASK 0x1
+#define VUL_CM1_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3)
+#define VUL_CM1_AGENT_FREE_RUN_SFT 2
+#define VUL_CM1_AGENT_FREE_RUN_MASK 0x1
+#define VUL_CM1_AGENT_FREE_RUN_MASK_SFT (0x1 << 2)
+#define VUL_CM1_USE_INT_ODD_SFT 1
+#define VUL_CM1_USE_INT_ODD_MASK 0x1
+#define VUL_CM1_USE_INT_ODD_MASK_SFT (0x1 << 1)
+#define VUL_CM1_INT_ODD_FLAG_SFT 0
+#define VUL_CM1_INT_ODD_FLAG_MASK 0x1
+#define VUL_CM1_INT_ODD_FLAG_MASK_SFT (0x1 << 0)
+
+/* AFE_ETDM_IN0_BASE_MSB */
+#define ETDM_IN0_BASE_ADDR_MSB_SFT 0
+#define ETDM_IN0_BASE_ADDR_MSB_MASK 0x1ff
+#define ETDM_IN0_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_ETDM_IN0_BASE */
+#define ETDM_IN0_BASE_ADDR_SFT 4
+#define ETDM_IN0_BASE_ADDR_MASK 0xfffffff
+#define ETDM_IN0_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_ETDM_IN0_CUR_MSB */
+#define ETDM_IN0_CUR_PTR_MSB_SFT 0
+#define ETDM_IN0_CUR_PTR_MSB_MASK 0x1ff
+#define ETDM_IN0_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_ETDM_IN0_CUR */
+#define ETDM_IN0_CUR_PTR_SFT 0
+#define ETDM_IN0_CUR_PTR_MASK 0xffffffff
+#define ETDM_IN0_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ETDM_IN0_END_MSB */
+#define ETDM_IN0_END_ADDR_MSB_SFT 0
+#define ETDM_IN0_END_ADDR_MSB_MASK 0x1ff
+#define ETDM_IN0_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_ETDM_IN0_END */
+#define ETDM_IN0_END_ADDR_SFT 4
+#define ETDM_IN0_END_ADDR_MASK 0xfffffff
+#define ETDM_IN0_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_ETDM_IN0_CON0 */
+#define ETDM_IN0_CH_NUM_SFT 28
+#define ETDM_IN0_CH_NUM_MASK 0xf
+#define ETDM_IN0_CH_NUM_MASK_SFT (0xf << 28)
+#define ETDM_IN0_ON_SFT 27
+#define ETDM_IN0_ON_MASK 0x1
+#define ETDM_IN0_ON_MASK_SFT (0x1 << 27)
+#define ETDM_IN0_REG_CH_SHIFT_MODE_SFT 26
+#define ETDM_IN0_REG_CH_SHIFT_MODE_MASK 0x1
+#define ETDM_IN0_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26)
+#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_SFT 25
+#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_MASK 0x1
+#define ETDM_IN0_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25)
+#define ETDM_IN0_SW_CLEAR_BUF_FULL_SFT 24
+#define ETDM_IN0_SW_CLEAR_BUF_FULL_MASK 0x1
+#define ETDM_IN0_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24)
+#define ETDM_IN0_ULTRA_TH_SFT 20
+#define ETDM_IN0_ULTRA_TH_MASK 0xf
+#define ETDM_IN0_ULTRA_TH_MASK_SFT (0xf << 20)
+#define ETDM_IN0_NORMAL_MODE_SFT 17
+#define ETDM_IN0_NORMAL_MODE_MASK 0x1
+#define ETDM_IN0_NORMAL_MODE_MASK_SFT (0x1 << 17)
+#define ETDM_IN0_ODD_USE_EVEN_SFT 16
+#define ETDM_IN0_ODD_USE_EVEN_MASK 0x1
+#define ETDM_IN0_ODD_USE_EVEN_MASK_SFT (0x1 << 16)
+#define ETDM_IN0_AXI_REQ_MAXLEN_SFT 12
+#define ETDM_IN0_AXI_REQ_MAXLEN_MASK 0x3
+#define ETDM_IN0_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12)
+#define ETDM_IN0_AXI_REQ_MINLEN_SFT 8
+#define ETDM_IN0_AXI_REQ_MINLEN_MASK 0x3
+#define ETDM_IN0_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8)
+#define ETDM_IN0_HALIGN_SFT 7
+#define ETDM_IN0_HALIGN_MASK 0x1
+#define ETDM_IN0_HALIGN_MASK_SFT (0x1 << 7)
+#define ETDM_IN0_SIGN_EXT_SFT 6
+#define ETDM_IN0_SIGN_EXT_MASK 0x1
+#define ETDM_IN0_SIGN_EXT_MASK_SFT (0x1 << 6)
+#define ETDM_IN0_HD_MODE_SFT 4
+#define ETDM_IN0_HD_MODE_MASK 0x3
+#define ETDM_IN0_HD_MODE_MASK_SFT (0x3 << 4)
+#define ETDM_IN0_MAKE_EXTRA_UPDATE_SFT 3
+#define ETDM_IN0_MAKE_EXTRA_UPDATE_MASK 0x1
+#define ETDM_IN0_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3)
+#define ETDM_IN0_AGENT_FREE_RUN_SFT 2
+#define ETDM_IN0_AGENT_FREE_RUN_MASK 0x1
+#define ETDM_IN0_AGENT_FREE_RUN_MASK_SFT (0x1 << 2)
+#define ETDM_IN0_USE_INT_ODD_SFT 1
+#define ETDM_IN0_USE_INT_ODD_MASK 0x1
+#define ETDM_IN0_USE_INT_ODD_MASK_SFT (0x1 << 1)
+#define ETDM_IN0_INT_ODD_FLAG_SFT 0
+#define ETDM_IN0_INT_ODD_FLAG_MASK 0x1
+#define ETDM_IN0_INT_ODD_FLAG_MASK_SFT (0x1 << 0)
+
+/* AFE_ETDM_IN1_BASE_MSB */
+#define ETDM_IN1_BASE_ADDR_MSB_SFT 0
+#define ETDM_IN1_BASE_ADDR_MSB_MASK 0x1ff
+#define ETDM_IN1_BASE_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_ETDM_IN1_BASE */
+#define ETDM_IN1_BASE_ADDR_SFT 4
+#define ETDM_IN1_BASE_ADDR_MASK 0xfffffff
+#define ETDM_IN1_BASE_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_ETDM_IN1_CUR_MSB */
+#define ETDM_IN1_CUR_PTR_MSB_SFT 0
+#define ETDM_IN1_CUR_PTR_MSB_MASK 0x1ff
+#define ETDM_IN1_CUR_PTR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_ETDM_IN1_CUR */
+#define ETDM_IN1_CUR_PTR_SFT 0
+#define ETDM_IN1_CUR_PTR_MASK 0xffffffff
+#define ETDM_IN1_CUR_PTR_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ETDM_IN1_END_MSB */
+#define ETDM_IN1_END_ADDR_MSB_SFT 0
+#define ETDM_IN1_END_ADDR_MSB_MASK 0x1ff
+#define ETDM_IN1_END_ADDR_MSB_MASK_SFT (0x1ff << 0)
+
+/* AFE_ETDM_IN1_END */
+#define ETDM_IN1_END_ADDR_SFT 4
+#define ETDM_IN1_END_ADDR_MASK 0xfffffff
+#define ETDM_IN1_END_ADDR_MASK_SFT (0xfffffff << 4)
+
+/* AFE_ETDM_IN1_CON0 */
+#define ETDM_IN1_CH_NUM_SFT 28
+#define ETDM_IN1_CH_NUM_MASK 0xf
+#define ETDM_IN1_CH_NUM_MASK_SFT (0xf << 28)
+#define ETDM_IN1_ON_SFT 27
+#define ETDM_IN1_ON_MASK 0x1
+#define ETDM_IN1_ON_MASK_SFT (0x1 << 27)
+#define ETDM_IN1_REG_CH_SHIFT_MODE_SFT 26
+#define ETDM_IN1_REG_CH_SHIFT_MODE_MASK 0x1
+#define ETDM_IN1_REG_CH_SHIFT_MODE_MASK_SFT (0x1 << 26)
+#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_SFT 25
+#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_MASK 0x1
+#define ETDM_IN1_RG_FORCE_NO_MASK_EXTRA_MASK_SFT (0x1 << 25)
+#define ETDM_IN1_SW_CLEAR_BUF_FULL_SFT 24
+#define ETDM_IN1_SW_CLEAR_BUF_FULL_MASK 0x1
+#define ETDM_IN1_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 24)
+#define ETDM_IN1_ULTRA_TH_SFT 20
+#define ETDM_IN1_ULTRA_TH_MASK 0xf
+#define ETDM_IN1_ULTRA_TH_MASK_SFT (0xf << 20)
+#define ETDM_IN1_NORMAL_MODE_SFT 17
+#define ETDM_IN1_NORMAL_MODE_MASK 0x1
+#define ETDM_IN1_NORMAL_MODE_MASK_SFT (0x1 << 17)
+#define ETDM_IN1_ODD_USE_EVEN_SFT 16
+#define ETDM_IN1_ODD_USE_EVEN_MASK 0x1
+#define ETDM_IN1_ODD_USE_EVEN_MASK_SFT (0x1 << 16)
+#define ETDM_IN1_AXI_REQ_MAXLEN_SFT 12
+#define ETDM_IN1_AXI_REQ_MAXLEN_MASK 0x3
+#define ETDM_IN1_AXI_REQ_MAXLEN_MASK_SFT (0x3 << 12)
+#define ETDM_IN1_AXI_REQ_MINLEN_SFT 8
+#define ETDM_IN1_AXI_REQ_MINLEN_MASK 0x3
+#define ETDM_IN1_AXI_REQ_MINLEN_MASK_SFT (0x3 << 8)
+#define ETDM_IN1_HALIGN_SFT 7
+#define ETDM_IN1_HALIGN_MASK 0x1
+#define ETDM_IN1_HALIGN_MASK_SFT (0x1 << 7)
+#define ETDM_IN1_SIGN_EXT_SFT 6
+#define ETDM_IN1_SIGN_EXT_MASK 0x1
+#define ETDM_IN1_SIGN_EXT_MASK_SFT (0x1 << 6)
+#define ETDM_IN1_HD_MODE_SFT 4
+#define ETDM_IN1_HD_MODE_MASK 0x3
+#define ETDM_IN1_HD_MODE_MASK_SFT (0x3 << 4)
+#define ETDM_IN1_MAKE_EXTRA_UPDATE_SFT 3
+#define ETDM_IN1_MAKE_EXTRA_UPDATE_MASK 0x1
+#define ETDM_IN1_MAKE_EXTRA_UPDATE_MASK_SFT (0x1 << 3)
+#define ETDM_IN1_AGENT_FREE_RUN_SFT 2
+#define ETDM_IN1_AGENT_FREE_RUN_MASK 0x1
+#define ETDM_IN1_AGENT_FREE_RUN_MASK_SFT (0x1 << 2)
+#define ETDM_IN1_USE_INT_ODD_SFT 1
+#define ETDM_IN1_USE_INT_ODD_MASK 0x1
+#define ETDM_IN1_USE_INT_ODD_MASK_SFT (0x1 << 1)
+#define ETDM_IN1_INT_ODD_FLAG_SFT 0
+#define ETDM_IN1_INT_ODD_FLAG_MASK 0x1
+#define ETDM_IN1_INT_ODD_FLAG_MASK_SFT (0x1 << 0)
+
+/* AFE_VUL24_RCH_MON */
+#define VUL24_RCH_DATA_SFT 0
+#define VUL24_RCH_DATA_MASK 0xffffffff
+#define VUL24_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL24_LCH_MON */
+#define VUL24_LCH_DATA_SFT 0
+#define VUL24_LCH_DATA_MASK 0xffffffff
+#define VUL24_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL25_RCH_MON */
+#define VUL25_RCH_DATA_SFT 0
+#define VUL25_RCH_DATA_MASK 0xffffffff
+#define VUL25_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL25_LCH_MON */
+#define VUL25_LCH_DATA_SFT 0
+#define VUL25_LCH_DATA_MASK 0xffffffff
+#define VUL25_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL_CM0_RCH_MON */
+#define VUL_CM0_RCH_DATA_SFT 0
+#define VUL_CM0_RCH_DATA_MASK 0xffffffff
+#define VUL_CM0_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL_CM0_LCH_MON */
+#define VUL_CM0_LCH_DATA_SFT 0
+#define VUL_CM0_LCH_DATA_MASK 0xffffffff
+#define VUL_CM0_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL_CM1_RCH_MON */
+#define VUL_CM1_RCH_DATA_SFT 0
+#define VUL_CM1_RCH_DATA_MASK 0xffffffff
+#define VUL_CM1_RCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_VUL_CM1_LCH_MON */
+#define VUL_CM1_LCH_DATA_SFT 0
+#define VUL_CM1_LCH_DATA_MASK 0xffffffff
+#define VUL_CM1_LCH_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH0_MON */
+#define DL_24CH_CH0_DATA_SFT 0
+#define DL_24CH_CH0_DATA_MASK 0xffffffff
+#define DL_24CH_CH0_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH1_MON */
+#define DL_24CH_CH1_DATA_SFT 0
+#define DL_24CH_CH1_DATA_MASK 0xffffffff
+#define DL_24CH_CH1_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH2_MON */
+#define DL_24CH_CH2_DATA_SFT 0
+#define DL_24CH_CH2_DATA_MASK 0xffffffff
+#define DL_24CH_CH2_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH3_MON */
+#define DL_24CH_CH3_DATA_SFT 0
+#define DL_24CH_CH3_DATA_MASK 0xffffffff
+#define DL_24CH_CH3_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH4_MON */
+#define DL_24CH_CH4_DATA_SFT 0
+#define DL_24CH_CH4_DATA_MASK 0xffffffff
+#define DL_24CH_CH4_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH5_MON */
+#define DL_24CH_CH5_DATA_SFT 0
+#define DL_24CH_CH5_DATA_MASK 0xffffffff
+#define DL_24CH_CH5_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH6_MON */
+#define DL_24CH_CH6_DATA_SFT 0
+#define DL_24CH_CH6_DATA_MASK 0xffffffff
+#define DL_24CH_CH6_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DL_24CH_CH7_MON */
+#define DL_24CH_CH7_DATA_SFT 0
+#define DL_24CH_CH7_DATA_MASK 0xffffffff
+#define DL_24CH_CH7_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SRAM_BOUND */
+#define SECURE_BIT_SFT 19
+#define SECURE_BIT_MASK 0x1
+#define SECURE_BIT_MASK_SFT (0x1 << 19)
+#define SECURE_SRAM_BOUND_SFT 0
+#define SECURE_SRAM_BOUND_MASK 0x7ffff
+#define SECURE_SRAM_BOUND_MASK_SFT (0x7ffff << 0)
+
+/* AFE_SECURE_CON0 */
+#define READ_EN15_NS_SFT 31
+#define READ_EN15_NS_MASK 0x1
+#define READ_EN15_NS_MASK_SFT (0x1 << 31)
+#define WRITE_EN15_NS_SFT 30
+#define WRITE_EN15_NS_MASK 0x1
+#define WRITE_EN15_NS_MASK_SFT (0x1 << 30)
+#define READ_EN14_NS_SFT 29
+#define READ_EN14_NS_MASK 0x1
+#define READ_EN14_NS_MASK_SFT (0x1 << 29)
+#define WRITE_EN14_NS_SFT 28
+#define WRITE_EN14_NS_MASK 0x1
+#define WRITE_EN14_NS_MASK_SFT (0x1 << 28)
+#define READ_EN13_NS_SFT 27
+#define READ_EN13_NS_MASK 0x1
+#define READ_EN13_NS_MASK_SFT (0x1 << 27)
+#define WRITE_EN13_NS_SFT 26
+#define WRITE_EN13_NS_MASK 0x1
+#define WRITE_EN13_NS_MASK_SFT (0x1 << 26)
+#define READ_EN12_NS_SFT 25
+#define READ_EN12_NS_MASK 0x1
+#define READ_EN12_NS_MASK_SFT (0x1 << 25)
+#define WRITE_EN12_NS_SFT 24
+#define WRITE_EN12_NS_MASK 0x1
+#define WRITE_EN12_NS_MASK_SFT (0x1 << 24)
+#define READ_EN11_NS_SFT 23
+#define READ_EN11_NS_MASK 0x1
+#define READ_EN11_NS_MASK_SFT (0x1 << 23)
+#define WRITE_EN11_NS_SFT 22
+#define WRITE_EN11_NS_MASK 0x1
+#define WRITE_EN11_NS_MASK_SFT (0x1 << 22)
+#define READ_EN10_NS_SFT 21
+#define READ_EN10_NS_MASK 0x1
+#define READ_EN10_NS_MASK_SFT (0x1 << 21)
+#define WRITE_EN10_NS_SFT 20
+#define WRITE_EN10_NS_MASK 0x1
+#define WRITE_EN10_NS_MASK_SFT (0x1 << 20)
+#define READ_EN9_NS_SFT 19
+#define READ_EN9_NS_MASK 0x1
+#define READ_EN9_NS_MASK_SFT (0x1 << 19)
+#define WRITE_EN9_NS_SFT 18
+#define WRITE_EN9_NS_MASK 0x1
+#define WRITE_EN9_NS_MASK_SFT (0x1 << 18)
+#define READ_EN8_NS_SFT 17
+#define READ_EN8_NS_MASK 0x1
+#define READ_EN8_NS_MASK_SFT (0x1 << 17)
+#define WRITE_EN8_NS_SFT 16
+#define WRITE_EN8_NS_MASK 0x1
+#define WRITE_EN8_NS_MASK_SFT (0x1 << 16)
+#define READ_EN7_NS_SFT 15
+#define READ_EN7_NS_MASK 0x1
+#define READ_EN7_NS_MASK_SFT (0x1 << 15)
+#define WRITE_EN7_NS_SFT 14
+#define WRITE_EN7_NS_MASK 0x1
+#define WRITE_EN7_NS_MASK_SFT (0x1 << 14)
+#define READ_EN6_NS_SFT 13
+#define READ_EN6_NS_MASK 0x1
+#define READ_EN6_NS_MASK_SFT (0x1 << 13)
+#define WRITE_EN6_NS_SFT 12
+#define WRITE_EN6_NS_MASK 0x1
+#define WRITE_EN6_NS_MASK_SFT (0x1 << 12)
+#define READ_EN5_NS_SFT 11
+#define READ_EN5_NS_MASK 0x1
+#define READ_EN5_NS_MASK_SFT (0x1 << 11)
+#define WRITE_EN5_NS_SFT 10
+#define WRITE_EN5_NS_MASK 0x1
+#define WRITE_EN5_NS_MASK_SFT (0x1 << 10)
+#define READ_EN4_NS_SFT 9
+#define READ_EN4_NS_MASK 0x1
+#define READ_EN4_NS_MASK_SFT (0x1 << 9)
+#define WRITE_EN4_NS_SFT 8
+#define WRITE_EN4_NS_MASK 0x1
+#define WRITE_EN4_NS_MASK_SFT (0x1 << 8)
+#define READ_EN3_NS_SFT 7
+#define READ_EN3_NS_MASK 0x1
+#define READ_EN3_NS_MASK_SFT (0x1 << 7)
+#define WRITE_EN3_NS_SFT 6
+#define WRITE_EN3_NS_MASK 0x1
+#define WRITE_EN3_NS_MASK_SFT (0x1 << 6)
+#define READ_EN2_NS_SFT 5
+#define READ_EN2_NS_MASK 0x1
+#define READ_EN2_NS_MASK_SFT (0x1 << 5)
+#define WRITE_EN2_NS_SFT 4
+#define WRITE_EN2_NS_MASK 0x1
+#define WRITE_EN2_NS_MASK_SFT (0x1 << 4)
+#define READ_EN1_NS_SFT 3
+#define READ_EN1_NS_MASK 0x1
+#define READ_EN1_NS_MASK_SFT (0x1 << 3)
+#define WRITE_EN1_NS_SFT 2
+#define WRITE_EN1_NS_MASK 0x1
+#define WRITE_EN1_NS_MASK_SFT (0x1 << 2)
+#define READ_EN0_NS_SFT 1
+#define READ_EN0_NS_MASK 0x1
+#define READ_EN0_NS_MASK_SFT (0x1 << 1)
+#define WRITE_EN0_NS_SFT 0
+#define WRITE_EN0_NS_MASK 0x1
+#define WRITE_EN0_NS_MASK_SFT (0x1 << 0)
+
+/* AFE_SECURE_CON1 */
+#define READ_EN15_S_SFT 31
+#define READ_EN15_S_MASK 0x1
+#define READ_EN15_S_MASK_SFT (0x1 << 31)
+#define WRITE_EN15_S_SFT 30
+#define WRITE_EN15_S_MASK 0x1
+#define WRITE_EN15_S_MASK_SFT (0x1 << 30)
+#define READ_EN14_S_SFT 29
+#define READ_EN14_S_MASK 0x1
+#define READ_EN14_S_MASK_SFT (0x1 << 29)
+#define WRITE_EN14_S_SFT 28
+#define WRITE_EN14_S_MASK 0x1
+#define WRITE_EN14_S_MASK_SFT (0x1 << 28)
+#define READ_EN13_S_SFT 27
+#define READ_EN13_S_MASK 0x1
+#define READ_EN13_S_MASK_SFT (0x1 << 27)
+#define WRITE_EN13_S_SFT 26
+#define WRITE_EN13_S_MASK 0x1
+#define WRITE_EN13_S_MASK_SFT (0x1 << 26)
+#define READ_EN12_S_SFT 25
+#define READ_EN12_S_MASK 0x1
+#define READ_EN12_S_MASK_SFT (0x1 << 25)
+#define WRITE_EN12_S_SFT 24
+#define WRITE_EN12_S_MASK 0x1
+#define WRITE_EN12_S_MASK_SFT (0x1 << 24)
+#define READ_EN11_S_SFT 23
+#define READ_EN11_S_MASK 0x1
+#define READ_EN11_S_MASK_SFT (0x1 << 23)
+#define WRITE_EN11_S_SFT 22
+#define WRITE_EN11_S_MASK 0x1
+#define WRITE_EN11_S_MASK_SFT (0x1 << 22)
+#define READ_EN10_S_SFT 21
+#define READ_EN10_S_MASK 0x1
+#define READ_EN10_S_MASK_SFT (0x1 << 21)
+#define WRITE_EN10_S_SFT 20
+#define WRITE_EN10_S_MASK 0x1
+#define WRITE_EN10_S_MASK_SFT (0x1 << 20)
+#define READ_EN9_S_SFT 19
+#define READ_EN9_S_MASK 0x1
+#define READ_EN9_S_MASK_SFT (0x1 << 19)
+#define WRITE_EN9_S_SFT 18
+#define WRITE_EN9_S_MASK 0x1
+#define WRITE_EN9_S_MASK_SFT (0x1 << 18)
+#define READ_EN8_S_SFT 17
+#define READ_EN8_S_MASK 0x1
+#define READ_EN8_S_MASK_SFT (0x1 << 17)
+#define WRITE_EN8_S_SFT 16
+#define WRITE_EN8_S_MASK 0x1
+#define WRITE_EN8_S_MASK_SFT (0x1 << 16)
+#define READ_EN7_S_SFT 15
+#define READ_EN7_S_MASK 0x1
+#define READ_EN7_S_MASK_SFT (0x1 << 15)
+#define WRITE_EN7_S_SFT 14
+#define WRITE_EN7_S_MASK 0x1
+#define WRITE_EN7_S_MASK_SFT (0x1 << 14)
+#define READ_EN6_S_SFT 13
+#define READ_EN6_S_MASK 0x1
+#define READ_EN6_S_MASK_SFT (0x1 << 13)
+#define WRITE_EN6_S_SFT 12
+#define WRITE_EN6_S_MASK 0x1
+#define WRITE_EN6_S_MASK_SFT (0x1 << 12)
+#define READ_EN5_S_SFT 11
+#define READ_EN5_S_MASK 0x1
+#define READ_EN5_S_MASK_SFT (0x1 << 11)
+#define WRITE_EN5_S_SFT 10
+#define WRITE_EN5_S_MASK 0x1
+#define WRITE_EN5_S_MASK_SFT (0x1 << 10)
+#define READ_EN4_S_SFT 9
+#define READ_EN4_S_MASK 0x1
+#define READ_EN4_S_MASK_SFT (0x1 << 9)
+#define WRITE_EN4_S_SFT 8
+#define WRITE_EN4_S_MASK 0x1
+#define WRITE_EN4_S_MASK_SFT (0x1 << 8)
+#define READ_EN3_S_SFT 7
+#define READ_EN3_S_MASK 0x1
+#define READ_EN3_S_MASK_SFT (0x1 << 7)
+#define WRITE_EN3_S_SFT 6
+#define WRITE_EN3_S_MASK 0x1
+#define WRITE_EN3_S_MASK_SFT (0x1 << 6)
+#define READ_EN2_S_SFT 5
+#define READ_EN2_S_MASK 0x1
+#define READ_EN2_S_MASK_SFT (0x1 << 5)
+#define WRITE_EN2_S_SFT 4
+#define WRITE_EN2_S_MASK 0x1
+#define WRITE_EN2_S_MASK_SFT (0x1 << 4)
+#define READ_EN1_S_SFT 3
+#define READ_EN1_S_MASK 0x1
+#define READ_EN1_S_MASK_SFT (0x1 << 3)
+#define WRITE_EN1_S_SFT 2
+#define WRITE_EN1_S_MASK 0x1
+#define WRITE_EN1_S_MASK_SFT (0x1 << 2)
+#define READ_EN0_S_SFT 1
+#define READ_EN0_S_MASK 0x1
+#define READ_EN0_S_MASK_SFT (0x1 << 1)
+#define WRITE_EN0_S_SFT 0
+#define WRITE_EN0_S_MASK 0x1
+#define WRITE_EN0_S_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_SECURE_CON0 */
+#define AFE_HDMI_SE_SECURE_BIT_SFT 11
+#define AFE_HDMI_SE_SECURE_BIT_MASK 0x1
+#define AFE_HDMI_SE_SECURE_BIT_MASK_SFT (0x1 << 11)
+#define AFE_SPDIF2_OUT_SE_SECURE_BIT_SFT 10
+#define AFE_SPDIF2_OUT_SE_SECURE_BIT_MASK 0x1
+#define AFE_SPDIF2_OUT_SE_SECURE_BIT_MASK_SFT (0x1 << 10)
+#define AFE_SPDIF_OUT_SE_SECURE_BIT_SFT 9
+#define AFE_SPDIF_OUT_SE_SECURE_BIT_MASK 0x1
+#define AFE_SPDIF_OUT_SE_SECURE_BIT_MASK_SFT (0x1 << 9)
+#define AFE_DL8_SE_SECURE_BIT_SFT 8
+#define AFE_DL8_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL8_SE_SECURE_BIT_MASK_SFT (0x1 << 8)
+#define AFE_DL7_SE_SECURE_BIT_SFT 7
+#define AFE_DL7_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL7_SE_SECURE_BIT_MASK_SFT (0x1 << 7)
+#define AFE_DL6_SE_SECURE_BIT_SFT 6
+#define AFE_DL6_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL6_SE_SECURE_BIT_MASK_SFT (0x1 << 6)
+#define AFE_DL5_SE_SECURE_BIT_SFT 5
+#define AFE_DL5_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL5_SE_SECURE_BIT_MASK_SFT (0x1 << 5)
+#define AFE_DL4_SE_SECURE_BIT_SFT 4
+#define AFE_DL4_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL4_SE_SECURE_BIT_MASK_SFT (0x1 << 4)
+#define AFE_DL3_SE_SECURE_BIT_SFT 3
+#define AFE_DL3_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL3_SE_SECURE_BIT_MASK_SFT (0x1 << 3)
+#define AFE_DL2_SE_SECURE_BIT_SFT 2
+#define AFE_DL2_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL2_SE_SECURE_BIT_MASK_SFT (0x1 << 2)
+#define AFE_DL1_SE_SECURE_BIT_SFT 1
+#define AFE_DL1_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL1_SE_SECURE_BIT_MASK_SFT (0x1 << 1)
+#define AFE_DL0_SE_SECURE_BIT_SFT 0
+#define AFE_DL0_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL0_SE_SECURE_BIT_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_SECURE_CON1 */
+#define AFE_DL46_SE_SECURE_BIT_SFT 26
+#define AFE_DL46_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL46_SE_SECURE_BIT_MASK_SFT (0x1 << 26)
+#define AFE_DL45_SE_SECURE_BIT_SFT 25
+#define AFE_DL45_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL45_SE_SECURE_BIT_MASK_SFT (0x1 << 25)
+#define AFE_DL44_SE_SECURE_BIT_SFT 24
+#define AFE_DL44_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL44_SE_SECURE_BIT_MASK_SFT (0x1 << 24)
+#define AFE_DL43_SE_SECURE_BIT_SFT 23
+#define AFE_DL43_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL43_SE_SECURE_BIT_MASK_SFT (0x1 << 23)
+#define AFE_DL42_SE_SECURE_BIT_SFT 22
+#define AFE_DL42_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL42_SE_SECURE_BIT_MASK_SFT (0x1 << 22)
+#define AFE_DL41_SE_SECURE_BIT_SFT 21
+#define AFE_DL41_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL41_SE_SECURE_BIT_MASK_SFT (0x1 << 21)
+#define AFE_DL40_SE_SECURE_BIT_SFT 20
+#define AFE_DL40_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL40_SE_SECURE_BIT_MASK_SFT (0x1 << 20)
+#define AFE_DL39_SE_SECURE_BIT_SFT 19
+#define AFE_DL39_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL39_SE_SECURE_BIT_MASK_SFT (0x1 << 19)
+#define AFE_DL38_SE_SECURE_BIT_SFT 18
+#define AFE_DL38_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL38_SE_SECURE_BIT_MASK_SFT (0x1 << 18)
+#define AFE_DL37_SE_SECURE_BIT_SFT 17
+#define AFE_DL37_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL37_SE_SECURE_BIT_MASK_SFT (0x1 << 17)
+#define AFE_DL36_SE_SECURE_BIT_SFT 16
+#define AFE_DL36_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL36_SE_SECURE_BIT_MASK_SFT (0x1 << 16)
+#define AFE_DL35_SE_SECURE_BIT_SFT 15
+#define AFE_DL35_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL35_SE_SECURE_BIT_MASK_SFT (0x1 << 15)
+#define AFE_DL34_SE_SECURE_BIT_SFT 14
+#define AFE_DL34_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL34_SE_SECURE_BIT_MASK_SFT (0x1 << 14)
+#define AFE_DL33_SE_SECURE_BIT_SFT 13
+#define AFE_DL33_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL33_SE_SECURE_BIT_MASK_SFT (0x1 << 13)
+#define AFE_DL32_SE_SECURE_BIT_SFT 12
+#define AFE_DL32_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL32_SE_SECURE_BIT_MASK_SFT (0x1 << 12)
+#define AFE_DL31_SE_SECURE_BIT_SFT 11
+#define AFE_DL31_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL31_SE_SECURE_BIT_MASK_SFT (0x1 << 11)
+#define AFE_DL30_SE_SECURE_BIT_SFT 10
+#define AFE_DL30_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL30_SE_SECURE_BIT_MASK_SFT (0x1 << 10)
+#define AFE_DL29_SE_SECURE_BIT_SFT 9
+#define AFE_DL29_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL29_SE_SECURE_BIT_MASK_SFT (0x1 << 9)
+#define AFE_DL28_SE_SECURE_BIT_SFT 8
+#define AFE_DL28_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL28_SE_SECURE_BIT_MASK_SFT (0x1 << 8)
+#define AFE_DL27_SE_SECURE_BIT_SFT 7
+#define AFE_DL27_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL27_SE_SECURE_BIT_MASK_SFT (0x1 << 7)
+#define AFE_DL26_SE_SECURE_BIT_SFT 6
+#define AFE_DL26_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL26_SE_SECURE_BIT_MASK_SFT (0x1 << 6)
+#define AFE_DL25_SE_SECURE_BIT_SFT 5
+#define AFE_DL25_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL25_SE_SECURE_BIT_MASK_SFT (0x1 << 5)
+#define AFE_DL24_SE_SECURE_BIT_SFT 4
+#define AFE_DL24_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL24_SE_SECURE_BIT_MASK_SFT (0x1 << 4)
+#define AFE_DL23_SE_SECURE_BIT_SFT 3
+#define AFE_DL23_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL23_SE_SECURE_BIT_MASK_SFT (0x1 << 3)
+#define AFE_DL_48CH_SE_SECURE_BIT_SFT 2
+#define AFE_DL_48CH_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL_48CH_SE_SECURE_BIT_MASK_SFT (0x1 << 2)
+#define AFE_DL_24CH_SE_SECURE_BIT_SFT 1
+#define AFE_DL_24CH_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL_24CH_SE_SECURE_BIT_MASK_SFT (0x1 << 1)
+#define AFE_DL_4CH_SE_SECURE_BIT_SFT 0
+#define AFE_DL_4CH_SE_SECURE_BIT_MASK 0x1
+#define AFE_DL_4CH_SE_SECURE_BIT_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_SECURE_CON2 */
+#define AFE_VUL38_SE_SECURE_BIT_SFT 28
+#define AFE_VUL38_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL38_SE_SECURE_BIT_MASK_SFT (0x1 << 28)
+#define AFE_VUL37_SE_SECURE_BIT_SFT 27
+#define AFE_VUL37_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL37_SE_SECURE_BIT_MASK_SFT (0x1 << 27)
+#define AFE_VUL36_SE_SECURE_BIT_SFT 26
+#define AFE_VUL36_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL36_SE_SECURE_BIT_MASK_SFT (0x1 << 26)
+#define AFE_VUL35_SE_SECURE_BIT_SFT 25
+#define AFE_VUL35_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL35_SE_SECURE_BIT_MASK_SFT (0x1 << 25)
+#define AFE_VUL34_SE_SECURE_BIT_SFT 24
+#define AFE_VUL34_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL34_SE_SECURE_BIT_MASK_SFT (0x1 << 24)
+#define AFE_VUL33_SE_SECURE_BIT_SFT 23
+#define AFE_VUL33_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL33_SE_SECURE_BIT_MASK_SFT (0x1 << 23)
+#define AFE_VUL32_SE_SECURE_BIT_SFT 22
+#define AFE_VUL32_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL32_SE_SECURE_BIT_MASK_SFT (0x1 << 22)
+#define AFE_VUL31_SE_SECURE_BIT_SFT 21
+#define AFE_VUL31_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL31_SE_SECURE_BIT_MASK_SFT (0x1 << 21)
+#define AFE_VUL30_SE_SECURE_BIT_SFT 20
+#define AFE_VUL30_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL30_SE_SECURE_BIT_MASK_SFT (0x1 << 20)
+#define AFE_VUL29_SE_SECURE_BIT_SFT 19
+#define AFE_VUL29_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL29_SE_SECURE_BIT_MASK_SFT (0x1 << 19)
+#define AFE_VUL28_SE_SECURE_BIT_SFT 18
+#define AFE_VUL28_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL28_SE_SECURE_BIT_MASK_SFT (0x1 << 18)
+#define AFE_VUL27_SE_SECURE_BIT_SFT 17
+#define AFE_VUL27_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL27_SE_SECURE_BIT_MASK_SFT (0x1 << 17)
+#define AFE_VUL26_SE_SECURE_BIT_SFT 16
+#define AFE_VUL26_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL26_SE_SECURE_BIT_MASK_SFT (0x1 << 16)
+#define AFE_VUL25_SE_SECURE_BIT_SFT 15
+#define AFE_VUL25_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL25_SE_SECURE_BIT_MASK_SFT (0x1 << 15)
+#define AFE_VUL24_SE_SECURE_BIT_SFT 14
+#define AFE_VUL24_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL24_SE_SECURE_BIT_MASK_SFT (0x1 << 14)
+#define AFE_VUL_CM2_SE_SECURE_BIT_SFT 13
+#define AFE_VUL_CM2_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL_CM2_SE_SECURE_BIT_MASK_SFT (0x1 << 13)
+#define AFE_VUL_CM1_SE_SECURE_BIT_SFT 12
+#define AFE_VUL_CM1_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL_CM1_SE_SECURE_BIT_MASK_SFT (0x1 << 12)
+#define AFE_VUL_CM0_SE_SECURE_BIT_SFT 11
+#define AFE_VUL_CM0_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL_CM0_SE_SECURE_BIT_MASK_SFT (0x1 << 11)
+#define AFE_VUL10_SE_SECURE_BIT_SFT 10
+#define AFE_VUL10_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL10_SE_SECURE_BIT_MASK_SFT (0x1 << 10)
+#define AFE_VUL9_SE_SECURE_BIT_SFT 9
+#define AFE_VUL9_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL9_SE_SECURE_BIT_MASK_SFT (0x1 << 9)
+#define AFE_VUL8_SE_SECURE_BIT_SFT 8
+#define AFE_VUL8_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL8_SE_SECURE_BIT_MASK_SFT (0x1 << 8)
+#define AFE_VUL7_SE_SECURE_BIT_SFT 7
+#define AFE_VUL7_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL7_SE_SECURE_BIT_MASK_SFT (0x1 << 7)
+#define AFE_VUL6_SE_SECURE_BIT_SFT 6
+#define AFE_VUL6_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL6_SE_SECURE_BIT_MASK_SFT (0x1 << 6)
+#define AFE_VUL5_SE_SECURE_BIT_SFT 5
+#define AFE_VUL5_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL5_SE_SECURE_BIT_MASK_SFT (0x1 << 5)
+#define AFE_VUL4_SE_SECURE_BIT_SFT 4
+#define AFE_VUL4_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL4_SE_SECURE_BIT_MASK_SFT (0x1 << 4)
+#define AFE_VUL3_SE_SECURE_BIT_SFT 3
+#define AFE_VUL3_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL3_SE_SECURE_BIT_MASK_SFT (0x1 << 3)
+#define AFE_VUL2_SE_SECURE_BIT_SFT 2
+#define AFE_VUL2_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL2_SE_SECURE_BIT_MASK_SFT (0x1 << 2)
+#define AFE_VUL1_SE_SECURE_BIT_SFT 1
+#define AFE_VUL1_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL1_SE_SECURE_BIT_MASK_SFT (0x1 << 1)
+#define AFE_VUL0_SE_SECURE_BIT_SFT 0
+#define AFE_VUL0_SE_SECURE_BIT_MASK 0x1
+#define AFE_VUL0_SE_SECURE_BIT_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_SECURE_CON3 */
+#define AFE_SPDIFIN_SE_SECURE_BIT_SFT 10
+#define AFE_SPDIFIN_SE_SECURE_BIT_MASK 0x1
+#define AFE_SPDIFIN_SE_SECURE_BIT_MASK_SFT (0x1 << 10)
+#define AFE_TDM_IN_SE_SECURE_BIT_SFT 9
+#define AFE_TDM_IN_SE_SECURE_BIT_MASK 0x1
+#define AFE_TDM_IN_SE_SECURE_BIT_MASK_SFT (0x1 << 9)
+#define AFE_MPHONE_EARC_SE_SECURE_BIT_SFT 8
+#define AFE_MPHONE_EARC_SE_SECURE_BIT_MASK 0x1
+#define AFE_MPHONE_EARC_SE_SECURE_BIT_MASK_SFT (0x1 << 8)
+#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_SFT 7
+#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_MASK 0x1
+#define AFE_MPHONE_SPDIF_SE_SECURE_BIT_MASK_SFT (0x1 << 7)
+#define AFE_ETDM_IN1_SE_SECURE_BIT_SFT 1
+#define AFE_ETDM_IN1_SE_SECURE_BIT_MASK 0x1
+#define AFE_ETDM_IN1_SE_SECURE_BIT_MASK_SFT (0x1 << 1)
+#define AFE_ETDM_IN0_SE_SECURE_BIT_SFT 0
+#define AFE_ETDM_IN0_SE_SECURE_BIT_MASK 0x1
+#define AFE_ETDM_IN0_SE_SECURE_BIT_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_PROT_SIDEBAND0 */
+#define HDMI_HPROT_SFT 11
+#define HDMI_HPROT_MASK 0x1
+#define HDMI_HPROT_MASK_SFT (0x1 << 11)
+#define SPDIF2_OUT_HPROT_SFT 10
+#define SPDIF2_OUT_HPROT_MASK 0x1
+#define SPDIF2_OUT_HPROT_MASK_SFT (0x1 << 10)
+#define SPDIF_OUT_HPROT_SFT 9
+#define SPDIF_OUT_HPROT_MASK 0x1
+#define SPDIF_OUT_HPROT_MASK_SFT (0x1 << 9)
+#define DL8_HPROT_SFT 8
+#define DL8_HPROT_MASK 0x1
+#define DL8_HPROT_MASK_SFT (0x1 << 8)
+#define DL7_HPROT_SFT 7
+#define DL7_HPROT_MASK 0x1
+#define DL7_HPROT_MASK_SFT (0x1 << 7)
+#define DL6_HPROT_SFT 6
+#define DL6_HPROT_MASK 0x1
+#define DL6_HPROT_MASK_SFT (0x1 << 6)
+#define DL5_HPROT_SFT 5
+#define DL5_HPROT_MASK 0x1
+#define DL5_HPROT_MASK_SFT (0x1 << 5)
+#define DL4_HPROT_SFT 4
+#define DL4_HPROT_MASK 0x1
+#define DL4_HPROT_MASK_SFT (0x1 << 4)
+#define DL3_HPROT_SFT 3
+#define DL3_HPROT_MASK 0x1
+#define DL3_HPROT_MASK_SFT (0x1 << 3)
+#define DL2_HPROT_SFT 2
+#define DL2_HPROT_MASK 0x1
+#define DL2_HPROT_MASK_SFT (0x1 << 2)
+#define DL1_HPROT_SFT 1
+#define DL1_HPROT_MASK 0x1
+#define DL1_HPROT_MASK_SFT (0x1 << 1)
+#define DL0_HPROT_SFT 0
+#define DL0_HPROT_MASK 0x1
+#define DL0_HPROT_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_PROT_SIDEBAND1 */
+#define DL46_HPROT_SFT 26
+#define DL46_HPROT_MASK 0x1
+#define DL46_HPROT_MASK_SFT (0x1 << 26)
+#define DL45_HPROT_SFT 25
+#define DL45_HPROT_MASK 0x1
+#define DL45_HPROT_MASK_SFT (0x1 << 25)
+#define DL44_HPROT_SFT 24
+#define DL44_HPROT_MASK 0x1
+#define DL44_HPROT_MASK_SFT (0x1 << 24)
+#define DL43_HPROT_SFT 23
+#define DL43_HPROT_MASK 0x1
+#define DL43_HPROT_MASK_SFT (0x1 << 23)
+#define DL42_HPROT_SFT 22
+#define DL42_HPROT_MASK 0x1
+#define DL42_HPROT_MASK_SFT (0x1 << 22)
+#define DL41_HPROT_SFT 21
+#define DL41_HPROT_MASK 0x1
+#define DL41_HPROT_MASK_SFT (0x1 << 21)
+#define DL40_HPROT_SFT 20
+#define DL40_HPROT_MASK 0x1
+#define DL40_HPROT_MASK_SFT (0x1 << 20)
+#define DL39_HPROT_SFT 19
+#define DL39_HPROT_MASK 0x1
+#define DL39_HPROT_MASK_SFT (0x1 << 19)
+#define DL38_HPROT_SFT 18
+#define DL38_HPROT_MASK 0x1
+#define DL38_HPROT_MASK_SFT (0x1 << 18)
+#define DL37_HPROT_SFT 17
+#define DL37_HPROT_MASK 0x1
+#define DL37_HPROT_MASK_SFT (0x1 << 17)
+#define DL36_HPROT_SFT 16
+#define DL36_HPROT_MASK 0x1
+#define DL36_HPROT_MASK_SFT (0x1 << 16)
+#define DL35_HPROT_SFT 15
+#define DL35_HPROT_MASK 0x1
+#define DL35_HPROT_MASK_SFT (0x1 << 15)
+#define DL34_HPROT_SFT 14
+#define DL34_HPROT_MASK 0x1
+#define DL34_HPROT_MASK_SFT (0x1 << 14)
+#define DL33_HPROT_SFT 13
+#define DL33_HPROT_MASK 0x1
+#define DL33_HPROT_MASK_SFT (0x1 << 13)
+#define DL32_HPROT_SFT 12
+#define DL32_HPROT_MASK 0x1
+#define DL32_HPROT_MASK_SFT (0x1 << 12)
+#define DL31_HPROT_SFT 11
+#define DL31_HPROT_MASK 0x1
+#define DL31_HPROT_MASK_SFT (0x1 << 11)
+#define DL30_HPROT_SFT 10
+#define DL30_HPROT_MASK 0x1
+#define DL30_HPROT_MASK_SFT (0x1 << 10)
+#define DL29_HPROT_SFT 9
+#define DL29_HPROT_MASK 0x1
+#define DL29_HPROT_MASK_SFT (0x1 << 9)
+#define DL28_HPROT_SFT 8
+#define DL28_HPROT_MASK 0x1
+#define DL28_HPROT_MASK_SFT (0x1 << 8)
+#define DL27_HPROT_SFT 7
+#define DL27_HPROT_MASK 0x1
+#define DL27_HPROT_MASK_SFT (0x1 << 7)
+#define DL26_HPROT_SFT 6
+#define DL26_HPROT_MASK 0x1
+#define DL26_HPROT_MASK_SFT (0x1 << 6)
+#define DL25_HPROT_SFT 5
+#define DL25_HPROT_MASK 0x1
+#define DL25_HPROT_MASK_SFT (0x1 << 5)
+#define DL24_HPROT_SFT 4
+#define DL24_HPROT_MASK 0x1
+#define DL24_HPROT_MASK_SFT (0x1 << 4)
+#define DL23_HPROT_SFT 3
+#define DL23_HPROT_MASK 0x1
+#define DL23_HPROT_MASK_SFT (0x1 << 3)
+#define DL_48CH_PROT_SFT 2
+#define DL_48CH_PROT_MASK 0x1
+#define DL_48CH_PROT_MASK_SFT (0x1 << 2)
+#define DL_24CH_PROT_SFT 1
+#define DL_24CH_PROT_MASK 0x1
+#define DL_24CH_PROT_MASK_SFT (0x1 << 1)
+#define DL_4CH_PROT_SFT 0
+#define DL_4CH_PROT_MASK 0x1
+#define DL_4CH_PROT_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_PROT_SIDEBAND2 */
+#define VUL38_HPROT_SFT 28
+#define VUL38_HPROT_MASK 0x1
+#define VUL38_HPROT_MASK_SFT (0x1 << 28)
+#define VUL37_HPROT_SFT 27
+#define VUL37_HPROT_MASK 0x1
+#define VUL37_HPROT_MASK_SFT (0x1 << 27)
+#define VUL36_HPROT_SFT 26
+#define VUL36_HPROT_MASK 0x1
+#define VUL36_HPROT_MASK_SFT (0x1 << 26)
+#define VUL35_HPROT_SFT 25
+#define VUL35_HPROT_MASK 0x1
+#define VUL35_HPROT_MASK_SFT (0x1 << 25)
+#define VUL34_HPROT_SFT 24
+#define VUL34_HPROT_MASK 0x1
+#define VUL34_HPROT_MASK_SFT (0x1 << 24)
+#define VUL33_HPROT_SFT 23
+#define VUL33_HPROT_MASK 0x1
+#define VUL33_HPROT_MASK_SFT (0x1 << 23)
+#define VUL32_HPROT_SFT 22
+#define VUL32_HPROT_MASK 0x1
+#define VUL32_HPROT_MASK_SFT (0x1 << 22)
+#define VUL31_HPROT_SFT 21
+#define VUL31_HPROT_MASK 0x1
+#define VUL31_HPROT_MASK_SFT (0x1 << 21)
+#define VUL30_HPROT_SFT 20
+#define VUL30_HPROT_MASK 0x1
+#define VUL30_HPROT_MASK_SFT (0x1 << 20)
+#define VUL29_HPROT_SFT 19
+#define VUL29_HPROT_MASK 0x1
+#define VUL29_HPROT_MASK_SFT (0x1 << 19)
+#define VUL28_HPROT_SFT 18
+#define VUL28_HPROT_MASK 0x1
+#define VUL28_HPROT_MASK_SFT (0x1 << 18)
+#define VUL27_HPROT_SFT 17
+#define VUL27_HPROT_MASK 0x1
+#define VUL27_HPROT_MASK_SFT (0x1 << 17)
+#define VUL26_HPROT_SFT 16
+#define VUL26_HPROT_MASK 0x1
+#define VUL26_HPROT_MASK_SFT (0x1 << 16)
+#define VUL25_HPROT_SFT 15
+#define VUL25_HPROT_MASK 0x1
+#define VUL25_HPROT_MASK_SFT (0x1 << 15)
+#define VUL24_HPROT_SFT 14
+#define VUL24_HPROT_MASK 0x1
+#define VUL24_HPROT_MASK_SFT (0x1 << 14)
+#define VUL_CM2_HPROT_SFT 13
+#define VUL_CM2_HPROT_MASK 0x1
+#define VUL_CM2_HPROT_MASK_SFT (0x1 << 13)
+#define VUL_CM1_HPROT_SFT 12
+#define VUL_CM1_HPROT_MASK 0x1
+#define VUL_CM1_HPROT_MASK_SFT (0x1 << 12)
+#define VUL_CM0_HPROT_SFT 11
+#define VUL_CM0_HPROT_MASK 0x1
+#define VUL_CM0_HPROT_MASK_SFT (0x1 << 11)
+#define VUL10_HPROT_SFT 10
+#define VUL10_HPROT_MASK 0x1
+#define VUL10_HPROT_MASK_SFT (0x1 << 10)
+#define VUL9_HPROT_SFT 9
+#define VUL9_HPROT_MASK 0x1
+#define VUL9_HPROT_MASK_SFT (0x1 << 9)
+#define VUL8_HPROT_SFT 8
+#define VUL8_HPROT_MASK 0x1
+#define VUL8_HPROT_MASK_SFT (0x1 << 8)
+#define VUL7_HPROT_SFT 7
+#define VUL7_HPROT_MASK 0x1
+#define VUL7_HPROT_MASK_SFT (0x1 << 7)
+#define VUL6_HPROT_SFT 6
+#define VUL6_HPROT_MASK 0x1
+#define VUL6_HPROT_MASK_SFT (0x1 << 6)
+#define VUL5_HPROT_SFT 5
+#define VUL5_HPROT_MASK 0x1
+#define VUL5_HPROT_MASK_SFT (0x1 << 5)
+#define VUL4_HPROT_SFT 4
+#define VUL4_HPROT_MASK 0x1
+#define VUL4_HPROT_MASK_SFT (0x1 << 4)
+#define VUL3_HPROT_SFT 3
+#define VUL3_HPROT_MASK 0x1
+#define VUL3_HPROT_MASK_SFT (0x1 << 3)
+#define VUL2_HPROT_SFT 2
+#define VUL2_HPROT_MASK 0x1
+#define VUL2_HPROT_MASK_SFT (0x1 << 2)
+#define VUL1_HPROT_SFT 1
+#define VUL1_HPROT_MASK 0x1
+#define VUL1_HPROT_MASK_SFT (0x1 << 1)
+#define VUL0_HPROT_SFT 0
+#define VUL0_HPROT_MASK 0x1
+#define VUL0_HPROT_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_PROT_SIDEBAND3 */
+#define MPHONE_EARC_HPROT_SFT 10
+#define MPHONE_EARC_HPROT_MASK 0x1
+#define MPHONE_EARC_HPROT_MASK_SFT (0x1 << 10)
+#define MPHONE_SPDIF_HPROT_SFT 9
+#define MPHONE_SPDIF_HPROT_MASK 0x1
+#define MPHONE_SPDIF_HPROT_MASK_SFT (0x1 << 9)
+#define SPDIFIN_HPROT_SFT 8
+#define SPDIFIN_HPROT_MASK 0x1
+#define SPDIFIN_HPROT_MASK_SFT (0x1 << 8)
+#define TDMIN_HPROT_SFT 7
+#define TDMIN_HPROT_MASK 0x1
+#define TDMIN_HPROT_MASK_SFT (0x1 << 7)
+#define ETDM_IN1_HPROT_SFT 1
+#define ETDM_IN1_HPROT_MASK 0x1
+#define ETDM_IN1_HPROT_MASK_SFT (0x1 << 1)
+#define ETDM_IN0_HPROT_SFT 0
+#define ETDM_IN0_HPROT_MASK 0x1
+#define ETDM_IN0_HPROT_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND0 */
+#define DL7_HDOMAIN_SFT 28
+#define DL7_HDOMAIN_MASK 0xf
+#define DL7_HDOMAIN_MASK_SFT (0xf << 28)
+#define DL6_HDOMAIN_SFT 24
+#define DL6_HDOMAIN_MASK 0xf
+#define DL6_HDOMAIN_MASK_SFT (0xf << 24)
+#define DL5_HDOMAIN_SFT 20
+#define DL5_HDOMAIN_MASK 0xf
+#define DL5_HDOMAIN_MASK_SFT (0xf << 20)
+#define DL4_HDOMAIN_SFT 16
+#define DL4_HDOMAIN_MASK 0xf
+#define DL4_HDOMAIN_MASK_SFT (0xf << 16)
+#define DL3_HDOMAIN_SFT 12
+#define DL3_HDOMAIN_MASK 0xf
+#define DL3_HDOMAIN_MASK_SFT (0xf << 12)
+#define DL2_HDOMAIN_SFT 8
+#define DL2_HDOMAIN_MASK 0xf
+#define DL2_HDOMAIN_MASK_SFT (0xf << 8)
+#define DL1_HDOMAIN_SFT 4
+#define DL1_HDOMAIN_MASK 0xf
+#define DL1_HDOMAIN_MASK_SFT (0xf << 4)
+#define DL0_HDOMAIN_SFT 0
+#define DL0_HDOMAIN_MASK 0xf
+#define DL0_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND1 */
+#define DL_48CH_HDOMAIN_SFT 24
+#define DL_48CH_HDOMAIN_MASK 0xf
+#define DL_48CH_HDOMAIN_MASK_SFT (0xf << 24)
+#define DL_24CH_HDOMAIN_SFT 20
+#define DL_24CH_HDOMAIN_MASK 0xf
+#define DL_24CH_HDOMAIN_MASK_SFT (0xf << 20)
+#define DL_4CH_HDOMAIN_SFT 16
+#define DL_4CH_HDOMAIN_MASK 0xf
+#define DL_4CH_HDOMAIN_MASK_SFT (0xf << 16)
+#define HDMI_HDOMAIN_SFT 12
+#define HDMI_HDOMAIN_MASK 0xf
+#define HDMI_HDOMAIN_MASK_SFT (0xf << 12)
+#define SPDIF2_OUT_HDOMAIN_SFT 8
+#define SPDIF2_OUT_HDOMAIN_MASK 0xf
+#define SPDIF2_OUT_HDOMAIN_MASK_SFT (0xf << 8)
+#define SPDIF_OUT_HDOMAIN_SFT 4
+#define SPDIF_OUT_HDOMAIN_MASK 0xf
+#define SPDIF_OUT_HDOMAIN_MASK_SFT (0xf << 4)
+#define DL8_HDOMAIN_SFT 0
+#define DL8_HDOMAIN_MASK 0xf
+#define DL8_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND2 */
+#define DL30_HDOMAIN_SFT 28
+#define DL30_HDOMAIN_MASK 0xf
+#define DL30_HDOMAIN_MASK_SFT (0xf << 28)
+#define DL29_HDOMAIN_SFT 24
+#define DL29_HDOMAIN_MASK 0xf
+#define DL29_HDOMAIN_MASK_SFT (0xf << 24)
+#define DL28_HDOMAIN_SFT 20
+#define DL28_HDOMAIN_MASK 0xf
+#define DL28_HDOMAIN_MASK_SFT (0xf << 20)
+#define DL27_HDOMAIN_SFT 16
+#define DL27_HDOMAIN_MASK 0xf
+#define DL27_HDOMAIN_MASK_SFT (0xf << 16)
+#define DL26_HDOMAIN_SFT 12
+#define DL26_HDOMAIN_MASK 0xf
+#define DL26_HDOMAIN_MASK_SFT (0xf << 12)
+#define DL25_HDOMAIN_SFT 8
+#define DL25_HDOMAIN_MASK 0xf
+#define DL25_HDOMAIN_MASK_SFT (0xf << 8)
+#define DL24_HDOMAIN_SFT 4
+#define DL24_HDOMAIN_MASK 0xf
+#define DL24_HDOMAIN_MASK_SFT (0xf << 4)
+#define DL23_HDOMAIN_SFT 0
+#define DL23_HDOMAIN_MASK 0xf
+#define DL23_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND3 */
+#define DL38_HDOMAIN_SFT 28
+#define DL38_HDOMAIN_MASK 0xf
+#define DL38_HDOMAIN_MASK_SFT (0xf << 28)
+#define DL37_HDOMAIN_SFT 24
+#define DL37_HDOMAIN_MASK 0xf
+#define DL37_HDOMAIN_MASK_SFT (0xf << 24)
+#define DL36_HDOMAIN_SFT 20
+#define DL36_HDOMAIN_MASK 0xf
+#define DL36_HDOMAIN_MASK_SFT (0xf << 20)
+#define DL35_HDOMAIN_SFT 16
+#define DL35_HDOMAIN_MASK 0xf
+#define DL35_HDOMAIN_MASK_SFT (0xf << 16)
+#define DL34_HDOMAIN_SFT 12
+#define DL34_HDOMAIN_MASK 0xf
+#define DL34_HDOMAIN_MASK_SFT (0xf << 12)
+#define DL33_HDOMAIN_SFT 8
+#define DL33_HDOMAIN_MASK 0xf
+#define DL33_HDOMAIN_MASK_SFT (0xf << 8)
+#define DL32_HDOMAIN_SFT 4
+#define DL32_HDOMAIN_MASK 0xf
+#define DL32_HDOMAIN_MASK_SFT (0xf << 4)
+#define DL31_HDOMAIN_SFT 0
+#define DL31_HDOMAIN_MASK 0xf
+#define DL31_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND4 */
+#define DL46_HDOMAIN_SFT 28
+#define DL46_HDOMAIN_MASK 0xf
+#define DL46_HDOMAIN_MASK_SFT (0xf << 28)
+#define DL45_HDOMAIN_SFT 24
+#define DL45_HDOMAIN_MASK 0xf
+#define DL45_HDOMAIN_MASK_SFT (0xf << 24)
+#define DL44_HDOMAIN_SFT 20
+#define DL44_HDOMAIN_MASK 0xf
+#define DL44_HDOMAIN_MASK_SFT (0xf << 20)
+#define DL43_HDOMAIN_SFT 16
+#define DL43_HDOMAIN_MASK 0xf
+#define DL43_HDOMAIN_MASK_SFT (0xf << 16)
+#define DL42_HDOMAIN_SFT 12
+#define DL42_HDOMAIN_MASK 0xf
+#define DL42_HDOMAIN_MASK_SFT (0xf << 12)
+#define DL41_HDOMAIN_SFT 8
+#define DL41_HDOMAIN_MASK 0xf
+#define DL41_HDOMAIN_MASK_SFT (0xf << 8)
+#define DL40_HDOMAIN_SFT 4
+#define DL40_HDOMAIN_MASK 0xf
+#define DL40_HDOMAIN_MASK_SFT (0xf << 4)
+#define DL39_HDOMAIN_SFT 0
+#define DL39_HDOMAIN_MASK 0xf
+#define DL39_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND5 */
+#define VUL7_HDOMAIN_SFT 28
+#define VUL7_HDOMAIN_MASK 0xf
+#define VUL7_HDOMAIN_MASK_SFT (0xf << 28)
+#define VUL6_HDOMAIN_SFT 24
+#define VUL6_HDOMAIN_MASK 0xf
+#define VUL6_HDOMAIN_MASK_SFT (0xf << 24)
+#define VUL5_HDOMAIN_SFT 20
+#define VUL5_HDOMAIN_MASK 0xf
+#define VUL5_HDOMAIN_MASK_SFT (0xf << 20)
+#define VUL4_HDOMAIN_SFT 16
+#define VUL4_HDOMAIN_MASK 0xf
+#define VUL4_HDOMAIN_MASK_SFT (0xf << 16)
+#define VUL3_HDOMAIN_SFT 12
+#define VUL3_HDOMAIN_MASK 0xf
+#define VUL3_HDOMAIN_MASK_SFT (0xf << 12)
+#define VUL2_HDOMAIN_SFT 8
+#define VUL2_HDOMAIN_MASK 0xf
+#define VUL2_HDOMAIN_MASK_SFT (0xf << 8)
+#define VUL1_HDOMAIN_SFT 4
+#define VUL1_HDOMAIN_MASK 0xf
+#define VUL1_HDOMAIN_MASK_SFT (0xf << 4)
+#define VUL0_HDOMAIN_SFT 0
+#define VUL0_HDOMAIN_MASK 0xf
+#define VUL0_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND6 */
+#define VU25_HDOMAIN_SFT 28
+#define VU25_HDOMAIN_MASK 0xf
+#define VU25_HDOMAIN_MASK_SFT (0xf << 28)
+#define VUL24_HDOMAIN_SFT 24
+#define VUL24_HDOMAIN_MASK 0xf
+#define VUL24_HDOMAIN_MASK_SFT (0xf << 24)
+#define VUL_CM2_HDOMAIN_SFT 20
+#define VUL_CM2_HDOMAIN_MASK 0xf
+#define VUL_CM2_HDOMAIN_MASK_SFT (0xf << 20)
+#define VUL_CM1_HDOMAIN_SFT 16
+#define VUL_CM1_HDOMAIN_MASK 0xf
+#define VUL_CM1_HDOMAIN_MASK_SFT (0xf << 16)
+#define VUL_CM0_HDOMAIN_SFT 12
+#define VUL_CM0_HDOMAIN_MASK 0xf
+#define VUL_CM0_HDOMAIN_MASK_SFT (0xf << 12)
+#define VUL10_HDOMAIN_SFT 8
+#define VUL10_HDOMAIN_MASK 0xf
+#define VUL10_HDOMAIN_MASK_SFT (0xf << 8)
+#define VUL9_HDOMAIN_SFT 4
+#define VUL9_HDOMAIN_MASK 0xf
+#define VUL9_HDOMAIN_MASK_SFT (0xf << 4)
+#define VUL8_HDOMAIN_SFT 0
+#define VUL8_HDOMAIN_MASK 0xf
+#define VUL8_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND7 */
+#define VUL33_HDOMAIN_SFT 28
+#define VUL33_HDOMAIN_MASK 0xf
+#define VUL33_HDOMAIN_MASK_SFT (0xf << 28)
+#define VUL32_HDOMAIN_SFT 24
+#define VUL32_HDOMAIN_MASK 0xf
+#define VUL32_HDOMAIN_MASK_SFT (0xf << 24)
+#define VUL31_HDOMAIN_SFT 20
+#define VUL31_HDOMAIN_MASK 0xf
+#define VUL31_HDOMAIN_MASK_SFT (0xf << 20)
+#define VUL30_HDOMAIN_SFT 16
+#define VUL30_HDOMAIN_MASK 0xf
+#define VUL30_HDOMAIN_MASK_SFT (0xf << 16)
+#define VUL29_HDOMAIN_SFT 12
+#define VUL29_HDOMAIN_MASK 0xf
+#define VUL29_HDOMAIN_MASK_SFT (0xf << 12)
+#define VUL28_HDOMAIN_SFT 8
+#define VUL28_HDOMAIN_MASK 0xf
+#define VUL28_HDOMAIN_MASK_SFT (0xf << 8)
+#define VUL27_HDOMAIN_SFT 4
+#define VUL27_HDOMAIN_MASK 0xf
+#define VUL27_HDOMAIN_MASK_SFT (0xf << 4)
+#define VUL26_HDOMAIN_SFT 0
+#define VUL26_HDOMAIN_MASK 0xf
+#define VUL26_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND8 */
+#define ETDM_IN1_HDOMAIN_SFT 24
+#define ETDM_IN1_HDOMAIN_MASK 0xf
+#define ETDM_IN1_HDOMAIN_MASK_SFT (0xf << 24)
+#define ETDM_IN0_HDOMAIN_SFT 20
+#define ETDM_IN0_HDOMAIN_MASK 0xf
+#define ETDM_IN0_HDOMAIN_MASK_SFT (0xf << 20)
+#define VUL38_HDOMAIN_SFT 16
+#define VUL38_HDOMAIN_MASK 0xf
+#define VUL38_HDOMAIN_MASK_SFT (0xf << 16)
+#define VUL37_HDOMAIN_SFT 12
+#define VUL37_HDOMAIN_MASK 0xf
+#define VUL37_HDOMAIN_MASK_SFT (0xf << 12)
+#define VUL36_HDOMAIN_SFT 8
+#define VUL36_HDOMAIN_MASK 0xf
+#define VUL36_HDOMAIN_MASK_SFT (0xf << 8)
+#define VUL35_HDOMAIN_SFT 4
+#define VUL35_HDOMAIN_MASK 0xf
+#define VUL35_HDOMAIN_MASK_SFT (0xf << 4)
+#define VUL34_HDOMAIN_SFT 0
+#define VUL34_HDOMAIN_MASK 0xf
+#define VUL34_HDOMAIN_MASK_SFT (0xf << 0)
+
+/* AFE_SE_DOMAIN_SIDEBAND9 */
+#define MPHONE_EARC_HDOMAIN_SFT 28
+#define MPHONE_EARC_HDOMAIN_MASK 0xf
+#define MPHONE_EARC_HDOMAIN_MASK_SFT (0xf << 28)
+#define MPHONE_SPDIF_HDOMAIN_SFT 24
+#define MPHONE_SPDIF_HDOMAIN_MASK 0xf
+#define MPHONE_SPDIF_HDOMAIN_MASK_SFT (0xf << 24)
+#define SPDIFIN_HDOMAIN_SFT 20
+#define SPDIFIN_HDOMAIN_MASK 0xf
+#define SPDIFIN_HDOMAIN_MASK_SFT (0xf << 20)
+#define TDMIN_HDOMAIN_SFT 16
+#define TDMIN_HDOMAIN_MASK 0xf
+#define TDMIN_HDOMAIN_MASK_SFT (0xf << 16)
+
+/* AFE_PROT_SIDEBAND0_MON */
+#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_PROT_SIDEBAND1_MON */
+#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_PROT_SIDEBAND2_MON */
+#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_PROT_SIDEBAND3_MON */
+#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND0_MON */
+#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND1_MON */
+#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND2_MON */
+#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND3_MON */
+#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND4_MON */
+#define AFE_DOMAIN_SIDEBAN0_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN0_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND5_MON */
+#define AFE_DOMAIN_SIDEBAN1_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN1_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND6_MON */
+#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND7_MON */
+#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND8_MON */
+#define AFE_DOMAIN_SIDEBAN2_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN2_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_DOMAIN_SIDEBAND9_MON */
+#define AFE_DOMAIN_SIDEBAN3_MON_SFT 0
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK 0xffffffff
+#define AFE_DOMAIN_SIDEBAN3_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SECURE_CONN0 */
+#define AFE_SPDIFIN_LPBK_CON_MASK_S_SFT 26
+#define AFE_SPDIFIN_LPBK_CON_MASK_S_MASK 0x3
+#define AFE_SPDIFIN_LPBK_CON_MASK_S_MASK_SFT (0x3 << 26)
+#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_SFT 25
+#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_MASK 0x1
+#define AFE_ADDA_DMIC1_SRC_CON0_MASK_S_MASK_SFT (0x1 << 25)
+#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_SFT 24
+#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_MASK 0x1
+#define AFE_ADDA_DMIC0_SRC_CON0_MASK_S_MASK_SFT (0x1 << 24)
+#define AFE_ADDA_UL3_SRC_CON0_MASK_S_SFT 23
+#define AFE_ADDA_UL3_SRC_CON0_MASK_S_MASK 0x1
+#define AFE_ADDA_UL3_SRC_CON0_MASK_S_MASK_SFT (0x1 << 23)
+#define AFE_ADDA_UL2_SRC_CON0_MASK_S_SFT 22
+#define AFE_ADDA_UL2_SRC_CON0_MASK_S_MASK 0x1
+#define AFE_ADDA_UL2_SRC_CON0_MASK_S_MASK_SFT (0x1 << 22)
+#define AFE_ADDA_UL1_SRC_CON0_MASK_S_SFT 21
+#define AFE_ADDA_UL1_SRC_CON0_MASK_S_MASK 0x1
+#define AFE_ADDA_UL1_SRC_CON0_MASK_S_MASK_SFT (0x1 << 21)
+#define AFE_ADDA_UL0_SRC_CON0_MASK_S_SFT 20
+#define AFE_ADDA_UL0_SRC_CON0_MASK_S_MASK 0x1
+#define AFE_ADDA_UL0_SRC_CON0_MASK_S_MASK_SFT (0x1 << 20)
+#define AFE_MRKAIF1_CFG0_MASK_S_SFT 19
+#define AFE_MRKAIF1_CFG0_MASK_S_MASK 0x1
+#define AFE_MRKAIF1_CFG0_MASK_S_MASK_SFT (0x1 << 19)
+#define AFE_MRKAIF0_CFG0_MASK_S_SFT 18
+#define AFE_MRKAIF0_CFG0_MASK_S_MASK 0x1
+#define AFE_MRKAIF0_CFG0_MASK_S_MASK_SFT (0x1 << 18)
+#define AFE_TDMIN_CON1_MASK_S_SFT 17
+#define AFE_TDMIN_CON1_MASK_S_MASK 0x1
+#define AFE_TDMIN_CON1_MASK_S_MASK_SFT (0x1 << 17)
+#define AFE_TDM_CON2_MASK_S_SFT 16
+#define AFE_TDM_CON2_MASK_S_MASK 0x1
+#define AFE_TDM_CON2_MASK_S_MASK_SFT (0x1 << 16)
+#define AFE_DAIBT_CON_MASK_S_SFT 14
+#define AFE_DAIBT_CON_MASK_S_MASK 0x3
+#define AFE_DAIBT_CON_MASK_S_MASK_SFT (0x3 << 14)
+#define AFE_MRGIF_CON_MASK_S_SFT 12
+#define AFE_MRGIF_CON_MASK_S_MASK 0x3
+#define AFE_MRGIF_CON_MASK_S_MASK_SFT (0x3 << 12)
+#define AFE_CONNSYS_I2S_CON_MASK_S_SFT 11
+#define AFE_CONNSYS_I2S_CON_MASK_S_MASK 0x1
+#define AFE_CONNSYS_I2S_CON_MASK_S_MASK_SFT (0x1 << 11)
+#define AFE_PCM1_INFT_CON0_MASK_S_SFT 6
+#define AFE_PCM1_INFT_CON0_MASK_S_MASK 0x1f
+#define AFE_PCM1_INFT_CON0_MASK_S_MASK_SFT (0x1f << 6)
+#define AFE_PCM0_INTF_CON1_MASK_S_SFT 0
+#define AFE_PCM0_INTF_CON1_MASK_S_MASK 0x3f
+#define AFE_PCM0_INTF_CON1_MASK_S_MASK_SFT (0x3f << 0)
+
+/* AFE_SECURE_CONN_ETDM1 */
+#define ETDM1_4_7_COWORK_CON1_MASK_S_0_SFT 24
+#define ETDM1_4_7_COWORK_CON1_MASK_S_0_MASK 0xff
+#define ETDM1_4_7_COWORK_CON1_MASK_S_0_MASK_SFT (0xff << 24)
+#define ETDM1_4_7_COWORK_CON0_MASK_S_0_SFT 20
+#define ETDM1_4_7_COWORK_CON0_MASK_S_0_MASK 0xf
+#define ETDM1_4_7_COWORK_CON0_MASK_S_0_MASK_SFT (0xf << 20)
+#define ETDM1_4_7_COWORK_CON0_MASK_S_1_SFT 16
+#define ETDM1_4_7_COWORK_CON0_MASK_S_1_MASK 0xf
+#define ETDM1_4_7_COWORK_CON0_MASK_S_1_MASK_SFT (0xf << 16)
+#define ETDM1_0_3_COWORK_CON3_MASK_S_0_SFT 8
+#define ETDM1_0_3_COWORK_CON3_MASK_S_0_MASK 0xff
+#define ETDM1_0_3_COWORK_CON3_MASK_S_0_MASK_SFT (0xff << 8)
+#define ETDM1_0_3_COWORK_CON3_MASK_S_1_SFT 0
+#define ETDM1_0_3_COWORK_CON3_MASK_S_1_MASK 0xff
+#define ETDM1_0_3_COWORK_CON3_MASK_S_1_MASK_SFT (0xff << 0)
+
+/* AFE_SECURE_CONN_ETDM2 */
+#define ETDM2_4_7_COWORK_CON3_MASK_S_0_SFT 24
+#define ETDM2_4_7_COWORK_CON3_MASK_S_0_MASK 0xff
+#define ETDM2_4_7_COWORK_CON3_MASK_S_0_MASK_SFT (0xff << 24)
+#define ETDM2_4_7_COWORK_CON3_MASK_S_1_SFT 16
+#define ETDM2_4_7_COWORK_CON3_MASK_S_1_MASK 0xff
+#define ETDM2_4_7_COWORK_CON3_MASK_S_1_MASK_SFT (0xff << 16)
+#define ETDM2_4_7_COWORK_CON2_MASK_S_0_SFT 12
+#define ETDM2_4_7_COWORK_CON2_MASK_S_0_MASK 0xf
+#define ETDM2_4_7_COWORK_CON2_MASK_S_0_MASK_SFT (0xf << 12)
+#define ETDM2_4_7_COWORK_CON2_MASK_S_1_SFT 8
+#define ETDM2_4_7_COWORK_CON2_MASK_S_1_MASK 0xf
+#define ETDM2_4_7_COWORK_CON2_MASK_S_1_MASK_SFT (0xf << 8)
+#define ETDM2_4_7_COWORK_CON1_MASK_S_0_SFT 0
+#define ETDM2_4_7_COWORK_CON1_MASK_S_0_MASK 0xff
+#define ETDM2_4_7_COWORK_CON1_MASK_S_0_MASK_SFT (0xff << 0)
+
+/* AFE_SECURE_SRAM_CON0 */
+#define SRAM_READ_EN15_NS_SFT 31
+#define SRAM_READ_EN15_NS_MASK 0x1
+#define SRAM_READ_EN15_NS_MASK_SFT (0x1 << 31)
+#define SRAM_WRITE_EN15_NS_SFT 30
+#define SRAM_WRITE_EN15_NS_MASK 0x1
+#define SRAM_WRITE_EN15_NS_MASK_SFT (0x1 << 30)
+#define SRAM_READ_EN14_NS_SFT 29
+#define SRAM_READ_EN14_NS_MASK 0x1
+#define SRAM_READ_EN14_NS_MASK_SFT (0x1 << 29)
+#define SRAM_WRITE_EN14_NS_SFT 28
+#define SRAM_WRITE_EN14_NS_MASK 0x1
+#define SRAM_WRITE_EN14_NS_MASK_SFT (0x1 << 28)
+#define SRAM_READ_EN13_NS_SFT 27
+#define SRAM_READ_EN13_NS_MASK 0x1
+#define SRAM_READ_EN13_NS_MASK_SFT (0x1 << 27)
+#define SRAM_WRITE_EN13_NS_SFT 26
+#define SRAM_WRITE_EN13_NS_MASK 0x1
+#define SRAM_WRITE_EN13_NS_MASK_SFT (0x1 << 26)
+#define SRAM_READ_EN12_NS_SFT 25
+#define SRAM_READ_EN12_NS_MASK 0x1
+#define SRAM_READ_EN12_NS_MASK_SFT (0x1 << 25)
+#define SRAM_WRITE_EN12_NS_SFT 24
+#define SRAM_WRITE_EN12_NS_MASK 0x1
+#define SRAM_WRITE_EN12_NS_MASK_SFT (0x1 << 24)
+#define SRAM_READ_EN11_NS_SFT 23
+#define SRAM_READ_EN11_NS_MASK 0x1
+#define SRAM_READ_EN11_NS_MASK_SFT (0x1 << 23)
+#define SRAM_WRITE_EN11_NS_SFT 22
+#define SRAM_WRITE_EN11_NS_MASK 0x1
+#define SRAM_WRITE_EN11_NS_MASK_SFT (0x1 << 22)
+#define SRAM_READ_EN10_NS_SFT 21
+#define SRAM_READ_EN10_NS_MASK 0x1
+#define SRAM_READ_EN10_NS_MASK_SFT (0x1 << 21)
+#define SRAM_WRITE_EN10_NS_SFT 20
+#define SRAM_WRITE_EN10_NS_MASK 0x1
+#define SRAM_WRITE_EN10_NS_MASK_SFT (0x1 << 20)
+#define SRAM_READ_EN9_NS_SFT 19
+#define SRAM_READ_EN9_NS_MASK 0x1
+#define SRAM_READ_EN9_NS_MASK_SFT (0x1 << 19)
+#define SRAM_WRITE_EN9_NS_SFT 18
+#define SRAM_WRITE_EN9_NS_MASK 0x1
+#define SRAM_WRITE_EN9_NS_MASK_SFT (0x1 << 18)
+#define SRAM_READ_EN8_NS_SFT 17
+#define SRAM_READ_EN8_NS_MASK 0x1
+#define SRAM_READ_EN8_NS_MASK_SFT (0x1 << 17)
+#define SRAM_WRITE_EN8_NS_SFT 16
+#define SRAM_WRITE_EN8_NS_MASK 0x1
+#define SRAM_WRITE_EN8_NS_MASK_SFT (0x1 << 16)
+#define SRAM_READ_EN7_NS_SFT 15
+#define SRAM_READ_EN7_NS_MASK 0x1
+#define SRAM_READ_EN7_NS_MASK_SFT (0x1 << 15)
+#define SRAM_WRITE_EN7_NS_SFT 14
+#define SRAM_WRITE_EN7_NS_MASK 0x1
+#define SRAM_WRITE_EN7_NS_MASK_SFT (0x1 << 14)
+#define SRAM_READ_EN6_NS_SFT 13
+#define SRAM_READ_EN6_NS_MASK 0x1
+#define SRAM_READ_EN6_NS_MASK_SFT (0x1 << 13)
+#define SRAM_WRITE_EN6_NS_SFT 12
+#define SRAM_WRITE_EN6_NS_MASK 0x1
+#define SRAM_WRITE_EN6_NS_MASK_SFT (0x1 << 12)
+#define SRAM_READ_EN5_NS_SFT 11
+#define SRAM_READ_EN5_NS_MASK 0x1
+#define SRAM_READ_EN5_NS_MASK_SFT (0x1 << 11)
+#define SRAM_WRITE_EN5_NS_SFT 10
+#define SRAM_WRITE_EN5_NS_MASK 0x1
+#define SRAM_WRITE_EN5_NS_MASK_SFT (0x1 << 10)
+#define SRAM_READ_EN4_NS_SFT 9
+#define SRAM_READ_EN4_NS_MASK 0x1
+#define SRAM_READ_EN4_NS_MASK_SFT (0x1 << 9)
+#define SRAM_WRITE_EN4_NS_SFT 8
+#define SRAM_WRITE_EN4_NS_MASK 0x1
+#define SRAM_WRITE_EN4_NS_MASK_SFT (0x1 << 8)
+#define SRAM_READ_EN3_NS_SFT 7
+#define SRAM_READ_EN3_NS_MASK 0x1
+#define SRAM_READ_EN3_NS_MASK_SFT (0x1 << 7)
+#define SRAM_WRITE_EN3_NS_SFT 6
+#define SRAM_WRITE_EN3_NS_MASK 0x1
+#define SRAM_WRITE_EN3_NS_MASK_SFT (0x1 << 6)
+#define SRAM_READ_EN2_NS_SFT 5
+#define SRAM_READ_EN2_NS_MASK 0x1
+#define SRAM_READ_EN2_NS_MASK_SFT (0x1 << 5)
+#define SRAM_WRITE_EN2_NS_SFT 4
+#define SRAM_WRITE_EN2_NS_MASK 0x1
+#define SRAM_WRITE_EN2_NS_MASK_SFT (0x1 << 4)
+#define SRAM_READ_EN1_NS_SFT 3
+#define SRAM_READ_EN1_NS_MASK 0x1
+#define SRAM_READ_EN1_NS_MASK_SFT (0x1 << 3)
+#define SRAM_WRITE_EN1_NS_SFT 2
+#define SRAM_WRITE_EN1_NS_MASK 0x1
+#define SRAM_WRITE_EN1_NS_MASK_SFT (0x1 << 2)
+#define SRAM_READ_EN0_NS_SFT 1
+#define SRAM_READ_EN0_NS_MASK 0x1
+#define SRAM_READ_EN0_NS_MASK_SFT (0x1 << 1)
+#define SRAM_WRITE_EN0_NS_SFT 0
+#define SRAM_WRITE_EN0_NS_MASK 0x1
+#define SRAM_WRITE_EN0_NS_MASK_SFT (0x1 << 0)
+
+/* AFE_SECURE_SRAM_CON1 */
+#define SRAM_READ_EN15_S_SFT 31
+#define SRAM_READ_EN15_S_MASK 0x1
+#define SRAM_READ_EN15_S_MASK_SFT (0x1 << 31)
+#define SRAM_WRITE_EN15_S_SFT 30
+#define SRAM_WRITE_EN15_S_MASK 0x1
+#define SRAM_WRITE_EN15_S_MASK_SFT (0x1 << 30)
+#define SRAM_READ_EN14_S_SFT 29
+#define SRAM_READ_EN14_S_MASK 0x1
+#define SRAM_READ_EN14_S_MASK_SFT (0x1 << 29)
+#define SRAM_WRITE_EN14_S_SFT 28
+#define SRAM_WRITE_EN14_S_MASK 0x1
+#define SRAM_WRITE_EN14_S_MASK_SFT (0x1 << 28)
+#define SRAM_READ_EN13_S_SFT 27
+#define SRAM_READ_EN13_S_MASK 0x1
+#define SRAM_READ_EN13_S_MASK_SFT (0x1 << 27)
+#define SRAM_WRITE_EN13_S_SFT 26
+#define SRAM_WRITE_EN13_S_MASK 0x1
+#define SRAM_WRITE_EN13_S_MASK_SFT (0x1 << 26)
+#define SRAM_READ_EN12_S_SFT 25
+#define SRAM_READ_EN12_S_MASK 0x1
+#define SRAM_READ_EN12_S_MASK_SFT (0x1 << 25)
+#define SRAM_WRITE_EN12_S_SFT 24
+#define SRAM_WRITE_EN12_S_MASK 0x1
+#define SRAM_WRITE_EN12_S_MASK_SFT (0x1 << 24)
+#define SRAM_READ_EN11_S_SFT 23
+#define SRAM_READ_EN11_S_MASK 0x1
+#define SRAM_READ_EN11_S_MASK_SFT (0x1 << 23)
+#define SRAM_WRITE_EN11_S_SFT 22
+#define SRAM_WRITE_EN11_S_MASK 0x1
+#define SRAM_WRITE_EN11_S_MASK_SFT (0x1 << 22)
+#define SRAM_READ_EN10_S_SFT 21
+#define SRAM_READ_EN10_S_MASK 0x1
+#define SRAM_READ_EN10_S_MASK_SFT (0x1 << 21)
+#define SRAM_WRITE_EN10_S_SFT 20
+#define SRAM_WRITE_EN10_S_MASK 0x1
+#define SRAM_WRITE_EN10_S_MASK_SFT (0x1 << 20)
+#define SRAM_READ_EN9_S_SFT 19
+#define SRAM_READ_EN9_S_MASK 0x1
+#define SRAM_READ_EN9_S_MASK_SFT (0x1 << 19)
+#define SRAM_WRITE_EN9_S_SFT 18
+#define SRAM_WRITE_EN9_S_MASK 0x1
+#define SRAM_WRITE_EN9_S_MASK_SFT (0x1 << 18)
+#define SRAM_READ_EN8_S_SFT 17
+#define SRAM_READ_EN8_S_MASK 0x1
+#define SRAM_READ_EN8_S_MASK_SFT (0x1 << 17)
+#define SRAM_WRITE_EN8_S_SFT 16
+#define SRAM_WRITE_EN8_S_MASK 0x1
+#define SRAM_WRITE_EN8_S_MASK_SFT (0x1 << 16)
+#define SRAM_READ_EN7_S_SFT 15
+#define SRAM_READ_EN7_S_MASK 0x1
+#define SRAM_READ_EN7_S_MASK_SFT (0x1 << 15)
+#define SRAM_WRITE_EN7_S_SFT 14
+#define SRAM_WRITE_EN7_S_MASK 0x1
+#define SRAM_WRITE_EN7_S_MASK_SFT (0x1 << 14)
+#define SRAM_READ_EN6_S_SFT 13
+#define SRAM_READ_EN6_S_MASK 0x1
+#define SRAM_READ_EN6_S_MASK_SFT (0x1 << 13)
+#define SRAM_WRITE_EN6_S_SFT 12
+#define SRAM_WRITE_EN6_S_MASK 0x1
+#define SRAM_WRITE_EN6_S_MASK_SFT (0x1 << 12)
+#define SRAM_READ_EN5_S_SFT 11
+#define SRAM_READ_EN5_S_MASK 0x1
+#define SRAM_READ_EN5_S_MASK_SFT (0x1 << 11)
+#define SRAM_WRITE_EN5_S_SFT 10
+#define SRAM_WRITE_EN5_S_MASK 0x1
+#define SRAM_WRITE_EN5_S_MASK_SFT (0x1 << 10)
+#define SRAM_READ_EN4_S_SFT 9
+#define SRAM_READ_EN4_S_MASK 0x1
+#define SRAM_READ_EN4_S_MASK_SFT (0x1 << 9)
+#define SRAM_WRITE_EN4_S_SFT 8
+#define SRAM_WRITE_EN4_S_MASK 0x1
+#define SRAM_WRITE_EN4_S_MASK_SFT (0x1 << 8)
+#define SRAM_READ_EN3_S_SFT 7
+#define SRAM_READ_EN3_S_MASK 0x1
+#define SRAM_READ_EN3_S_MASK_SFT (0x1 << 7)
+#define SRAM_WRITE_EN3_S_SFT 6
+#define SRAM_WRITE_EN3_S_MASK 0x1
+#define SRAM_WRITE_EN3_S_MASK_SFT (0x1 << 6)
+#define SRAM_READ_EN2_S_SFT 5
+#define SRAM_READ_EN2_S_MASK 0x1
+#define SRAM_READ_EN2_S_MASK_SFT (0x1 << 5)
+#define SRAM_WRITE_EN2_S_SFT 4
+#define SRAM_WRITE_EN2_S_MASK 0x1
+#define SRAM_WRITE_EN2_S_MASK_SFT (0x1 << 4)
+#define SRAM_READ_EN1_S_SFT 3
+#define SRAM_READ_EN1_S_MASK 0x1
+#define SRAM_READ_EN1_S_MASK_SFT (0x1 << 3)
+#define SRAM_WRITE_EN1_S_SFT 2
+#define SRAM_WRITE_EN1_S_MASK 0x1
+#define SRAM_WRITE_EN1_S_MASK_SFT (0x1 << 2)
+#define SRAM_READ_EN0_S_SFT 1
+#define SRAM_READ_EN0_S_MASK 0x1
+#define SRAM_READ_EN0_S_MASK_SFT (0x1 << 1)
+#define SRAM_WRITE_EN0_S_SFT 0
+#define SRAM_WRITE_EN0_S_MASK 0x1
+#define SRAM_WRITE_EN0_S_MASK_SFT (0x1 << 0)
+
+/* AFE_SE_CONN_INPUT_MASK0 */
+#define SECURE_INTRCONN_I0_I31_S_SFT 0
+#define SECURE_INTRCONN_I0_I31_S_MASK 0xffffffff
+#define SECURE_INTRCONN_I0_I31_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK1 */
+#define SECURE_INTRCONN_I32_I63_S_SFT 0
+#define SECURE_INTRCONN_I32_I63_S_MASK 0xffffffff
+#define SECURE_INTRCONN_I32_I63_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK2 */
+#define SECURE_INTRCONN_I64_I95_S_SFT 0
+#define SECURE_INTRCONN_I64_I95_S_MASK 0xffffffff
+#define SECURE_INTRCONN_I64_I95_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK3 */
+#define SECURE_INTRCONN_I96_I127_S_SFT 0
+#define SECURE_INTRCONN_I96_I127_S_MASK 0xffffffff
+#define SECURE_INTRCONN_I96_I127_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK4 */
+#define SECURE_INTRCONN_I128_I159_S_SFT 0
+#define SECURE_INTRCONN_I128_I159_S_MASK 0xffffffff
+#define SECURE_INTRCONN_I128_I159_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK5 */
+#define SECURE_INTRCONN_I160_I191_S_SFT 0
+#define SECURE_INTRCONN_I160_I191_S_MASK 0xffffffff
+#define SECURE_INTRCONN_I160_I191_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK6 */
+#define SECURE_INTRCONN_I192_I223_S_SFT 0
+#define SECURE_INTRCONN_I192_I223_S_MASK 0xffffffff
+#define SECURE_INTRCONN_I192_I223_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_INPUT_MASK7 */
+#define SECURE_INTRCONN_I224_I256_S_SFT 0
+#define SECURE_INTRCONN_I224_I256_S_MASK 0xffffffff
+#define SECURE_INTRCONN_I224_I256_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK0 */
+#define NORMAL_INTRCONN_I0_I31_S_SFT 0
+#define NORMAL_INTRCONN_I0_I31_S_MASK 0xffffffff
+#define NORMAL_INTRCONN_I0_I31_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK1 */
+#define NORMAL_INTRCONN_I32_I63_S_SFT 0
+#define NORMAL_INTRCONN_I32_I63_S_MASK 0xffffffff
+#define NORMAL_INTRCONN_I32_I63_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK2 */
+#define NORMAL_INTRCONN_I64_I95_S_SFT 0
+#define NORMAL_INTRCONN_I64_I95_S_MASK 0xffffffff
+#define NORMAL_INTRCONN_I64_I95_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK3 */
+#define NORMAL_INTRCONN_I96_I127_S_SFT 0
+#define NORMAL_INTRCONN_I96_I127_S_MASK 0xffffffff
+#define NORMAL_INTRCONN_I96_I127_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK4 */
+#define NORMAL_INTRCONN_I128_I159_S_SFT 0
+#define NORMAL_INTRCONN_I128_I159_S_MASK 0xffffffff
+#define NORMAL_INTRCONN_I128_I159_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK5 */
+#define NORMAL_INTRCONN_I160_I191_S_SFT 0
+#define NORMAL_INTRCONN_I160_I191_S_MASK 0xffffffff
+#define NORMAL_INTRCONN_I160_I191_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK6 */
+#define NORMAL_INTRCONN_I192_I223_S_SFT 0
+#define NORMAL_INTRCONN_I192_I223_S_MASK 0xffffffff
+#define NORMAL_INTRCONN_I192_I223_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_NON_SE_CONN_INPUT_MASK7 */
+#define NORMAL_INTRCONN_I224_I256_S_SFT 0
+#define NORMAL_INTRCONN_I224_I256_S_MASK 0xffffffff
+#define NORMAL_INTRCONN_I224_I256_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL0 */
+#define SECURE_INTRCONN_O0_O31_S_SFT 0
+#define SECURE_INTRCONN_O0_O31_S_MASK 0xffffffff
+#define SECURE_INTRCONN_O0_O31_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL1 */
+#define SECURE_INTRCONN_O32_O63_S_SFT 0
+#define SECURE_INTRCONN_O32_O63_S_MASK 0xffffffff
+#define SECURE_INTRCONN_O32_O63_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL2 */
+#define SECURE_INTRCONN_O64_O95_S_SFT 0
+#define SECURE_INTRCONN_O64_O95_S_MASK 0xffffffff
+#define SECURE_INTRCONN_O64_O95_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL3 */
+#define SECURE_INTRCONN_O96_O127_S_SFT 0
+#define SECURE_INTRCONN_O96_O127_S_MASK 0xffffffff
+#define SECURE_INTRCONN_O96_O127_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL4 */
+#define SECURE_INTRCONN_O128_O159_S_SFT 0
+#define SECURE_INTRCONN_O128_O159_S_MASK 0xffffffff
+#define SECURE_INTRCONN_O128_O159_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL5 */
+#define SECURE_INTRCONN_O160_O191_S_SFT 0
+#define SECURE_INTRCONN_O160_O191_S_MASK 0xffffffff
+#define SECURE_INTRCONN_O160_O191_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL6 */
+#define SECURE_INTRCONN_O192_O223_S_SFT 0
+#define SECURE_INTRCONN_O192_O223_S_MASK 0xffffffff
+#define SECURE_INTRCONN_O192_O223_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_SE_CONN_OUTPUT_SEL7 */
+#define SECURE_INTRCONN_O224_O256_S_SFT 0
+#define SECURE_INTRCONN_O224_O256_S_MASK 0xffffffff
+#define SECURE_INTRCONN_O224_O256_S_MASK_SFT (0xffffffff << 0)
+
+/* AFE_PCM0_INTF_CON1_MASK_MON */
+#define AFE_PCM0_INTF_CON1_MASK_MON_SFT 0
+#define AFE_PCM0_INTF_CON1_MASK_MON_MASK 0xffffffff
+#define AFE_PCM0_INTF_CON1_MASK_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_PCM0_INTF_CON0_MASK_MON */
+#define AFE_PCM0_INTF_CON0_MASK_MON_SFT 0
+#define AFE_PCM0_INTF_CON0_MASK_MON_MASK 0xffffffff
+#define AFE_PCM0_INTF_CON0_MASK_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_CONNSYS_I2S_CON_MASK_MON */
+#define AFE_CONNSYS_I2S_CON_MASK_MON_SFT 0
+#define AFE_CONNSYS_I2S_CON_MASK_MON_MASK 0xffffffff
+#define AFE_CONNSYS_I2S_CON_MASK_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_MTKAIF0_CFG0_MASK_MON */
+#define AFE_MTKAIF0_CFG0_MASK_MON_SFT 0
+#define AFE_MTKAIF0_CFG0_MASK_MON_MASK 0xffffffff
+#define AFE_MTKAIF0_CFG0_MASK_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_MTKAIF1_CFG0_MASK_MON */
+#define AFE_MTKAIF1_CFG0_MASK_MON_SFT 0
+#define AFE_MTKAIF1_CFG0_MASK_MON_MASK 0xffffffff
+#define AFE_MTKAIF1_CFG0_MASK_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL0_SRC_CON0_MASK_MON */
+#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_SFT 0
+#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_MASK 0xffffffff
+#define AFE_ADDA_UL0_SRC_CON0_MASK_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_ADDA_UL1_SRC_CON0_MASK_MON */
+#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_SFT 0
+#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_MASK 0xffffffff
+#define AFE_ADDA_UL1_SRC_CON0_MASK_MON_MASK_SFT (0xffffffff << 0)
+
+/* AFE_GASRC0_NEW_CON0 */
+#define ONE_HEART_SFT 31
+#define ONE_HEART_MASK 0x1
+#define ONE_HEART_MASK_SFT (0x1 << 31)
+#define CHSET0_OFS_ONE_HEART_DISABLE_SFT 30
+#define CHSET0_OFS_ONE_HEART_DISABLE_MASK 0x1
+#define CHSET0_OFS_ONE_HEART_DISABLE_MASK_SFT (0x1 << 30)
+#define USE_SHORT_DELAY_COEFF_SFT 29
+#define USE_SHORT_DELAY_COEFF_MASK 0x1
+#define USE_SHORT_DELAY_COEFF_MASK_SFT (0x1 << 29)
+#define CHSET0_O16BIT_SFT 19
+#define CHSET0_O16BIT_MASK 0x1
+#define CHSET0_O16BIT_MASK_SFT (0x1 << 19)
+#define CHSET0_CLR_IIR_HISTORY_SFT 17
+#define CHSET0_CLR_IIR_HISTORY_MASK 0x1
+#define CHSET0_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)
+#define CHSET0_IS_MONO_SFT 16
+#define CHSET0_IS_MONO_MASK 0x1
+#define CHSET0_IS_MONO_MASK_SFT (0x1 << 16)
+#define CHSET0_OFS_SEL_SFT 14
+#define CHSET0_OFS_SEL_MASK 0x3
+#define CHSET0_OFS_SEL_MASK_SFT (0x3 << 14)
+#define CHSET0_IFS_SEL_SFT 12
+#define CHSET0_IFS_SEL_MASK 0x3
+#define CHSET0_IFS_SEL_MASK_SFT (0x3 << 12)
+#define CHSET0_IIR_EN_SFT 11
+#define CHSET0_IIR_EN_MASK 0x1
+#define CHSET0_IIR_EN_MASK_SFT (0x1 << 11)
+#define CHSET0_IIR_STAGE_SFT 8
+#define CHSET0_IIR_STAGE_MASK 0x7
+#define CHSET0_IIR_STAGE_MASK_SFT (0x7 << 8)
+#define ASM_ON_MOD_SFT 7
+#define ASM_ON_MOD_MASK 0x1
+#define ASM_ON_MOD_MASK_SFT (0x1 << 7)
+#define CHSET_STR_CLR_SFT 4
+#define CHSET_STR_CLR_MASK 0x1
+#define CHSET_STR_CLR_MASK_SFT (0x1 << 4)
+#define CHSET_ON_SFT 2
+#define CHSET_ON_MASK 0x1
+#define CHSET_ON_MASK_SFT (0x1 << 2)
+#define COEFF_SRAM_CTRL_SFT 1
+#define COEFF_SRAM_CTRL_MASK 0x1
+#define COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)
+#define ASM_ON_SFT 0
+#define ASM_ON_MASK 0x1
+#define ASM_ON_MASK_SFT (0x1 << 0)
+
+/* AFE_GASRC0_NEW_CON1 */
+#define ASM_FREQ_0_SFT 0
+#define ASM_FREQ_0_MASK 0xffffff
+#define ASM_FREQ_0_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_CON2 */
+#define ASM_FREQ_1_SFT 0
+#define ASM_FREQ_1_MASK 0xffffff
+#define ASM_FREQ_1_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_CON3 */
+#define ASM_FREQ_2_SFT 0
+#define ASM_FREQ_2_MASK 0xffffff
+#define ASM_FREQ_2_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_CON4 */
+#define ASM_FREQ_3_SFT 0
+#define ASM_FREQ_3_MASK 0xffffff
+#define ASM_FREQ_3_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_CON5 */
+#define OUT_EN_SEL_DOMAIN_SFT 29
+#define OUT_EN_SEL_DOMAIN_MASK 0x7
+#define OUT_EN_SEL_DOMAIN_MASK_SFT (0x7 << 29)
+#define OUT_EN_SEL_FS_SFT 24
+#define OUT_EN_SEL_FS_MASK 0x1f
+#define OUT_EN_SEL_FS_MASK_SFT (0x1f << 24)
+#define IN_EN_SEL_DOMAIN_SFT 21
+#define IN_EN_SEL_DOMAIN_MASK 0x7
+#define IN_EN_SEL_DOMAIN_MASK_SFT (0x7 << 21)
+#define IN_EN_SEL_FS_SFT 16
+#define IN_EN_SEL_FS_MASK 0x1f
+#define IN_EN_SEL_FS_MASK_SFT (0x1f << 16)
+#define RESULT_SEL_SFT 8
+#define RESULT_SEL_MASK 0x7
+#define RESULT_SEL_MASK_SFT (0x7 << 8)
+#define CALI_CK_SEL_SFT 4
+#define CALI_CK_SEL_MASK 0x7
+#define CALI_CK_SEL_MASK_SFT (0x7 << 4)
+#define CALI_LRCK_SEL_SFT 1
+#define CALI_LRCK_SEL_MASK 0x7
+#define CALI_LRCK_SEL_MASK_SFT (0x7 << 1)
+#define SOFT_RESET_SFT 0
+#define SOFT_RESET_MASK 0x1
+#define SOFT_RESET_MASK_SFT (0x1 << 0)
+
+/* AFE_GASRC0_NEW_CON6 */
+#define FREQ_CALI_CYCLE_SFT 16
+#define FREQ_CALI_CYCLE_MASK 0xffff
+#define FREQ_CALI_CYCLE_MASK_SFT (0xffff << 16)
+#define FREQ_CALI_AUTORST_EN_SFT 15
+#define FREQ_CALI_AUTORST_EN_MASK 0x1
+#define FREQ_CALI_AUTORST_EN_MASK_SFT (0x1 << 15)
+#define CALI_AUTORST_DETECT_SFT 14
+#define CALI_AUTORST_DETECT_MASK 0x1
+#define CALI_AUTORST_DETECT_MASK_SFT (0x1 << 14)
+#define FREQ_CALC_RUNNING_SFT 13
+#define FREQ_CALC_RUNNING_MASK 0x1
+#define FREQ_CALC_RUNNING_MASK_SFT (0x1 << 13)
+#define AUTO_TUNE_FREQ3_SFT 12
+#define AUTO_TUNE_FREQ3_MASK 0x1
+#define AUTO_TUNE_FREQ3_MASK_SFT (0x1 << 12)
+#define COMP_FREQ_RES_EN_SFT 11
+#define COMP_FREQ_RES_EN_MASK 0x1
+#define COMP_FREQ_RES_EN_MASK_SFT (0x1 << 11)
+#define FREQ_CALI_SEL_SFT 8
+#define FREQ_CALI_SEL_MASK 0x3
+#define FREQ_CALI_SEL_MASK_SFT (0x3 << 8)
+#define FREQ_CALI_BP_DGL_SFT 7
+#define FREQ_CALI_BP_DGL_MASK 0x1
+#define FREQ_CALI_BP_DGL_MASK_SFT (0x1 << 7)
+#define FREQ_CALI_MAX_GWIDTH_SFT 4
+#define FREQ_CALI_MAX_GWIDTH_MASK 0x7
+#define FREQ_CALI_MAX_GWIDTH_MASK_SFT (0x7 << 4)
+#define AUTO_TUNE_FREQ2_SFT 3
+#define AUTO_TUNE_FREQ2_MASK 0x1
+#define AUTO_TUNE_FREQ2_MASK_SFT (0x1 << 3)
+#define FREQ_CALI_AUTO_RESTART_SFT 2
+#define FREQ_CALI_AUTO_RESTART_MASK 0x1
+#define FREQ_CALI_AUTO_RESTART_MASK_SFT (0x1 << 2)
+#define CALI_USE_FREQ_OUT_SFT 1
+#define CALI_USE_FREQ_OUT_MASK 0x1
+#define CALI_USE_FREQ_OUT_MASK_SFT (0x1 << 1)
+#define CALI_EN_SFT 0
+#define CALI_EN_MASK 0x1
+#define CALI_EN_MASK_SFT (0x1 << 0)
+
+/* AFE_GASRC0_NEW_CON7 */
+#define FREQ_CALC_DENOMINATOR_SFT 0
+#define FREQ_CALC_DENOMINATOR_MASK 0xffffff
+#define FREQ_CALC_DENOMINATOR_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_CON8 */
+#define PRD_CALI_RESULT_RECORD_SFT 0
+#define PRD_CALI_RESULT_RECORD_MASK 0xffffff
+#define PRD_CALI_RESULT_RECORD_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_CON9 */
+#define FREQ_CALI_RESULT_SFT 0
+#define FREQ_CALI_RESULT_MASK 0xffffff
+#define FREQ_CALI_RESULT_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_CON10 */
+#define COEFF_SRAM_DATA_SFT 0
+#define COEFF_SRAM_DATA_MASK 0xffffffff
+#define COEFF_SRAM_DATA_MASK_SFT (0xffffffff << 0)
+
+/* AFE_GASRC0_NEW_CON11 */
+#define COEFF_SRAM_ADR_SFT 0
+#define COEFF_SRAM_ADR_MASK 0x3f
+#define COEFF_SRAM_ADR_MASK_SFT (0x3f << 0)
+
+/* AFE_GASRC0_NEW_CON12 */
+#define RING_DBG_RD_SFT 0
+#define RING_DBG_RD_MASK 0x3ffffff
+#define RING_DBG_RD_MASK_SFT (0x3ffffff << 0)
+
+/* AFE_GASRC0_NEW_CON13 */
+#define FREQ_CALI_AUTORST_TH_HIGH_SFT 0
+#define FREQ_CALI_AUTORST_TH_HIGH_MASK 0xffffff
+#define FREQ_CALI_AUTORST_TH_HIGH_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_CON14 */
+#define FREQ_CALI_AUTORST_TH_LOW_SFT 0
+#define FREQ_CALI_AUTORST_TH_LOW_MASK 0xffffff
+#define FREQ_CALI_AUTORST_TH_LOW_MASK_SFT (0xffffff << 0)
+
+/* AFE_GASRC0_NEW_IP_VERSION */
+#define IP_VERSION_SFT 0
+#define IP_VERSION_MASK 0xffffffff
+#define IP_VERSION_MASK_SFT (0xffffffff << 0)
+
+#define AUDIO_TOP_CON0 0x0
+#define AUDIO_TOP_CON1 0x4
+#define AUDIO_TOP_CON2 0x8
+#define AUDIO_TOP_CON3 0xc
+#define AUDIO_TOP_CON4 0x10
+#define AUDIO_ENGEN_CON0 0x14
+#define AUDIO_ENGEN_CON0_USER1 0x18
+#define AUDIO_ENGEN_CON0_USER2 0x1c
+#define AFE_SINEGEN_CON0 0x20
+#define AFE_SINEGEN_CON1 0x24
+#define AFE_SINEGEN_CON2 0x28
+#define AFE_SINEGEN_CON3 0x2c
+#define AFE_APLL1_TUNER_CFG 0x30
+#define AFE_APLL1_TUNER_MON0 0x34
+#define AFE_APLL2_TUNER_CFG 0x38
+#define AFE_APLL2_TUNER_MON0 0x3c
+#define AUDIO_TOP_RG0 0x4c
+#define AUDIO_TOP_RG1 0x50
+#define AUDIO_TOP_RG2 0x54
+#define AUDIO_TOP_RG3 0x58
+#define AUDIO_TOP_RG4 0x5c
+#define AFE_SPM_CONTROL_REQ 0x60
+#define AFE_SPM_CONTROL_ACK 0x64
+#define AUD_TOP_CFG_VCORE_RG 0x68
+#define AUDIO_TOP_IP_VERSION 0x6c
+#define AUDIO_ENGEN_CON0_MON 0x7c
+#define AUDIO_PROJECT_MON 0x80
+#define AUD_TOP_CFG_VLP_RG 0x98
+#define AUD_TOP_MON_RG 0x9c
+#define AUDIO_USE_DEFAULT_DELSEL0 0xa0
+#define AUDIO_USE_DEFAULT_DELSEL1 0xa4
+#define AUDIO_USE_DEFAULT_DELSEL2 0xa8
+#define AFE_CONNSYS_I2S_IPM_VER_MON 0xb0
+#define AFE_CONNSYS_I2S_MON_SEL 0xb4
+#define AFE_CONNSYS_I2S_MON 0xb8
+#define AFE_CONNSYS_I2S_CON 0xbc
+#define AFE_PCM0_INTF_CON0 0xc0
+#define AFE_PCM0_INTF_CON1 0xc4
+#define AFE_PCM_INTF_MON 0xc8
+#define AFE_PCM_TOP_IP_VERSION 0xe8
+#define AFE_GAIN0_CON0 0x400
+#define AFE_GAIN0_CON1_R 0x404
+#define AFE_GAIN0_CON1_L 0x408
+#define AFE_GAIN0_CON2 0x40c
+#define AFE_GAIN0_CON3 0x410
+#define AFE_GAIN0_CUR_R 0x414
+#define AFE_GAIN0_CUR_L 0x418
+#define AFE_GAIN1_CON0 0x41c
+#define AFE_GAIN1_CON1_R 0x420
+#define AFE_GAIN1_CON1_L 0x424
+#define AFE_GAIN1_CON2 0x428
+#define AFE_GAIN1_CON3 0x42c
+#define AFE_GAIN1_CUR_R 0x430
+#define AFE_GAIN1_CUR_L 0x434
+#define AFE_GAIN2_CON0 0x438
+#define AFE_GAIN2_CON1_R 0x43c
+#define AFE_GAIN2_CON1_L 0x440
+#define AFE_GAIN2_CON2 0x444
+#define AFE_GAIN2_CON3 0x448
+#define AFE_GAIN2_CUR_R 0x44c
+#define AFE_GAIN2_CUR_L 0x450
+#define AFE_GAIN3_CON0 0x454
+#define AFE_GAIN3_CON1_R 0x458
+#define AFE_GAIN3_CON1_L 0x45c
+#define AFE_GAIN3_CON2 0x460
+#define AFE_GAIN3_CON3 0x464
+#define AFE_GAIN3_CUR_R 0x468
+#define AFE_GAIN3_CUR_L 0x46c
+#define AFE_GAIN_0_1_IP_VERSION 0x474
+#define AFE_GAIN_2_3_IP_VERSION 0x478
+#define AFE_ADDA_DL_IPM_VER_MON 0x4c0
+#define AFE_ADDA_DL_SRC_CON0 0x4d0
+#define AFE_ADDA_DL_SRC_CON1 0x4d4
+#define AFE_ADDA_DL_SRC_DEBUG_MON0 0x4d8
+#define AFE_ADDA_DL_PREDIS_CON0 0x4dc
+#define AFE_ADDA_DL_PREDIS_CON1 0x4e0
+#define AFE_ADDA_DL_PREDIS_CON2 0x4e4
+#define AFE_ADDA_DL_PREDIS_CON3 0x4e8
+#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x4ec
+#define AFE_ADDA_DL_SDM_TEST 0x4f0
+#define AFE_ADDA_DL_DC_COMP_CFG0 0x4f4
+#define AFE_ADDA_DL_DC_COMP_CFG1 0x4f8
+#define AFE_ADDA_DL_SDM_OUT_MON 0x4fc
+#define AFE_ADDA_DL_SRC_LCH_MON 0x500
+#define AFE_ADDA_DL_SRC_RCH_MON 0x504
+#define AFE_ADDA_DL_SRC_DEBUG 0x508
+#define AFE_ADDA_DL_SDM_DITHER_CON 0x50c
+#define AFE_ADDA_DL_SDM_AUTO_RESET_CON 0x510
+#define AFE_ADDA_DL_HBF1_SCF1_CONFIG 0x514
+#define AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG 0x518
+#define AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG 0x51c
+#define AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG 0x520
+#define AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG 0x524
+#define AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG 0x528
+#define AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG 0x52c
+#define AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG 0x530
+#define AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG 0x534
+#define AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG 0x538
+#define AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG 0x53c
+#define AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG 0x540
+#define AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG 0x544
+#define AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG 0x548
+#define AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG 0x54c
+#define AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG 0x550
+#define AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG 0x554
+#define AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG 0x558
+#define AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG 0x55c
+#define AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG 0x560
+#define AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG 0x564
+#define AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG 0x568
+#define AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG 0x56c
+#define AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG 0x570
+#define AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG 0x574
+#define AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG 0x578
+#define AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG 0x57c
+#define AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG 0x580
+#define AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG 0x584
+#define AFE_DEM_IDWA_CON0 0xa1c
+#define DEM_RECONSTRUCT_MON 0xa20
+#define AFE_CM0_CON0 0xba0
+#define AFE_CM0_MON 0xba4
+#define AFE_CM0_IP_VERSION 0xba8
+#define AFE_CM1_CON0 0xbb0
+#define AFE_CM1_MON 0xbb4
+#define AFE_CM1_IP_VERSION 0xbb8
+#define AFE_ADDA_UL0_SRC_CON0 0xbd0
+#define AFE_ADDA_UL0_SRC_CON1 0xbd4
+#define AFE_ADDA_UL0_SRC_CON2 0xbd8
+#define AFE_ADDA_UL0_SRC_DEBUG 0xbdc
+#define AFE_ADDA_UL0_SRC_DEBUG_MON0 0xbe0
+#define AFE_ADDA_UL0_SRC_MON0 0xbe4
+#define AFE_ADDA_UL0_SRC_MON1 0xbe8
+#define AFE_ADDA_UL0_IIR_COEF_02_01 0xbec
+#define AFE_ADDA_UL0_IIR_COEF_04_03 0xbf0
+#define AFE_ADDA_UL0_IIR_COEF_06_05 0xbf4
+#define AFE_ADDA_UL0_IIR_COEF_08_07 0xbf8
+#define AFE_ADDA_UL0_IIR_COEF_10_09 0xbfc
+#define AFE_ADDA_UL0_ULCF_CFG_02_01 0xc00
+#define AFE_ADDA_UL0_ULCF_CFG_04_03 0xc04
+#define AFE_ADDA_UL0_ULCF_CFG_06_05 0xc08
+#define AFE_ADDA_UL0_ULCF_CFG_08_07 0xc0c
+#define AFE_ADDA_UL0_ULCF_CFG_10_09 0xc10
+#define AFE_ADDA_UL0_ULCF_CFG_12_11 0xc14
+#define AFE_ADDA_UL0_ULCF_CFG_14_13 0xc18
+#define AFE_ADDA_UL0_ULCF_CFG_16_15 0xc1c
+#define AFE_ADDA_UL0_ULCF_CFG_18_17 0xc20
+#define AFE_ADDA_UL0_ULCF_CFG_20_19 0xc24
+#define AFE_ADDA_UL0_ULCF_CFG_22_21 0xc28
+#define AFE_ADDA_UL0_ULCF_CFG_24_23 0xc2c
+#define AFE_ADDA_UL0_ULCF_CFG_26_25 0xc30
+#define AFE_ADDA_UL0_ULCF_CFG_28_27 0xc34
+#define AFE_ADDA_UL0_ULCF_CFG_30_29 0xc38
+#define AFE_ADDA_UL0_ULCF_CFG_32_31 0xc3c
+#define AFE_ADDA_UL0_IP_VERSION 0xc4c
+#define AFE_ADDA_DMIC0_SRC_CON0 0xdd0
+#define AFE_ADDA_DMIC0_SRC_CON1 0xdd4
+#define AFE_ADDA_DMIC0_SRC_CON2 0xdd8
+#define AFE_ADDA_DMIC0_SRC_DEBUG 0xddc
+#define AFE_ADDA_DMIC0_SRC_DEBUG_MON0 0xde0
+#define AFE_ADDA_DMIC0_SRC_MON0 0xde4
+#define AFE_ADDA_DMIC0_SRC_MON1 0xde8
+#define AFE_ADDA_DMIC0_IIR_COEF_02_01 0xdec
+#define AFE_ADDA_DMIC0_IIR_COEF_04_03 0xdf0
+#define AFE_ADDA_DMIC0_IIR_COEF_06_05 0xdf4
+#define AFE_ADDA_DMIC0_IIR_COEF_08_07 0xdf8
+#define AFE_ADDA_DMIC0_IIR_COEF_10_09 0xdfc
+#define AFE_ADDA_DMIC0_ULCF_CFG_02_01 0xe00
+#define AFE_ADDA_DMIC0_ULCF_CFG_04_03 0xe04
+#define AFE_ADDA_DMIC0_ULCF_CFG_06_05 0xe08
+#define AFE_ADDA_DMIC0_ULCF_CFG_08_07 0xe0c
+#define AFE_ADDA_DMIC0_ULCF_CFG_10_09 0xe10
+#define AFE_ADDA_DMIC0_ULCF_CFG_12_11 0xe14
+#define AFE_ADDA_DMIC0_ULCF_CFG_14_13 0xe18
+#define AFE_ADDA_DMIC0_ULCF_CFG_16_15 0xe1c
+#define AFE_ADDA_DMIC0_ULCF_CFG_18_17 0xe20
+#define AFE_ADDA_DMIC0_ULCF_CFG_20_19 0xe24
+#define AFE_ADDA_DMIC0_ULCF_CFG_22_21 0xe28
+#define AFE_ADDA_DMIC0_ULCF_CFG_24_23 0xe2c
+#define AFE_ADDA_DMIC0_ULCF_CFG_26_25 0xe30
+#define AFE_ADDA_DMIC0_ULCF_CFG_28_27 0xe34
+#define AFE_ADDA_DMIC0_ULCF_CFG_30_29 0xe38
+#define AFE_ADDA_DMIC0_ULCF_CFG_32_31 0xe3c
+#define AFE_ADDA_DMIC0_IP_VERSION 0xe4c
+#define AFE_ADDA_DMIC1_SRC_CON0 0xe50
+#define AFE_ADDA_DMIC1_SRC_CON1 0xe54
+#define AFE_ADDA_DMIC1_SRC_CON2 0xe58
+#define AFE_ADDA_DMIC1_SRC_DEBUG 0xe5c
+#define AFE_ADDA_DMIC1_SRC_DEBUG_MON0 0xe60
+#define AFE_ADDA_DMIC1_SRC_MON0 0xe64
+#define AFE_ADDA_DMIC1_SRC_MON1 0xe68
+#define AFE_ADDA_DMIC1_IIR_COEF_02_01 0xe6c
+#define AFE_ADDA_DMIC1_IIR_COEF_04_03 0xe70
+#define AFE_ADDA_DMIC1_IIR_COEF_06_05 0xe74
+#define AFE_ADDA_DMIC1_IIR_COEF_08_07 0xe78
+#define AFE_ADDA_DMIC1_IIR_COEF_10_09 0xe7c
+#define AFE_ADDA_DMIC1_ULCF_CFG_02_01 0xe80
+#define AFE_ADDA_DMIC1_ULCF_CFG_04_03 0xe84
+#define AFE_ADDA_DMIC1_ULCF_CFG_06_05 0xe88
+#define AFE_ADDA_DMIC1_ULCF_CFG_08_07 0xe8c
+#define AFE_ADDA_DMIC1_ULCF_CFG_10_09 0xe90
+#define AFE_ADDA_DMIC1_ULCF_CFG_12_11 0xe94
+#define AFE_ADDA_DMIC1_ULCF_CFG_14_13 0xe98
+#define AFE_ADDA_DMIC1_ULCF_CFG_16_15 0xe9c
+#define AFE_ADDA_DMIC1_ULCF_CFG_18_17 0xea0
+#define AFE_ADDA_DMIC1_ULCF_CFG_20_19 0xea4
+#define AFE_ADDA_DMIC1_ULCF_CFG_22_21 0xea8
+#define AFE_ADDA_DMIC1_ULCF_CFG_24_23 0xeac
+#define AFE_ADDA_DMIC1_ULCF_CFG_26_25 0xeb0
+#define AFE_ADDA_DMIC1_ULCF_CFG_28_27 0xeb4
+#define AFE_ADDA_DMIC1_ULCF_CFG_30_29 0xeb8
+#define AFE_ADDA_DMIC1_ULCF_CFG_32_31 0xebc
+#define AFE_ADDA_DMIC1_IP_VERSION 0xecc
+#define AFE_ADDA_ULSRC_PHASE_CLK_CON0 0xf00
+#define AFE_ADDA_ULSRC_PHASE_CLK_CON1 0xf04
+#define AFE_ADDA_ULSRC_PHASE_CLK_CON2 0xf08
+#define AFE_ADDA_ULSRC_PHASE_CLK_CON3 0xf0c
+#define AFE_ADDA_ULSRC_PHASE_CLK_CON4 0xf10
+#define AFE_ADDA_ULSRC_PHASE_ENGEN_CON0 0xf14
+#define AFE_ADDA_ULSRC_PHASE_ENGEN_CON1 0xf18
+#define AFE_ADDA_ULSRC_PHASE_RST_CON0 0xf1c
+#define AFE_MTKAIF_IPM_VER_MON 0x1180
+#define AFE_MTKAIF_MON_SEL 0x1184
+#define AFE_MTKAIF_MON 0x1188
+#define AFE_MTKAIF0_CFG0 0x1190
+#define AFE_MTKAIF0_TX_CFG0 0x1194
+#define AFE_MTKAIF0_RX_CFG0 0x1198
+#define AFE_MTKAIF0_RX_CFG1 0x119c
+#define AFE_MTKAIF0_RX_CFG2 0x11a0
+#define AFE_MTKAIF1_CFG0 0x11f0
+#define AFE_MTKAIF1_TX_CFG0 0x11f4
+#define AFE_MTKAIF1_RX_CFG0 0x11f8
+#define AFE_MTKAIF1_RX_CFG1 0x11fc
+#define AFE_MTKAIF1_RX_CFG2 0x1200
+#define AFE_AUD_PAD_TOP_CFG0 0x1204
+#define AFE_AUD_PAD_TOP_MON 0x1208
+#define AFE_ADDA_MTKAIFV4_TX_CFG0 0x1280
+#define AFE_ADDA6_MTKAIFV4_TX_CFG0 0x1284
+#define AFE_ADDA_MTKAIFV4_RX_CFG0 0x1288
+#define AFE_ADDA_MTKAIFV4_RX_CFG1 0x128c
+#define AFE_ADDA6_MTKAIFV4_RX_CFG0 0x1290
+#define AFE_ADDA6_MTKAIFV4_RX_CFG1 0x1294
+#define AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG 0x1298
+#define AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG 0x129c
+#define AFE_ADDA_MTKAIFV4_MON0 0x12a0
+#define AFE_ADDA_MTKAIFV4_MON1 0x12a4
+#define AFE_ADDA6_MTKAIFV4_MON0 0x12a8
+#define ETDM_IN0_CON0 0x1300
+#define ETDM_IN0_CON1 0x1304
+#define ETDM_IN0_CON2 0x1308
+#define ETDM_IN0_CON3 0x130c
+#define ETDM_IN0_CON4 0x1310
+#define ETDM_IN0_CON5 0x1314
+#define ETDM_IN0_CON6 0x1318
+#define ETDM_IN0_CON7 0x131c
+#define ETDM_IN0_CON8 0x1320
+#define ETDM_IN0_CON9 0x1324
+#define ETDM_IN0_MON 0x1328
+#define ETDM_IN1_CON0 0x1330
+#define ETDM_IN1_CON1 0x1334
+#define ETDM_IN1_CON2 0x1338
+#define ETDM_IN1_CON3 0x133c
+#define ETDM_IN1_CON4 0x1340
+#define ETDM_IN1_CON5 0x1344
+#define ETDM_IN1_CON6 0x1348
+#define ETDM_IN1_CON7 0x134c
+#define ETDM_IN1_CON8 0x1350
+#define ETDM_IN1_CON9 0x1354
+#define ETDM_IN1_MON 0x1358
+#define ETDM_OUT0_CON0 0x1480
+#define ETDM_OUT0_CON1 0x1484
+#define ETDM_OUT0_CON2 0x1488
+#define ETDM_OUT0_CON3 0x148c
+#define ETDM_OUT0_CON4 0x1490
+#define ETDM_OUT0_CON5 0x1494
+#define ETDM_OUT0_CON6 0x1498
+#define ETDM_OUT0_CON7 0x149c
+#define ETDM_OUT0_CON8 0x14a0
+#define ETDM_OUT0_CON9 0x14a4
+#define ETDM_OUT0_MON 0x14a8
+#define ETDM_OUT1_CON0 0x14c0
+#define ETDM_OUT1_CON1 0x14c4
+#define ETDM_OUT1_CON2 0x14c8
+#define ETDM_OUT1_CON3 0x14cc
+#define ETDM_OUT1_CON4 0x14d0
+#define ETDM_OUT1_CON5 0x14d4
+#define ETDM_OUT1_CON6 0x14d8
+#define ETDM_OUT1_CON7 0x14dc
+#define ETDM_OUT1_CON8 0x14e0
+#define ETDM_OUT1_CON9 0x14e4
+#define ETDM_OUT1_MON 0x14e8
+#define ETDM_OUT4_CON0 0x1580
+#define ETDM_OUT4_CON1 0x1584
+#define ETDM_OUT4_CON2 0x1588
+#define ETDM_OUT4_CON3 0x158c
+#define ETDM_OUT4_CON4 0x1590
+#define ETDM_OUT4_CON5 0x1594
+#define ETDM_OUT4_CON6 0x1598
+#define ETDM_OUT4_CON7 0x159c
+#define ETDM_OUT4_CON8 0x15a0
+#define ETDM_OUT4_CON9 0x15a4
+#define ETDM_OUT4_MON 0x15a8
+#define ETDM_0_3_COWORK_CON0 0x1680
+#define ETDM_0_3_COWORK_CON1 0x1684
+#define ETDM_0_3_COWORK_CON2 0x1688
+#define ETDM_0_3_COWORK_CON3 0x168c
+#define ETDM_4_7_COWORK_CON0 0x1690
+#define ETDM_4_7_COWORK_CON1 0x1694
+#define ETDM_4_7_COWORK_CON2 0x1698
+#define ETDM_4_7_COWORK_CON3 0x169c
+#define ETDM_IP_VERSION 0x1c4c
+#define AFE_DPTX_CON 0x2040
+#define AFE_DPTX_MON 0x2044
+#define AFE_TDM_CON1 0x2048
+#define AFE_TDM_CON2 0x204c
+#define AFE_TDM_CON3 0x2050
+#define AFE_TDM_OUT_MON 0x2054
+#define AFE_HDMI_CONN0 0x2078
+#define AFE_TDM_TOP_IP_VERSION 0x207c
+#define AFE_CONN004_0 0x2100
+#define AFE_CONN004_1 0x2104
+#define AFE_CONN004_2 0x2108
+#define AFE_CONN004_4 0x2110
+#define AFE_CONN004_6 0x2118
+#define AFE_CONN005_0 0x2120
+#define AFE_CONN005_1 0x2124
+#define AFE_CONN005_2 0x2128
+#define AFE_CONN005_4 0x2130
+#define AFE_CONN005_6 0x2138
+#define AFE_CONN006_0 0x2140
+#define AFE_CONN006_1 0x2144
+#define AFE_CONN006_2 0x2148
+#define AFE_CONN006_4 0x2150
+#define AFE_CONN006_6 0x2158
+#define AFE_CONN007_0 0x2160
+#define AFE_CONN007_1 0x2164
+#define AFE_CONN007_2 0x2168
+#define AFE_CONN007_4 0x2170
+#define AFE_CONN007_6 0x2178
+#define AFE_CONN008_0 0x2180
+#define AFE_CONN008_1 0x2184
+#define AFE_CONN008_2 0x2188
+#define AFE_CONN008_4 0x2190
+#define AFE_CONN008_6 0x2198
+#define AFE_CONN009_0 0x21a0
+#define AFE_CONN009_1 0x21a4
+#define AFE_CONN009_2 0x21a8
+#define AFE_CONN009_4 0x21b0
+#define AFE_CONN009_6 0x21b8
+#define AFE_CONN010_0 0x21c0
+#define AFE_CONN010_1 0x21c4
+#define AFE_CONN010_2 0x21c8
+#define AFE_CONN010_4 0x21d0
+#define AFE_CONN010_6 0x21d8
+#define AFE_CONN011_0 0x21e0
+#define AFE_CONN011_1 0x21e4
+#define AFE_CONN011_2 0x21e8
+#define AFE_CONN011_4 0x21f0
+#define AFE_CONN011_6 0x21f8
+#define AFE_CONN014_0 0x2240
+#define AFE_CONN014_1 0x2244
+#define AFE_CONN014_2 0x2248
+#define AFE_CONN014_4 0x2250
+#define AFE_CONN014_6 0x2258
+#define AFE_CONN015_0 0x2260
+#define AFE_CONN015_1 0x2264
+#define AFE_CONN015_2 0x2268
+#define AFE_CONN015_4 0x2270
+#define AFE_CONN015_6 0x2278
+#define AFE_CONN016_0 0x2280
+#define AFE_CONN016_1 0x2284
+#define AFE_CONN016_2 0x2288
+#define AFE_CONN016_4 0x2290
+#define AFE_CONN016_6 0x2298
+#define AFE_CONN017_0 0x22a0
+#define AFE_CONN017_1 0x22a4
+#define AFE_CONN017_2 0x22a8
+#define AFE_CONN017_4 0x22b0
+#define AFE_CONN017_6 0x22b8
+#define AFE_CONN018_0 0x22c0
+#define AFE_CONN018_1 0x22c4
+#define AFE_CONN018_2 0x22c8
+#define AFE_CONN018_4 0x22d0
+#define AFE_CONN018_6 0x22d8
+#define AFE_CONN019_0 0x22e0
+#define AFE_CONN019_1 0x22e4
+#define AFE_CONN019_2 0x22e8
+#define AFE_CONN019_4 0x22f0
+#define AFE_CONN019_6 0x22f8
+#define AFE_CONN020_0 0x2300
+#define AFE_CONN020_1 0x2304
+#define AFE_CONN020_2 0x2308
+#define AFE_CONN020_4 0x2310
+#define AFE_CONN020_6 0x2318
+#define AFE_CONN021_0 0x2320
+#define AFE_CONN021_1 0x2324
+#define AFE_CONN021_2 0x2328
+#define AFE_CONN021_4 0x2330
+#define AFE_CONN021_6 0x2338
+#define AFE_CONN022_0 0x2340
+#define AFE_CONN022_1 0x2344
+#define AFE_CONN022_2 0x2348
+#define AFE_CONN022_4 0x2350
+#define AFE_CONN022_6 0x2358
+#define AFE_CONN023_0 0x2360
+#define AFE_CONN023_1 0x2364
+#define AFE_CONN023_2 0x2368
+#define AFE_CONN023_4 0x2370
+#define AFE_CONN023_6 0x2378
+#define AFE_CONN024_0 0x2380
+#define AFE_CONN024_1 0x2384
+#define AFE_CONN024_2 0x2388
+#define AFE_CONN024_4 0x2390
+#define AFE_CONN024_6 0x2398
+#define AFE_CONN025_0 0x23a0
+#define AFE_CONN025_1 0x23a4
+#define AFE_CONN025_2 0x23a8
+#define AFE_CONN025_4 0x23b0
+#define AFE_CONN025_6 0x23b8
+#define AFE_CONN026_0 0x23c0
+#define AFE_CONN026_1 0x23c4
+#define AFE_CONN026_2 0x23c8
+#define AFE_CONN026_4 0x23d0
+#define AFE_CONN026_6 0x23d8
+#define AFE_CONN027_0 0x23e0
+#define AFE_CONN027_1 0x23e4
+#define AFE_CONN027_2 0x23e8
+#define AFE_CONN027_4 0x23f0
+#define AFE_CONN027_6 0x23f8
+#define AFE_CONN028_0 0x2400
+#define AFE_CONN028_1 0x2404
+#define AFE_CONN028_2 0x2408
+#define AFE_CONN028_4 0x2410
+#define AFE_CONN028_6 0x2418
+#define AFE_CONN029_0 0x2420
+#define AFE_CONN029_1 0x2424
+#define AFE_CONN029_2 0x2428
+#define AFE_CONN029_4 0x2430
+#define AFE_CONN029_6 0x2438
+#define AFE_CONN030_0 0x2440
+#define AFE_CONN030_1 0x2444
+#define AFE_CONN030_2 0x2448
+#define AFE_CONN030_4 0x2450
+#define AFE_CONN030_6 0x2458
+#define AFE_CONN031_0 0x2460
+#define AFE_CONN031_1 0x2464
+#define AFE_CONN031_2 0x2468
+#define AFE_CONN031_4 0x2470
+#define AFE_CONN031_6 0x2478
+#define AFE_CONN032_0 0x2480
+#define AFE_CONN032_1 0x2484
+#define AFE_CONN032_2 0x2488
+#define AFE_CONN032_4 0x2490
+#define AFE_CONN032_6 0x2498
+#define AFE_CONN033_0 0x24a0
+#define AFE_CONN033_1 0x24a4
+#define AFE_CONN033_2 0x24a8
+#define AFE_CONN033_4 0x24b0
+#define AFE_CONN033_6 0x24b8
+#define AFE_CONN034_0 0x24c0
+#define AFE_CONN034_1 0x24c4
+#define AFE_CONN034_2 0x24c8
+#define AFE_CONN034_4 0x24d0
+#define AFE_CONN034_6 0x24d8
+#define AFE_CONN035_0 0x24e0
+#define AFE_CONN035_1 0x24e4
+#define AFE_CONN035_2 0x24e8
+#define AFE_CONN035_4 0x24f0
+#define AFE_CONN035_6 0x24f8
+#define AFE_CONN036_0 0x2500
+#define AFE_CONN036_1 0x2504
+#define AFE_CONN036_2 0x2508
+#define AFE_CONN036_4 0x2510
+#define AFE_CONN036_6 0x2518
+#define AFE_CONN037_0 0x2520
+#define AFE_CONN037_1 0x2524
+#define AFE_CONN037_2 0x2528
+#define AFE_CONN037_4 0x2530
+#define AFE_CONN037_6 0x2538
+#define AFE_CONN038_0 0x2540
+#define AFE_CONN038_1 0x2544
+#define AFE_CONN038_2 0x2548
+#define AFE_CONN038_4 0x2550
+#define AFE_CONN038_6 0x2558
+#define AFE_CONN039_0 0x2560
+#define AFE_CONN039_1 0x2564
+#define AFE_CONN039_2 0x2568
+#define AFE_CONN039_4 0x2570
+#define AFE_CONN039_6 0x2578
+#define AFE_CONN040_0 0x2580
+#define AFE_CONN040_1 0x2584
+#define AFE_CONN040_2 0x2588
+#define AFE_CONN040_4 0x2590
+#define AFE_CONN040_6 0x2598
+#define AFE_CONN041_0 0x25a0
+#define AFE_CONN041_1 0x25a4
+#define AFE_CONN041_2 0x25a8
+#define AFE_CONN041_4 0x25b0
+#define AFE_CONN041_6 0x25b8
+#define AFE_CONN042_0 0x25c0
+#define AFE_CONN042_1 0x25c4
+#define AFE_CONN042_2 0x25c8
+#define AFE_CONN042_4 0x25d0
+#define AFE_CONN042_6 0x25d8
+#define AFE_CONN043_0 0x25e0
+#define AFE_CONN043_1 0x25e4
+#define AFE_CONN043_2 0x25e8
+#define AFE_CONN043_4 0x25f0
+#define AFE_CONN043_6 0x25f8
+#define AFE_CONN044_0 0x2600
+#define AFE_CONN044_1 0x2604
+#define AFE_CONN044_2 0x2608
+#define AFE_CONN044_4 0x2610
+#define AFE_CONN044_6 0x2618
+#define AFE_CONN045_0 0x2620
+#define AFE_CONN045_1 0x2624
+#define AFE_CONN045_2 0x2628
+#define AFE_CONN045_4 0x2630
+#define AFE_CONN045_6 0x2638
+#define AFE_CONN046_0 0x2640
+#define AFE_CONN046_1 0x2644
+#define AFE_CONN046_2 0x2648
+#define AFE_CONN046_4 0x2650
+#define AFE_CONN046_6 0x2658
+#define AFE_CONN047_0 0x2660
+#define AFE_CONN047_1 0x2664
+#define AFE_CONN047_2 0x2668
+#define AFE_CONN047_4 0x2670
+#define AFE_CONN047_6 0x2678
+#define AFE_CONN048_0 0x2680
+#define AFE_CONN048_1 0x2684
+#define AFE_CONN048_2 0x2688
+#define AFE_CONN048_4 0x2690
+#define AFE_CONN048_6 0x2698
+#define AFE_CONN049_0 0x26a0
+#define AFE_CONN049_1 0x26a4
+#define AFE_CONN049_2 0x26a8
+#define AFE_CONN049_4 0x26b0
+#define AFE_CONN049_6 0x26b8
+#define AFE_CONN050_0 0x26c0
+#define AFE_CONN050_1 0x26c4
+#define AFE_CONN050_2 0x26c8
+#define AFE_CONN050_4 0x26d0
+#define AFE_CONN050_6 0x26d8
+#define AFE_CONN051_0 0x26e0
+#define AFE_CONN051_1 0x26e4
+#define AFE_CONN051_2 0x26e8
+#define AFE_CONN051_4 0x26f0
+#define AFE_CONN051_6 0x26f8
+#define AFE_CONN052_0 0x2700
+#define AFE_CONN052_1 0x2704
+#define AFE_CONN052_2 0x2708
+#define AFE_CONN052_4 0x2710
+#define AFE_CONN052_6 0x2718
+#define AFE_CONN053_0 0x2720
+#define AFE_CONN053_1 0x2724
+#define AFE_CONN053_2 0x2728
+#define AFE_CONN053_4 0x2730
+#define AFE_CONN053_6 0x2738
+#define AFE_CONN054_0 0x2740
+#define AFE_CONN054_1 0x2744
+#define AFE_CONN054_2 0x2748
+#define AFE_CONN054_4 0x2750
+#define AFE_CONN054_6 0x2758
+#define AFE_CONN055_0 0x2760
+#define AFE_CONN055_1 0x2764
+#define AFE_CONN055_2 0x2768
+#define AFE_CONN055_4 0x2770
+#define AFE_CONN055_6 0x2778
+#define AFE_CONN056_0 0x2780
+#define AFE_CONN056_1 0x2784
+#define AFE_CONN056_2 0x2788
+#define AFE_CONN056_4 0x2790
+#define AFE_CONN056_6 0x2798
+#define AFE_CONN057_0 0x27a0
+#define AFE_CONN057_1 0x27a4
+#define AFE_CONN057_2 0x27a8
+#define AFE_CONN057_4 0x27b0
+#define AFE_CONN057_6 0x27b8
+#define AFE_CONN058_0 0x27c0
+#define AFE_CONN058_1 0x27c4
+#define AFE_CONN058_2 0x27c8
+#define AFE_CONN058_4 0x27d0
+#define AFE_CONN058_6 0x27d8
+#define AFE_CONN059_0 0x27e0
+#define AFE_CONN059_1 0x27e4
+#define AFE_CONN059_2 0x27e8
+#define AFE_CONN059_4 0x27f0
+#define AFE_CONN059_6 0x27f8
+#define AFE_CONN060_0 0x2800
+#define AFE_CONN060_1 0x2804
+#define AFE_CONN060_2 0x2808
+#define AFE_CONN060_4 0x2810
+#define AFE_CONN060_6 0x2818
+#define AFE_CONN061_0 0x2820
+#define AFE_CONN061_1 0x2824
+#define AFE_CONN061_2 0x2828
+#define AFE_CONN061_4 0x2830
+#define AFE_CONN061_6 0x2838
+#define AFE_CONN062_0 0x2840
+#define AFE_CONN062_1 0x2844
+#define AFE_CONN062_2 0x2848
+#define AFE_CONN062_4 0x2850
+#define AFE_CONN062_6 0x2858
+#define AFE_CONN063_0 0x2860
+#define AFE_CONN063_1 0x2864
+#define AFE_CONN063_2 0x2868
+#define AFE_CONN063_4 0x2870
+#define AFE_CONN063_6 0x2878
+#define AFE_CONN066_0 0x28c0
+#define AFE_CONN066_1 0x28c4
+#define AFE_CONN066_2 0x28c8
+#define AFE_CONN066_4 0x28d0
+#define AFE_CONN066_6 0x28d8
+#define AFE_CONN067_0 0x28e0
+#define AFE_CONN067_1 0x28e4
+#define AFE_CONN067_2 0x28e8
+#define AFE_CONN067_4 0x28f0
+#define AFE_CONN067_6 0x28f8
+#define AFE_CONN068_0 0x2900
+#define AFE_CONN068_1 0x2904
+#define AFE_CONN068_2 0x2908
+#define AFE_CONN068_4 0x2910
+#define AFE_CONN068_6 0x2918
+#define AFE_CONN069_0 0x2920
+#define AFE_CONN069_1 0x2924
+#define AFE_CONN069_2 0x2928
+#define AFE_CONN069_4 0x2930
+#define AFE_CONN069_6 0x2938
+#define AFE_CONN096_0 0x2c80
+#define AFE_CONN096_1 0x2c84
+#define AFE_CONN096_2 0x2c88
+#define AFE_CONN096_4 0x2c90
+#define AFE_CONN096_6 0x2c98
+#define AFE_CONN097_0 0x2ca0
+#define AFE_CONN097_1 0x2ca4
+#define AFE_CONN097_2 0x2ca8
+#define AFE_CONN097_4 0x2cb0
+#define AFE_CONN097_6 0x2cb8
+#define AFE_CONN098_0 0x2cc0
+#define AFE_CONN098_1 0x2cc4
+#define AFE_CONN098_2 0x2cc8
+#define AFE_CONN098_4 0x2cd0
+#define AFE_CONN098_6 0x2cd8
+#define AFE_CONN099_0 0x2ce0
+#define AFE_CONN099_1 0x2ce4
+#define AFE_CONN099_2 0x2ce8
+#define AFE_CONN099_4 0x2cf0
+#define AFE_CONN099_6 0x2cf8
+#define AFE_CONN100_0 0x2d00
+#define AFE_CONN100_1 0x2d04
+#define AFE_CONN100_2 0x2d08
+#define AFE_CONN100_4 0x2d10
+#define AFE_CONN100_6 0x2d18
+#define AFE_CONN108_0 0x2e00
+#define AFE_CONN108_1 0x2e04
+#define AFE_CONN108_2 0x2e08
+#define AFE_CONN108_4 0x2e10
+#define AFE_CONN108_6 0x2e18
+#define AFE_CONN109_0 0x2e20
+#define AFE_CONN109_1 0x2e24
+#define AFE_CONN109_2 0x2e28
+#define AFE_CONN109_4 0x2e30
+#define AFE_CONN109_6 0x2e38
+#define AFE_CONN110_0 0x2e40
+#define AFE_CONN110_1 0x2e44
+#define AFE_CONN110_2 0x2e48
+#define AFE_CONN110_4 0x2e50
+#define AFE_CONN110_6 0x2e58
+#define AFE_CONN111_0 0x2e60
+#define AFE_CONN111_1 0x2e64
+#define AFE_CONN111_2 0x2e68
+#define AFE_CONN111_4 0x2e70
+#define AFE_CONN111_6 0x2e78
+#define AFE_CONN116_0 0x2f00
+#define AFE_CONN116_1 0x2f04
+#define AFE_CONN116_2 0x2f08
+#define AFE_CONN116_4 0x2f10
+#define AFE_CONN116_6 0x2f18
+#define AFE_CONN117_0 0x2f20
+#define AFE_CONN117_1 0x2f24
+#define AFE_CONN117_2 0x2f28
+#define AFE_CONN117_4 0x2f30
+#define AFE_CONN117_6 0x2f38
+#define AFE_CONN118_0 0x2f40
+#define AFE_CONN118_1 0x2f44
+#define AFE_CONN118_2 0x2f48
+#define AFE_CONN118_4 0x2f50
+#define AFE_CONN118_6 0x2f58
+#define AFE_CONN119_0 0x2f60
+#define AFE_CONN119_1 0x2f64
+#define AFE_CONN119_2 0x2f68
+#define AFE_CONN119_4 0x2f70
+#define AFE_CONN119_6 0x2f78
+#define AFE_CONN120_0 0x2f80
+#define AFE_CONN120_1 0x2f84
+#define AFE_CONN120_2 0x2f88
+#define AFE_CONN120_4 0x2f90
+#define AFE_CONN120_6 0x2f98
+#define AFE_CONN121_0 0x2fa0
+#define AFE_CONN121_1 0x2fa4
+#define AFE_CONN121_2 0x2fa8
+#define AFE_CONN121_4 0x2fb0
+#define AFE_CONN121_6 0x2fb8
+#define AFE_CONN122_0 0x2fc0
+#define AFE_CONN122_1 0x2fc4
+#define AFE_CONN122_2 0x2fc8
+#define AFE_CONN122_4 0x2fd0
+#define AFE_CONN122_6 0x2fd8
+#define AFE_CONN123_0 0x2fe0
+#define AFE_CONN123_1 0x2fe4
+#define AFE_CONN123_2 0x2fe8
+#define AFE_CONN123_4 0x2ff0
+#define AFE_CONN123_6 0x2ff8
+#define AFE_CONN180_0 0x3700
+#define AFE_CONN180_1 0x3704
+#define AFE_CONN180_2 0x3708
+#define AFE_CONN180_4 0x3710
+#define AFE_CONN180_6 0x3718
+#define AFE_CONN181_0 0x3720
+#define AFE_CONN181_1 0x3724
+#define AFE_CONN181_2 0x3728
+#define AFE_CONN181_4 0x3730
+#define AFE_CONN181_6 0x3738
+#define AFE_CONN182_0 0x3740
+#define AFE_CONN182_1 0x3744
+#define AFE_CONN182_2 0x3748
+#define AFE_CONN182_4 0x3750
+#define AFE_CONN182_6 0x3758
+#define AFE_CONN183_0 0x3760
+#define AFE_CONN183_1 0x3764
+#define AFE_CONN183_2 0x3768
+#define AFE_CONN183_4 0x3770
+#define AFE_CONN183_6 0x3778
+#define AFE_CONN184_0 0x3780
+#define AFE_CONN184_1 0x3784
+#define AFE_CONN184_2 0x3788
+#define AFE_CONN184_4 0x3790
+#define AFE_CONN184_6 0x3798
+#define AFE_CONN185_0 0x37a0
+#define AFE_CONN185_1 0x37a4
+#define AFE_CONN185_2 0x37a8
+#define AFE_CONN185_4 0x37b0
+#define AFE_CONN185_6 0x37b8
+#define AFE_CONN186_0 0x37c0
+#define AFE_CONN186_1 0x37c4
+#define AFE_CONN186_2 0x37c8
+#define AFE_CONN186_4 0x37d0
+#define AFE_CONN186_6 0x37d8
+#define AFE_CONN187_0 0x37e0
+#define AFE_CONN187_1 0x37e4
+#define AFE_CONN187_2 0x37e8
+#define AFE_CONN187_4 0x37f0
+#define AFE_CONN187_6 0x37f8
+#define AFE_CONN188_0 0x3800
+#define AFE_CONN188_1 0x3804
+#define AFE_CONN188_2 0x3808
+#define AFE_CONN188_4 0x3810
+#define AFE_CONN188_6 0x3818
+#define AFE_CONN189_0 0x3820
+#define AFE_CONN189_1 0x3824
+#define AFE_CONN189_2 0x3828
+#define AFE_CONN189_4 0x3830
+#define AFE_CONN189_6 0x3838
+#define AFE_CONN_MON_CFG 0x4080
+#define AFE_CONN_MON0 0x4084
+#define AFE_CONN_MON1 0x4088
+#define AFE_CONN_MON2 0x408c
+#define AFE_CONN_MON3 0x4090
+#define AFE_CONN_MON4 0x4094
+#define AFE_CONN_MON5 0x4098
+#define AFE_CONN_RS_0 0x40a0
+#define AFE_CONN_RS_1 0x40a4
+#define AFE_CONN_RS_2 0x40a8
+#define AFE_CONN_RS_3 0x40ac
+#define AFE_CONN_RS_5 0x40b4
+#define AFE_CONN_DI_0 0x40c0
+#define AFE_CONN_DI_1 0x40c4
+#define AFE_CONN_DI_2 0x40c8
+#define AFE_CONN_DI_3 0x40cc
+#define AFE_CONN_DI_5 0x40d4
+#define AFE_CONN_16BIT_0 0x40e0
+#define AFE_CONN_16BIT_1 0x40e4
+#define AFE_CONN_16BIT_2 0x40e8
+#define AFE_CONN_16BIT_3 0x40ec
+#define AFE_CONN_16BIT_5 0x40f4
+#define AFE_CONN_24BIT_0 0x4100
+#define AFE_CONN_24BIT_1 0x4104
+#define AFE_CONN_24BIT_2 0x4108
+#define AFE_CONN_24BIT_3 0x410c
+#define AFE_CONN_24BIT_5 0x4114
+#define AFE_CONN_TOP_IP_VERSION 0x4120
+#define AFE_CBIP_CFG0 0x4380
+#define AFE_CBIP_SLV_DECODER_MON0 0x4384
+#define AFE_CBIP_SLV_DECODER_MON1 0x4388
+#define AFE_CBIP_SLV_MUX_MON_CFG 0x438c
+#define AFE_CBIP_SLV_MUX_MON0 0x4390
+#define AFE_CBIP_SLV_MUX_MON1 0x4394
+#define AFE_MEMIF_IP_VERSION 0x4398
+#define AFE_MEMIF_CON0 0x4400
+#define AFE_MEMIF_RD_MON 0x4408
+#define AFE_MEMIF_WR_MON 0x440c
+#define AFE_MEMIF_CFG_MON0 0x4410
+#define AFE_BUS_CFG0 0x4414
+#define AFE_BUS_MON1 0x4418
+#define AFE_BUS_MON2 0x441c
+#define AFE_MEMIF_ONE_HEART 0x4420
+#define AFE_DL0_BASE_MSB 0x4440
+#define AFE_DL0_BASE 0x4444
+#define AFE_DL0_CUR_MSB 0x4448
+#define AFE_DL0_CUR 0x444c
+#define AFE_DL0_END_MSB 0x4450
+#define AFE_DL0_END 0x4454
+#define AFE_DL0_RCH_MON 0x4458
+#define AFE_DL0_LCH_MON 0x445c
+#define AFE_DL0_CON0 0x4460
+#define AFE_DL0_MON0 0x4464
+#define AFE_DL0_MEM_UP_MSB 0x4468
+#define AFE_DL0_MEM_UP 0x446c
+#define AFE_DL1_BASE_MSB 0x4470
+#define AFE_DL1_BASE 0x4474
+#define AFE_DL1_CUR_MSB 0x4478
+#define AFE_DL1_CUR 0x447c
+#define AFE_DL1_END_MSB 0x4480
+#define AFE_DL1_END 0x4484
+#define AFE_DL1_RCH_MON 0x4488
+#define AFE_DL1_LCH_MON 0x448c
+#define AFE_DL1_CON0 0x4490
+#define AFE_DL1_MON0 0x4494
+#define AFE_DL1_MEM_UP_MSB 0x4498
+#define AFE_DL1_MEM_UP 0x449c
+#define AFE_DL2_BASE_MSB 0x44a0
+#define AFE_DL2_BASE 0x44a4
+#define AFE_DL2_CUR_MSB 0x44a8
+#define AFE_DL2_CUR 0x44ac
+#define AFE_DL2_END_MSB 0x44b0
+#define AFE_DL2_END 0x44b4
+#define AFE_DL2_RCH_MON 0x44b8
+#define AFE_DL2_LCH_MON 0x44bc
+#define AFE_DL2_CON0 0x44c0
+#define AFE_DL2_MON0 0x44c4
+#define AFE_DL2_MEM_UP_MSB 0x44c8
+#define AFE_DL2_MEM_UP 0x44cc
+#define AFE_DL3_BASE_MSB 0x44d0
+#define AFE_DL3_BASE 0x44d4
+#define AFE_DL3_CUR_MSB 0x44d8
+#define AFE_DL3_CUR 0x44dc
+#define AFE_DL3_END_MSB 0x44e0
+#define AFE_DL3_END 0x44e4
+#define AFE_DL3_RCH_MON 0x44e8
+#define AFE_DL3_LCH_MON 0x44ec
+#define AFE_DL3_CON0 0x44f0
+#define AFE_DL3_MON0 0x44f4
+#define AFE_DL3_MEM_UP_MSB 0x44f8
+#define AFE_DL3_MEM_UP 0x44fc
+#define AFE_DL4_BASE_MSB 0x4500
+#define AFE_DL4_BASE 0x4504
+#define AFE_DL4_CUR_MSB 0x4508
+#define AFE_DL4_CUR 0x450c
+#define AFE_DL4_END_MSB 0x4510
+#define AFE_DL4_END 0x4514
+#define AFE_DL4_RCH_MON 0x4518
+#define AFE_DL4_LCH_MON 0x451c
+#define AFE_DL4_CON0 0x4520
+#define AFE_DL4_MON0 0x4524
+#define AFE_DL4_MEM_UP_MSB 0x4528
+#define AFE_DL4_MEM_UP 0x452c
+#define AFE_DL5_BASE_MSB 0x4530
+#define AFE_DL5_BASE 0x4534
+#define AFE_DL5_CUR_MSB 0x4538
+#define AFE_DL5_CUR 0x453c
+#define AFE_DL5_END_MSB 0x4540
+#define AFE_DL5_END 0x4544
+#define AFE_DL5_RCH_MON 0x4548
+#define AFE_DL5_LCH_MON 0x454c
+#define AFE_DL5_CON0 0x4550
+#define AFE_DL5_MON0 0x4554
+#define AFE_DL5_MEM_UP_MSB 0x4558
+#define AFE_DL5_MEM_UP 0x455c
+#define AFE_DL6_BASE_MSB 0x4560
+#define AFE_DL6_BASE 0x4564
+#define AFE_DL6_CUR_MSB 0x4568
+#define AFE_DL6_CUR 0x456c
+#define AFE_DL6_END_MSB 0x4570
+#define AFE_DL6_END 0x4574
+#define AFE_DL6_RCH_MON 0x4578
+#define AFE_DL6_LCH_MON 0x457c
+#define AFE_DL6_CON0 0x4580
+#define AFE_DL6_MON0 0x4584
+#define AFE_DL6_MEM_UP_MSB 0x4588
+#define AFE_DL6_MEM_UP 0x458c
+#define AFE_DL7_BASE_MSB 0x4590
+#define AFE_DL7_BASE 0x4594
+#define AFE_DL7_CUR_MSB 0x4598
+#define AFE_DL7_CUR 0x459c
+#define AFE_DL7_END_MSB 0x45a0
+#define AFE_DL7_END 0x45a4
+#define AFE_DL7_RCH_MON 0x45a8
+#define AFE_DL7_LCH_MON 0x45ac
+#define AFE_DL7_CON0 0x45b0
+#define AFE_DL7_MON0 0x45b4
+#define AFE_DL7_MEM_UP_MSB 0x45b8
+#define AFE_DL7_MEM_UP 0x45bc
+#define AFE_DL8_BASE_MSB 0x45c0
+#define AFE_DL8_BASE 0x45c4
+#define AFE_DL8_CUR_MSB 0x45c8
+#define AFE_DL8_CUR 0x45cc
+#define AFE_DL8_END_MSB 0x45d0
+#define AFE_DL8_END 0x45d4
+#define AFE_DL8_RCH_MON 0x45d8
+#define AFE_DL8_LCH_MON 0x45dc
+#define AFE_DL8_CON0 0x45e0
+#define AFE_DL8_MON0 0x45e4
+#define AFE_DL8_MEM_UP_MSB 0x45e8
+#define AFE_DL8_MEM_UP 0x45ec
+#define AFE_DL_24CH_BASE_MSB 0x4620
+#define AFE_DL_24CH_BASE 0x4624
+#define AFE_DL_24CH_CUR_MSB 0x4628
+#define AFE_DL_24CH_CUR 0x462c
+#define AFE_DL_24CH_END_MSB 0x4630
+#define AFE_DL_24CH_END 0x4634
+#define AFE_DL_24CH_CON0 0x4640
+#define AFE_DL_24CH_MON0 0x4644
+#define AFE_DL_24CH_MEM_UP_MSB 0x4648
+#define AFE_DL_24CH_MEM_UP 0x464c
+#define AFE_DL23_BASE_MSB 0x4680
+#define AFE_DL23_BASE 0x4684
+#define AFE_DL23_CUR_MSB 0x4688
+#define AFE_DL23_CUR 0x468c
+#define AFE_DL23_END_MSB 0x4690
+#define AFE_DL23_END 0x4694
+#define AFE_DL23_RCH_MON 0x4698
+#define AFE_DL23_LCH_MON 0x469c
+#define AFE_DL23_CON0 0x46a0
+#define AFE_DL23_MON0 0x46a4
+#define AFE_DL23_MEM_UP_MSB 0x46a8
+#define AFE_DL23_MEM_UP 0x46ac
+#define AFE_DL24_BASE_MSB 0x46b0
+#define AFE_DL24_BASE 0x46b4
+#define AFE_DL24_CUR_MSB 0x46b8
+#define AFE_DL24_CUR 0x46bc
+#define AFE_DL24_END_MSB 0x46c0
+#define AFE_DL24_END 0x46c4
+#define AFE_DL24_RCH_MON 0x46c8
+#define AFE_DL24_LCH_MON 0x46cc
+#define AFE_DL24_CON0 0x46d0
+#define AFE_DL24_MON0 0x46d4
+#define AFE_DL24_MEM_UP_MSB 0x46d8
+#define AFE_DL24_MEM_UP 0x46dc
+#define AFE_DL25_BASE_MSB 0x46e0
+#define AFE_DL25_BASE 0x46e4
+#define AFE_DL25_CUR_MSB 0x46e8
+#define AFE_DL25_CUR 0x46ec
+#define AFE_DL25_END_MSB 0x46f0
+#define AFE_DL25_END 0x46f4
+#define AFE_DL25_RCH_MON 0x46f8
+#define AFE_DL25_LCH_MON 0x46fc
+#define AFE_DL25_CON0 0x4700
+#define AFE_DL25_MON0 0x4704
+#define AFE_DL25_MEM_UP_MSB 0x4708
+#define AFE_DL25_MEM_UP 0x470c
+#define AFE_VUL0_BASE_MSB 0x4d60
+#define AFE_VUL0_BASE 0x4d64
+#define AFE_VUL0_CUR_MSB 0x4d68
+#define AFE_VUL0_CUR 0x4d6c
+#define AFE_VUL0_END_MSB 0x4d70
+#define AFE_VUL0_END 0x4d74
+#define AFE_VUL0_RCH_MON 0x4d78
+#define AFE_VUL0_LCH_MON 0x4d7c
+#define AFE_VUL0_CON0 0x4d80
+#define AFE_VUL0_MON0 0x4d84
+#define AFE_VUL1_BASE_MSB 0x4d90
+#define AFE_VUL1_BASE 0x4d94
+#define AFE_VUL1_CUR_MSB 0x4d98
+#define AFE_VUL1_CUR 0x4d9c
+#define AFE_VUL1_END_MSB 0x4da0
+#define AFE_VUL1_END 0x4da4
+#define AFE_VUL1_RCH_MON 0x4da8
+#define AFE_VUL1_LCH_MON 0x4dac
+#define AFE_VUL1_CON0 0x4db0
+#define AFE_VUL1_MON0 0x4db4
+#define AFE_VUL2_BASE_MSB 0x4dc0
+#define AFE_VUL2_BASE 0x4dc4
+#define AFE_VUL2_CUR_MSB 0x4dc8
+#define AFE_VUL2_CUR 0x4dcc
+#define AFE_VUL2_END_MSB 0x4dd0
+#define AFE_VUL2_END 0x4dd4
+#define AFE_VUL2_RCH_MON 0x4dd8
+#define AFE_VUL2_LCH_MON 0x4ddc
+#define AFE_VUL2_CON0 0x4de0
+#define AFE_VUL2_MON0 0x4de4
+#define AFE_VUL3_BASE_MSB 0x4df0
+#define AFE_VUL3_BASE 0x4df4
+#define AFE_VUL3_CUR_MSB 0x4df8
+#define AFE_VUL3_CUR 0x4dfc
+#define AFE_VUL3_END_MSB 0x4e00
+#define AFE_VUL3_END 0x4e04
+#define AFE_VUL3_RCH_MON 0x4e08
+#define AFE_VUL3_LCH_MON 0x4e0c
+#define AFE_VUL3_CON0 0x4e10
+#define AFE_VUL3_MON0 0x4e14
+#define AFE_VUL4_BASE_MSB 0x4e20
+#define AFE_VUL4_BASE 0x4e24
+#define AFE_VUL4_CUR_MSB 0x4e28
+#define AFE_VUL4_CUR 0x4e2c
+#define AFE_VUL4_END_MSB 0x4e30
+#define AFE_VUL4_END 0x4e34
+#define AFE_VUL4_RCH_MON 0x4e38
+#define AFE_VUL4_LCH_MON 0x4e3c
+#define AFE_VUL4_CON0 0x4e40
+#define AFE_VUL4_MON0 0x4e44
+#define AFE_VUL5_BASE_MSB 0x4e50
+#define AFE_VUL5_BASE 0x4e54
+#define AFE_VUL5_CUR_MSB 0x4e58
+#define AFE_VUL5_CUR 0x4e5c
+#define AFE_VUL5_END_MSB 0x4e60
+#define AFE_VUL5_END 0x4e64
+#define AFE_VUL5_RCH_MON 0x4e68
+#define AFE_VUL5_LCH_MON 0x4e6c
+#define AFE_VUL5_CON0 0x4e70
+#define AFE_VUL5_MON0 0x4e74
+#define AFE_VUL6_BASE_MSB 0x4e80
+#define AFE_VUL6_BASE 0x4e84
+#define AFE_VUL6_CUR_MSB 0x4e88
+#define AFE_VUL6_CUR 0x4e8c
+#define AFE_VUL6_END_MSB 0x4e90
+#define AFE_VUL6_END 0x4e94
+#define AFE_VUL6_RCH_MON 0x4e98
+#define AFE_VUL6_LCH_MON 0x4e9c
+#define AFE_VUL6_CON0 0x4ea0
+#define AFE_VUL6_MON0 0x4ea4
+#define AFE_VUL7_BASE_MSB 0x4eb0
+#define AFE_VUL7_BASE 0x4eb4
+#define AFE_VUL7_CUR_MSB 0x4eb8
+#define AFE_VUL7_CUR 0x4ebc
+#define AFE_VUL7_END_MSB 0x4ec0
+#define AFE_VUL7_END 0x4ec4
+#define AFE_VUL7_RCH_MON 0x4ec8
+#define AFE_VUL7_LCH_MON 0x4ecc
+#define AFE_VUL7_CON0 0x4ed0
+#define AFE_VUL7_MON0 0x4ed4
+#define AFE_VUL8_BASE_MSB 0x4ee0
+#define AFE_VUL8_BASE 0x4ee4
+#define AFE_VUL8_CUR_MSB 0x4ee8
+#define AFE_VUL8_CUR 0x4eec
+#define AFE_VUL8_END_MSB 0x4ef0
+#define AFE_VUL8_END 0x4ef4
+#define AFE_VUL8_RCH_MON 0x4ef8
+#define AFE_VUL8_LCH_MON 0x4efc
+#define AFE_VUL8_CON0 0x4f00
+#define AFE_VUL8_MON0 0x4f04
+#define AFE_VUL9_BASE_MSB 0x4f10
+#define AFE_VUL9_BASE 0x4f14
+#define AFE_VUL9_CUR_MSB 0x4f18
+#define AFE_VUL9_CUR 0x4f1c
+#define AFE_VUL9_END_MSB 0x4f20
+#define AFE_VUL9_END 0x4f24
+#define AFE_VUL9_RCH_MON 0x4f28
+#define AFE_VUL9_LCH_MON 0x4f2c
+#define AFE_VUL9_CON0 0x4f30
+#define AFE_VUL9_MON0 0x4f34
+#define AFE_VUL10_BASE_MSB 0x4f40
+#define AFE_VUL10_BASE 0x4f44
+#define AFE_VUL10_CUR_MSB 0x4f48
+#define AFE_VUL10_CUR 0x4f4c
+#define AFE_VUL10_END_MSB 0x4f50
+#define AFE_VUL10_END 0x4f54
+#define AFE_VUL10_RCH_MON 0x4f58
+#define AFE_VUL10_LCH_MON 0x4f5c
+#define AFE_VUL10_CON0 0x4f60
+#define AFE_VUL10_MON0 0x4f64
+#define AFE_VUL24_BASE_MSB 0x4fa0
+#define AFE_VUL24_BASE 0x4fa4
+#define AFE_VUL24_CUR_MSB 0x4fa8
+#define AFE_VUL24_CUR 0x4fac
+#define AFE_VUL24_END_MSB 0x4fb0
+#define AFE_VUL24_END 0x4fb4
+#define AFE_VUL24_CON0 0x4fb8
+#define AFE_VUL24_MON0 0x4fbc
+#define AFE_VUL25_BASE_MSB 0x4fc0
+#define AFE_VUL25_BASE 0x4fc4
+#define AFE_VUL25_CUR_MSB 0x4fc8
+#define AFE_VUL25_CUR 0x4fcc
+#define AFE_VUL25_END_MSB 0x4fd0
+#define AFE_VUL25_END 0x4fd4
+#define AFE_VUL25_CON0 0x4fd8
+#define AFE_VUL25_MON0 0x4fdc
+#define AFE_VUL_CM0_BASE_MSB 0x51c0
+#define AFE_VUL_CM0_BASE 0x51c4
+#define AFE_VUL_CM0_CUR_MSB 0x51c8
+#define AFE_VUL_CM0_CUR 0x51cc
+#define AFE_VUL_CM0_END_MSB 0x51d0
+#define AFE_VUL_CM0_END 0x51d4
+#define AFE_VUL_CM0_CON0 0x51d8
+#define AFE_VUL_CM0_MON0 0x51dc
+#define AFE_VUL_CM1_BASE_MSB 0x51e0
+#define AFE_VUL_CM1_BASE 0x51e4
+#define AFE_VUL_CM1_CUR_MSB 0x51e8
+#define AFE_VUL_CM1_CUR 0x51ec
+#define AFE_VUL_CM1_END_MSB 0x51f0
+#define AFE_VUL_CM1_END 0x51f4
+#define AFE_VUL_CM1_CON0 0x51f8
+#define AFE_VUL_CM1_MON0 0x51fc
+#define AFE_ETDM_IN0_BASE_MSB 0x5220
+#define AFE_ETDM_IN0_BASE 0x5224
+#define AFE_ETDM_IN0_CUR_MSB 0x5228
+#define AFE_ETDM_IN0_CUR 0x522c
+#define AFE_ETDM_IN0_END_MSB 0x5230
+#define AFE_ETDM_IN0_END 0x5234
+#define AFE_ETDM_IN0_CON0 0x5238
+#define AFE_ETDM_IN1_BASE_MSB 0x5240
+#define AFE_ETDM_IN1_BASE 0x5244
+#define AFE_ETDM_IN1_CUR_MSB 0x5248
+#define AFE_ETDM_IN1_CUR 0x524c
+#define AFE_ETDM_IN1_END_MSB 0x5250
+#define AFE_ETDM_IN1_END 0x5254
+#define AFE_ETDM_IN1_CON0 0x5258
+#define AFE_HDMI_OUT_BASE_MSB 0x5360
+#define AFE_HDMI_OUT_BASE 0x5364
+#define AFE_HDMI_OUT_CUR_MSB 0x5368
+#define AFE_HDMI_OUT_CUR 0x536c
+#define AFE_HDMI_OUT_END_MSB 0x5370
+#define AFE_HDMI_OUT_END 0x5374
+#define AFE_HDMI_OUT_CON0 0x5378
+#define AFE_HDMI_OUT_MON0 0x537c
+#define AFE_VUL24_RCH_MON 0x53e0
+#define AFE_VUL24_LCH_MON 0x53e4
+#define AFE_VUL25_RCH_MON 0x53e8
+#define AFE_VUL25_LCH_MON 0x53ec
+#define AFE_VUL_CM0_RCH_MON 0x5458
+#define AFE_VUL_CM0_LCH_MON 0x545c
+#define AFE_VUL_CM1_RCH_MON 0x5460
+#define AFE_VUL_CM1_LCH_MON 0x5464
+#define AFE_DL_24CH_CH0_MON 0x5504
+#define AFE_DL_24CH_CH1_MON 0x5508
+#define AFE_DL_24CH_CH2_MON 0x550c
+#define AFE_DL_24CH_CH3_MON 0x5510
+#define AFE_DL_24CH_CH4_MON 0x5514
+#define AFE_DL_24CH_CH5_MON 0x5518
+#define AFE_DL_24CH_CH6_MON 0x551c
+#define AFE_DL_24CH_CH7_MON 0x5520
+#define AFE_HDMI_OUT_MEM_UP_MSB 0x55b0
+#define AFE_HDMI_OUT_MEM_UP 0x55b4
+#define AFE_SRAM_BOUND 0x5620
+#define AFE_SECURE_CON0 0x5624
+#define AFE_SECURE_CON1 0x5628
+#define AFE_SE_SECURE_CON0 0x5630
+#define AFE_SE_SECURE_CON1 0x5634
+#define AFE_SE_SECURE_CON2 0x5638
+#define AFE_SE_SECURE_CON3 0x563c
+#define AFE_SE_PROT_SIDEBAND0 0x5640
+#define AFE_SE_PROT_SIDEBAND1 0x5644
+#define AFE_SE_PROT_SIDEBAND2 0x5648
+#define AFE_SE_PROT_SIDEBAND3 0x564c
+#define AFE_SE_DOMAIN_SIDEBAND0 0x5650
+#define AFE_SE_DOMAIN_SIDEBAND1 0x5654
+#define AFE_SE_DOMAIN_SIDEBAND2 0x5658
+#define AFE_SE_DOMAIN_SIDEBAND3 0x565c
+#define AFE_SE_DOMAIN_SIDEBAND4 0x5660
+#define AFE_SE_DOMAIN_SIDEBAND5 0x5664
+#define AFE_SE_DOMAIN_SIDEBAND6 0x5668
+#define AFE_SE_DOMAIN_SIDEBAND7 0x566c
+#define AFE_SE_DOMAIN_SIDEBAND8 0x5670
+#define AFE_SE_DOMAIN_SIDEBAND9 0x5674
+#define AFE_PROT_SIDEBAND0_MON 0x5678
+#define AFE_PROT_SIDEBAND1_MON 0x567c
+#define AFE_PROT_SIDEBAND2_MON 0x5680
+#define AFE_PROT_SIDEBAND3_MON 0x5684
+#define AFE_DOMAIN_SIDEBAND0_MON 0x5688
+#define AFE_DOMAIN_SIDEBAND1_MON 0x568c
+#define AFE_DOMAIN_SIDEBAND2_MON 0x5690
+#define AFE_DOMAIN_SIDEBAND3_MON 0x5694
+#define AFE_DOMAIN_SIDEBAND4_MON 0x5698
+#define AFE_DOMAIN_SIDEBAND5_MON 0x569c
+#define AFE_DOMAIN_SIDEBAND6_MON 0x56a0
+#define AFE_DOMAIN_SIDEBAND7_MON 0x56a4
+#define AFE_DOMAIN_SIDEBAND8_MON 0x56a8
+#define AFE_DOMAIN_SIDEBAND9_MON 0x56ac
+#define AFE_SECURE_CONN0 0x56b0
+#define AFE_SECURE_CONN_ETDM0 0x56b4
+#define AFE_SECURE_CONN_ETDM1 0x56b8
+#define AFE_SECURE_CONN_ETDM2 0x56bc
+#define AFE_SECURE_SRAM_CON0 0x56c0
+#define AFE_SECURE_SRAM_CON1 0x56c4
+#define AFE_SE_CONN_INPUT_MASK0 0x56d0
+#define AFE_SE_CONN_INPUT_MASK1 0x56d4
+#define AFE_SE_CONN_INPUT_MASK2 0x56d8
+#define AFE_SE_CONN_INPUT_MASK3 0x56dc
+#define AFE_SE_CONN_INPUT_MASK4 0x56e0
+#define AFE_SE_CONN_INPUT_MASK5 0x56e4
+#define AFE_SE_CONN_INPUT_MASK6 0x56e8
+#define AFE_SE_CONN_INPUT_MASK7 0x56ec
+#define AFE_NON_SE_CONN_INPUT_MASK0 0x56f0
+#define AFE_NON_SE_CONN_INPUT_MASK1 0x56f4
+#define AFE_NON_SE_CONN_INPUT_MASK2 0x56f8
+#define AFE_NON_SE_CONN_INPUT_MASK3 0x56fc
+#define AFE_NON_SE_CONN_INPUT_MASK4 0x5700
+#define AFE_NON_SE_CONN_INPUT_MASK5 0x5704
+#define AFE_NON_SE_CONN_INPUT_MASK6 0x5708
+#define AFE_NON_SE_CONN_INPUT_MASK7 0x570c
+#define AFE_SE_CONN_OUTPUT_SEL0 0x5710
+#define AFE_SE_CONN_OUTPUT_SEL1 0x5714
+#define AFE_SE_CONN_OUTPUT_SEL2 0x5718
+#define AFE_SE_CONN_OUTPUT_SEL3 0x571c
+#define AFE_SE_CONN_OUTPUT_SEL4 0x5720
+#define AFE_SE_CONN_OUTPUT_SEL5 0x5724
+#define AFE_SE_CONN_OUTPUT_SEL6 0x5728
+#define AFE_SE_CONN_OUTPUT_SEL7 0x572c
+#define AFE_PCM0_INTF_CON1_MASK_MON 0x5730
+#define AFE_CONNSYS_I2S_CON_MASK_MON 0x5738
+#define AFE_TDM_CON2_MASK_MON 0x5744
+#define AFE_MTKAIF0_CFG0_MASK_MON 0x574c
+#define AFE_MTKAIF1_CFG0_MASK_MON 0x5750
+#define AFE_ADDA_UL0_SRC_CON0_MASK_MON 0x5754
+#define AFE_ADDA_DMIC0_SRC_CON0_MASK_MON 0x5764
+#define AFE_ADDA_DMIC1_SRC_CON0_MASK_MON 0x5768
+#define AFE_MON_SECURE_CON0 0x5840
+#define AFE_SECURE_CONN_ETDM3 0x5850
+#define AFE_ASRC_NEW_CON0 0x7800
+#define AFE_ASRC_NEW_CON1 0x7804
+#define AFE_ASRC_NEW_CON2 0x7808
+#define AFE_ASRC_NEW_CON3 0x780c
+#define AFE_ASRC_NEW_CON4 0x7810
+#define AFE_ASRC_NEW_CON5 0x7814
+#define AFE_ASRC_NEW_CON6 0x7818
+#define AFE_ASRC_NEW_CON7 0x781c
+#define AFE_ASRC_NEW_CON8 0x7820
+#define AFE_ASRC_NEW_CON9 0x7824
+#define AFE_ASRC_NEW_CON10 0x7828
+#define AFE_ASRC_NEW_CON11 0x782c
+#define AFE_ASRC_NEW_CON12 0x7830
+#define AFE_ASRC_NEW_CON13 0x7834
+#define AFE_ASRC_NEW_CON14 0x7838
+#define AFE_ASRC_NEW_IP_VERSION 0x783c
+#define AFE_GASRC0_NEW_CON0 0x7840
+#define AFE_GASRC0_NEW_CON1 0x7844
+#define AFE_GASRC0_NEW_CON2 0x7848
+#define AFE_GASRC0_NEW_CON3 0x784c
+#define AFE_GASRC0_NEW_CON4 0x7850
+#define AFE_GASRC0_NEW_CON5 0x7854
+#define AFE_GASRC0_NEW_CON6 0x7858
+#define AFE_GASRC0_NEW_CON7 0x785c
+#define AFE_GASRC0_NEW_CON8 0x7860
+#define AFE_GASRC0_NEW_CON9 0x7864
+#define AFE_GASRC0_NEW_CON10 0x7868
+#define AFE_GASRC0_NEW_CON11 0x786c
+#define AFE_GASRC0_NEW_CON12 0x7870
+#define AFE_GASRC0_NEW_CON13 0x7874
+#define AFE_GASRC0_NEW_CON14 0x7878
+#define AFE_GASRC0_NEW_IP_VERSION 0x787c
+#define AFE_GASRC1_NEW_CON0 0x7880
+#define AFE_GASRC1_NEW_CON1 0x7884
+#define AFE_GASRC1_NEW_CON2 0x7888
+#define AFE_GASRC1_NEW_CON3 0x788c
+#define AFE_GASRC1_NEW_CON4 0x7890
+#define AFE_GASRC1_NEW_CON5 0x7894
+#define AFE_GASRC1_NEW_CON6 0x7898
+#define AFE_GASRC1_NEW_CON7 0x789c
+#define AFE_GASRC1_NEW_CON8 0x78a0
+#define AFE_GASRC1_NEW_CON9 0x78a4
+#define AFE_GASRC1_NEW_CON10 0x78a8
+#define AFE_GASRC1_NEW_CON11 0x78ac
+#define AFE_GASRC1_NEW_CON12 0x78b0
+#define AFE_GASRC1_NEW_CON13 0x78b4
+#define AFE_GASRC1_NEW_CON14 0x78b8
+#define AFE_GASRC1_NEW_IP_VERSION 0x78bc
+#define AFE_GASRC2_NEW_CON0 0x78c0
+#define AFE_GASRC2_NEW_CON1 0x78c4
+#define AFE_GASRC2_NEW_CON2 0x78c8
+#define AFE_GASRC2_NEW_CON3 0x78cc
+#define AFE_GASRC2_NEW_CON4 0x78d0
+#define AFE_GASRC2_NEW_CON5 0x78d4
+#define AFE_GASRC2_NEW_CON6 0x78d8
+#define AFE_GASRC2_NEW_CON7 0x78dc
+#define AFE_GASRC2_NEW_CON8 0x78e0
+#define AFE_GASRC2_NEW_CON9 0x78e4
+#define AFE_GASRC2_NEW_CON10 0x78e8
+#define AFE_GASRC2_NEW_CON11 0x78ec
+#define AFE_GASRC2_NEW_CON12 0x78f0
+#define AFE_GASRC2_NEW_CON13 0x78f4
+#define AFE_GASRC2_NEW_CON14 0x78f8
+#define AFE_GASRC2_NEW_IP_VERSION 0x78fc
+#define AFE_GASRC3_NEW_CON0 0x7900
+#define AFE_GASRC3_NEW_CON1 0x7904
+#define AFE_GASRC3_NEW_CON2 0x7908
+#define AFE_GASRC3_NEW_CON3 0x790c
+#define AFE_GASRC3_NEW_CON4 0x7910
+#define AFE_GASRC3_NEW_CON5 0x7914
+#define AFE_GASRC3_NEW_CON6 0x7918
+#define AFE_GASRC3_NEW_CON7 0x791c
+#define AFE_GASRC3_NEW_CON8 0x7920
+#define AFE_GASRC3_NEW_CON9 0x7924
+#define AFE_GASRC3_NEW_CON10 0x7928
+#define AFE_GASRC3_NEW_CON11 0x792c
+#define AFE_GASRC3_NEW_CON12 0x7930
+#define AFE_GASRC3_NEW_CON13 0x7934
+#define AFE_GASRC3_NEW_CON14 0x7938
+#define AFE_GASRC3_NEW_IP_VERSION 0x793c
+#define AFE_GASRC4_NEW_CON0 0x7940
+#define AFE_GASRC4_NEW_CON1 0x7944
+#define AFE_GASRC4_NEW_CON2 0x7948
+#define AFE_GASRC4_NEW_CON3 0x794c
+#define AFE_GASRC4_NEW_CON4 0x7950
+#define AFE_GASRC4_NEW_CON5 0x7954
+#define AFE_GASRC4_NEW_CON6 0x7958
+#define AFE_GASRC4_NEW_CON7 0x795c
+#define AFE_GASRC4_NEW_CON8 0x7960
+#define AFE_GASRC4_NEW_CON9 0x7964
+#define AFE_GASRC4_NEW_CON10 0x7968
+#define AFE_GASRC4_NEW_CON11 0x796c
+#define AFE_GASRC4_NEW_CON12 0x7970
+#define AFE_GASRC4_NEW_CON13 0x7974
+#define AFE_GASRC4_NEW_CON14 0x7978
+#define AFE_GASRC4_NEW_IP_VERSION 0x797c
+#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON0 0x9400
+#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON1 0x9404
+#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON2 0x9408
+#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON3 0x940c
+#define AFE_SOUNDWIRE_ULSRC_PHASE_CLK_CON4 0x9410
+#define AFE_SOUNDWIRE_ULSRC_PHASE_ENGEN_CON0 0x9414
+#define AFE_SOUNDWIRE_ULSRC_PHASE_ENGEN_CON1 0x9418
+#define AFE_SOUNDWIRE_ULSRC_PHASE_RST_CON0 0x941c
+#define AFE_IRQ_MCU_EN 0x9d00
+#define AFE_IRQ_MCU_DSP_EN 0x9d04
+#define AFE_IRQ_MCU_DSP2_EN 0x9d08
+#define AFE_IRQ_MCU_SCP_EN 0x9d0c
+#define AFE_CUSTOM_IRQ_MCU_EN 0x9d10
+#define AFE_CUSTOM_IRQ_MCU_DSP_EN 0x9d14
+#define AFE_CUSTOM_IRQ_MCU_DSP2_EN 0x9d18
+#define AFE_CUSTOM_IRQ_MCU_SCP_EN 0x9d1c
+#define AFE_IRQ_MCU_STATUS 0x9d20
+#define AFE_CUSTOM_IRQ_MCU_STATUS 0x9d24
+#define AFE_IRQ0_MCU_CFG0 0x9d40
+#define AFE_IRQ0_MCU_CFG1 0x9d44
+#define AFE_IRQ1_MCU_CFG0 0x9d48
+#define AFE_IRQ1_MCU_CFG1 0x9d4c
+#define AFE_IRQ2_MCU_CFG0 0x9d50
+#define AFE_IRQ2_MCU_CFG1 0x9d54
+#define AFE_IRQ3_MCU_CFG0 0x9d58
+#define AFE_IRQ3_MCU_CFG1 0x9d5c
+#define AFE_IRQ4_MCU_CFG0 0x9d60
+#define AFE_IRQ4_MCU_CFG1 0x9d64
+#define AFE_IRQ5_MCU_CFG0 0x9d68
+#define AFE_IRQ5_MCU_CFG1 0x9d6c
+#define AFE_IRQ6_MCU_CFG0 0x9d70
+#define AFE_IRQ6_MCU_CFG1 0x9d74
+#define AFE_IRQ7_MCU_CFG0 0x9d78
+#define AFE_IRQ7_MCU_CFG1 0x9d7c
+#define AFE_IRQ8_MCU_CFG0 0x9d80
+#define AFE_IRQ8_MCU_CFG1 0x9d84
+#define AFE_IRQ9_MCU_CFG0 0x9d88
+#define AFE_IRQ9_MCU_CFG1 0x9d8c
+#define AFE_IRQ10_MCU_CFG0 0x9d90
+#define AFE_IRQ10_MCU_CFG1 0x9d94
+#define AFE_IRQ11_MCU_CFG0 0x9d98
+#define AFE_IRQ11_MCU_CFG1 0x9d9c
+#define AFE_IRQ12_MCU_CFG0 0x9da0
+#define AFE_IRQ12_MCU_CFG1 0x9da4
+#define AFE_IRQ13_MCU_CFG0 0x9da8
+#define AFE_IRQ13_MCU_CFG1 0x9dac
+#define AFE_IRQ14_MCU_CFG0 0x9db0
+#define AFE_IRQ14_MCU_CFG1 0x9db4
+#define AFE_IRQ15_MCU_CFG0 0x9db8
+#define AFE_IRQ15_MCU_CFG1 0x9dbc
+#define AFE_IRQ16_MCU_CFG0 0x9dc0
+#define AFE_IRQ16_MCU_CFG1 0x9dc4
+#define AFE_IRQ17_MCU_CFG0 0x9dc8
+#define AFE_IRQ17_MCU_CFG1 0x9dcc
+#define AFE_IRQ18_MCU_CFG0 0x9dd0
+#define AFE_IRQ18_MCU_CFG1 0x9dd4
+#define AFE_IRQ19_MCU_CFG0 0x9dd8
+#define AFE_IRQ19_MCU_CFG1 0x9ddc
+#define AFE_IRQ20_MCU_CFG0 0x9de0
+#define AFE_IRQ20_MCU_CFG1 0x9de4
+#define AFE_IRQ21_MCU_CFG0 0x9de8
+#define AFE_IRQ21_MCU_CFG1 0x9dec
+#define AFE_IRQ22_MCU_CFG0 0x9df0
+#define AFE_IRQ22_MCU_CFG1 0x9df4
+#define AFE_IRQ23_MCU_CFG0 0x9df8
+#define AFE_IRQ23_MCU_CFG1 0x9dfc
+#define AFE_IRQ24_MCU_CFG0 0x9e00
+#define AFE_IRQ24_MCU_CFG1 0x9e04
+#define AFE_IRQ25_MCU_CFG0 0x9e08
+#define AFE_IRQ25_MCU_CFG1 0x9e0c
+#define AFE_IRQ26_MCU_CFG0 0x9e10
+#define AFE_IRQ26_MCU_CFG1 0x9e14
+#define AFE_CUSTOM_IRQ0_MCU_CFG0 0x9e68
+#define AFE_CUSTOM_IRQ22_MCU_CFG0 0x9ec8
+#define AFE_CUSTOM_IRQ22_MCU_CFG1 0x9ecc
+#define AFE_CUSTOM_IRQ23_MCU_CFG0 0x9ed0
+#define AFE_CUSTOM_IRQ23_MCU_CFG1 0x9ed4
+#define AFE_IRQ0_CNT_MON 0x9f10
+#define AFE_IRQ1_CNT_MON 0x9f14
+#define AFE_IRQ2_CNT_MON 0x9f18
+#define AFE_IRQ3_CNT_MON 0x9f1c
+#define AFE_IRQ4_CNT_MON 0x9f20
+#define AFE_IRQ5_CNT_MON 0x9f24
+#define AFE_IRQ6_CNT_MON 0x9f28
+#define AFE_IRQ7_CNT_MON 0x9f2c
+#define AFE_IRQ8_CNT_MON 0x9f30
+#define AFE_IRQ9_CNT_MON 0x9f34
+#define AFE_IRQ10_CNT_MON 0x9f38
+#define AFE_IRQ11_CNT_MON 0x9f3c
+#define AFE_IRQ12_CNT_MON 0x9f40
+#define AFE_IRQ13_CNT_MON 0x9f44
+#define AFE_IRQ14_CNT_MON 0x9f48
+#define AFE_IRQ15_CNT_MON 0x9f4c
+#define AFE_IRQ16_CNT_MON 0x9f50
+#define AFE_IRQ17_CNT_MON 0x9f54
+#define AFE_IRQ18_CNT_MON 0x9f58
+#define AFE_IRQ19_CNT_MON 0x9f5c
+#define AFE_IRQ20_CNT_MON 0x9f60
+#define AFE_IRQ21_CNT_MON 0x9f64
+#define AFE_IRQ22_CNT_MON 0x9f68
+#define AFE_IRQ23_CNT_MON 0x9f6c
+#define AFE_IRQ24_CNT_MON 0x9f70
+#define AFE_IRQ25_CNT_MON 0x9f74
+#define AFE_IRQ26_CNT_MON 0x9f78
+#define AFE_CUSTOM_IRQ0_CNT_MON 0x9f90
+#define AFE_CUSTOM_IRQ0_MCU_CFG1 0x9fdc
+#define AFE_IRQ_MCU_DSP3_EN 0xa000
+#define AFE_CUSTOM_IRQ_MCU_DSP3_EN 0xa004
+#define AFE_CUSTOM2_IRQ_MCU_EN 0xa008
+#define AFE_CUSTOM2_IRQ_MCU_DSP_EN 0xa00c
+#define AFE_CUSTOM2_IRQ_MCU_DSP2_EN 0xa010
+#define AFE_CUSTOM2_IRQ_MCU_DSP3_EN 0xa014
+#define AFE_CUSTOM2_IRQ_MCU_SCP_EN 0xa018
+#define AFE_IRQ_MCU_MON3 0xa01c
+#define AFE_IRQ_MCU_MON0 0xa024
+#define AFE_IRQ_MCU_MON1 0xa028
+#define AFE_IRQ_MCU_MON2 0xa02c
+#define AFE_CUSTOM2_IRQ_MISS_FLAG_MCU_MON 0xa034
+#define AFE_CUSTOM2_IRQ_DELAY_EN 0xa038
+#define AFE_CUSTOM2_IRQ_MCU_STATUS 0xa03c
+#define AFE_CUSTOM2_IRQ0_MCU_CFG0 0xa040
+#define AFE_CUSTOM2_IRQ0_MCU_CFG1 0xa044
+#define AFE_CUSTOM2_IRQ0_CNT_MON 0xa048
+#define AFE_CUSTOM2_IRQ0_MCU_DELAY_CNT_CFG0 0xa04c
+#define AFE_CUSTOM2_IRQ1_MCU_CFG0 0xa050
+#define AFE_CUSTOM2_IRQ1_MCU_CFG1 0xa054
+#define AFE_CUSTOM2_IRQ1_CNT_MON 0xa058
+#define AFE_CUSTOM2_IRQ1_MCU_DELAY_CNT_CFG0 0xa05c
+#define AFE_CUSTOM2_IRQ2_MCU_CFG0 0xa060
+#define AFE_CUSTOM2_IRQ2_MCU_CFG1 0xa064
+#define AFE_CUSTOM2_IRQ2_CNT_MON 0xa068
+#define AFE_CUSTOM2_IRQ2_MCU_DELAY_CNT_CFG0 0xa06c
+#define AFE_CUSTOM2_IRQ3_MCU_CFG0 0xa070
+#define AFE_CUSTOM2_IRQ3_MCU_CFG1 0xa074
+#define AFE_CUSTOM2_IRQ3_CNT_MON 0xa078
+#define AFE_CUSTOM2_IRQ3_MCU_DELAY_CNT_CFG0 0xa07c
+#define AFE_CUSTOM2_IRQ4_MCU_CFG0 0xa080
+#define AFE_CUSTOM2_IRQ4_MCU_CFG1 0xa084
+#define AFE_CUSTOM2_IRQ4_CNT_MON 0xa088
+#define AFE_CUSTOM2_IRQ4_MCU_DELAY_CNT_CFG0 0xa08c
+#define AFE_CUSTOM2_IRQ5_MCU_CFG0 0xa090
+#define AFE_CUSTOM2_IRQ5_MCU_CFG1 0xa094
+#define AFE_CUSTOM2_IRQ5_CNT_MON 0xa098
+#define AFE_CUSTOM2_IRQ5_MCU_DELAY_CNT_CFG0 0xa09c
+#define AFE_CUSTOM2_IRQ6_MCU_CFG0 0xa0a0
+#define AFE_CUSTOM2_IRQ6_MCU_CFG1 0xa0a4
+#define AFE_CUSTOM2_IRQ6_CNT_MON 0xa0a8
+#define AFE_CUSTOM2_IRQ6_MCU_DELAY_CNT_CFG0 0xa0ac
+#define AFE_CUSTOM2_IRQ7_MCU_CFG0 0xa0b0
+#define AFE_CUSTOM2_IRQ7_MCU_CFG1 0xa0b4
+#define AFE_CUSTOM2_IRQ7_CNT_MON 0xa0b8
+#define AFE_CUSTOM2_IRQ7_MCU_DELAY_CNT_CFG0 0xa0bc
+#define AFE_CUSTOM2_IRQ8_MCU_CFG0 0xa0c0
+#define AFE_CUSTOM2_IRQ8_MCU_CFG1 0xa0c4
+#define AFE_CUSTOM2_IRQ8_CNT_MON 0xa0c8
+#define AFE_CUSTOM2_IRQ8_MCU_DELAY_CNT_CFG0 0xa0cc
+#define AFE_CUSTOM2_IRQ9_MCU_CFG0 0xa0d0
+#define AFE_CUSTOM2_IRQ9_MCU_CFG1 0xa0d4
+#define AFE_CUSTOM2_IRQ9_CNT_MON 0xa0d8
+#define AFE_CUSTOM2_IRQ9_MCU_DELAY_CNT_CFG0 0xa0dc
+#define AFE_CUSTOM2_IRQ10_MCU_CFG0 0xa0e0
+#define AFE_CUSTOM2_IRQ10_MCU_CFG1 0xa0e4
+#define AFE_CUSTOM2_IRQ10_CNT_MON 0xa0e8
+#define AFE_CUSTOM2_IRQ10_MCU_DELAY_CNT_CFG0 0xa0ec
+#define AFE_CUSTOM2_IRQ11_MCU_CFG0 0xa0f0
+#define AFE_CUSTOM2_IRQ11_MCU_CFG1 0xa0f4
+#define AFE_CUSTOM2_IRQ11_CNT_MON 0xa0f8
+#define AFE_CUSTOM2_IRQ11_MCU_DELAY_CNT_CFG0 0xa0fc
+#define AFE_CUSTOM2_IRQ12_MCU_CFG0 0xa100
+#define AFE_CUSTOM2_IRQ12_MCU_CFG1 0xa104
+#define AFE_CUSTOM2_IRQ12_CNT_MON 0xa108
+#define AFE_CUSTOM2_IRQ12_MCU_DELAY_CNT_CFG0 0xa10c
+#define AFE_CUSTOM2_IRQ30_MCU_CFG0 0xa220
+#define AFE_CUSTOM2_IRQ30_MCU_CFG1 0xa224
+#define AFE_CUSTOM2_IRQ30_CNT_MON 0xa228
+#define AFE_CUSTOM2_IRQ30_MCU_DELAY_CNT_CFG0 0xa22c
+#define AFE_CUSTOM2_IRQ31_MCU_CFG0 0xa230
+#define AFE_CUSTOM2_IRQ31_MCU_CFG1 0xa234
+#define AFE_CUSTOM2_IRQ31_CNT_MON 0xa238
+#define AFE_CUSTOM2_IRQ31_MCU_DELAY_CNT_CFG0 0xa23c
+#define AFE_CUSTOM3_IRQ8_MCU_CFG0 0xa2c0
+#define AFE_CUSTOM3_IRQ8_MCU_CFG1 0xa2c4
+#define AFE_CUSTOM3_IRQ8_CNT_MON 0xa2c8
+#define AFE_CUSTOM3_IRQ8_MCU_DELAY_CNT_CFG0 0xa2cc
+#define AFE_CUSTOM3_IRQ9_MCU_CFG0 0xa2d0
+#define AFE_CUSTOM3_IRQ9_MCU_CFG1 0xa2d4
+#define AFE_CUSTOM3_IRQ9_CNT_MON 0xa2d8
+#define AFE_CUSTOM3_IRQ9_MCU_DELAY_CNT_CFG0 0xa2dc
+#define AFE_CUSTOM3_IRQ_MISS_FLAG_MCU_MON 0xa440
+#define AFE_CUSTOM3_IRQ_DELAY_EN 0xa444
+#define AFE_CUSTOM3_IRQ_MCU_STATUS 0xa448
+#define AFE_CUSTOM3_IRQ_MCU_EN 0xa44c
+#define AFE_CUSTOM3_IRQ_MCU_DSP_EN 0xa450
+#define AFE_CUSTOM3_IRQ_MCU_DSP2_EN 0xa454
+#define AFE_CUSTOM3_IRQ_MCU_DSP3_EN 0xa458
+#define AFE_CUSTOM3_IRQ_MCU_DSP_WLA_EN 0xa45c
+#define AFE_CUSTOM3_IRQ_MCU_SCP_EN 0xa460
+#define AFE_CUSTOM2_IRQ_MCU_DSP_WLA_EN 0xa464
+#define AFE_IRQ_MCU_DSP_WLA_EN 0xa468
+#define AFE_COMMON2_IRQ_MCU_STATUS 0xa46c
+#define AFE_COMMON2_IRQ_MCU_EN 0xa470
+#define AFE_COMMON2_IRQ_MCU_DSP_EN 0xa474
+#define AFE_COMMON2_IRQ_MCU_DSP2_EN 0xa478
+#define AFE_COMMON2_IRQ_MCU_DSP3_EN 0xa47c
+#define AFE_COMMON2_IRQ_MCU_DSP_WLA_EN 0xa480
+#define AFE_COMMON2_IRQ_MCU_SCP_EN 0xa484
+#define AFE_CUSTOM_IRQ_MCU_DSP_WLA_EN 0xa508
+
+#define AFE_MAX_REGISTER AFE_CUSTOM_IRQ_MCU_DSP_WLA_EN
+
+#define AFE_IRQ_STATUS_BITS 0x7FFFFFF
+#define AFE_IRQ_CNT_SHIFT 0
+#define AFE_IRQ_CNT_MASK 0xffffff
+
+#endif
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 02/10] ASoC: mediatek: mt8189: support audio clock control
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
2025-10-31 7:31 ` [PATCH v3 01/10] ASoC: mediatek: mt8189: add common header Cyril Chao
@ 2025-10-31 7:31 ` Cyril Chao
2025-10-31 7:31 ` [PATCH v3 03/10] ASoC: mediatek: mt8189: support ADDA in platform driver Cyril Chao
` (8 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:31 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add audio clock wrapper and audio tuner control.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
sound/soc/mediatek/mt8189/mt8189-afe-clk.c | 750 +++++++++++++++++++++
sound/soc/mediatek/mt8189/mt8189-afe-clk.h | 76 +++
2 files changed, 826 insertions(+)
create mode 100644 sound/soc/mediatek/mt8189/mt8189-afe-clk.c
create mode 100644 sound/soc/mediatek/mt8189/mt8189-afe-clk.h
diff --git a/sound/soc/mediatek/mt8189/mt8189-afe-clk.c b/sound/soc/mediatek/mt8189/mt8189-afe-clk.c
new file mode 100644
index 000000000000..fc7a7a73b0cf
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-afe-clk.c
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * mt8189-afe-clk.c -- Mediatek 8189 afe clock ctrl
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#include "mt8189-afe-common.h"
+#include "mt8189-afe-clk.h"
+
+/* mck */
+struct mt8189_mck_div {
+ int m_sel_id;
+ int div_clk_id;
+};
+
+static const struct mt8189_mck_div mck_div[MT8189_MCK_NUM] = {
+ [MT8189_I2SIN0_MCK] = {
+ .m_sel_id = MT8189_CLK_TOP_I2SIN0_M_SEL,
+ .div_clk_id = MT8189_CLK_TOP_APLL12_DIV_I2SIN0,
+ },
+ [MT8189_I2SIN1_MCK] = {
+ .m_sel_id = MT8189_CLK_TOP_I2SIN1_M_SEL,
+ .div_clk_id = MT8189_CLK_TOP_APLL12_DIV_I2SIN1,
+ },
+ [MT8189_I2SOUT0_MCK] = {
+ .m_sel_id = MT8189_CLK_TOP_I2SOUT0_M_SEL,
+ .div_clk_id = MT8189_CLK_TOP_APLL12_DIV_I2SOUT0,
+ },
+ [MT8189_I2SOUT1_MCK] = {
+ .m_sel_id = MT8189_CLK_TOP_I2SOUT1_M_SEL,
+ .div_clk_id = MT8189_CLK_TOP_APLL12_DIV_I2SOUT1,
+ },
+ [MT8189_FMI2S_MCK] = {
+ .m_sel_id = MT8189_CLK_TOP_FMI2S_M_SEL,
+ .div_clk_id = MT8189_CLK_TOP_APLL12_DIV_FMI2S,
+ },
+ [MT8189_TDMOUT_MCK] = {
+ .m_sel_id = MT8189_CLK_TOP_TDMOUT_M_SEL,
+ .div_clk_id = MT8189_CLK_TOP_APLL12_DIV_TDMOUT_M,
+ },
+ [MT8189_TDMOUT_BCK] = {
+ .m_sel_id = -1,
+ .div_clk_id = MT8189_CLK_TOP_APLL12_DIV_TDMOUT_B,
+ },
+};
+
+static const char *aud_clks[MT8189_CLK_NUM] = {
+ [MT8189_CLK_TOP_MUX_AUDIOINTBUS] = "top_aud_intbus",
+ [MT8189_CLK_TOP_MUX_AUD_ENG1] = "top_aud_eng1",
+ [MT8189_CLK_TOP_MUX_AUD_ENG2] = "top_aud_eng2",
+ [MT8189_CLK_TOP_MUX_AUDIO_H] = "top_aud_h",
+ /* pll */
+ [MT8189_CLK_TOP_APLL1_CK] = "apll1",
+ [MT8189_CLK_TOP_APLL2_CK] = "apll2",
+ /* divider */
+ [MT8189_CLK_TOP_APLL1_D4] = "apll1_d4",
+ [MT8189_CLK_TOP_APLL2_D4] = "apll2_d4",
+ [MT8189_CLK_TOP_APLL12_DIV_I2SIN0] = "apll12_div_i2sin0",
+ [MT8189_CLK_TOP_APLL12_DIV_I2SIN1] = "apll12_div_i2sin1",
+ [MT8189_CLK_TOP_APLL12_DIV_I2SOUT0] = "apll12_div_i2sout0",
+ [MT8189_CLK_TOP_APLL12_DIV_I2SOUT1] = "apll12_div_i2sout1",
+ [MT8189_CLK_TOP_APLL12_DIV_FMI2S] = "apll12_div_fmi2s",
+ [MT8189_CLK_TOP_APLL12_DIV_TDMOUT_M] = "apll12_div_tdmout_m",
+ [MT8189_CLK_TOP_APLL12_DIV_TDMOUT_B] = "apll12_div_tdmout_b",
+ /* mux */
+ [MT8189_CLK_TOP_MUX_AUD_1] = "top_apll1",
+ [MT8189_CLK_TOP_MUX_AUD_2] = "top_apll2",
+ [MT8189_CLK_TOP_I2SIN0_M_SEL] = "top_i2sin0",
+ [MT8189_CLK_TOP_I2SIN1_M_SEL] = "top_i2sin1",
+ [MT8189_CLK_TOP_I2SOUT0_M_SEL] = "top_i2sout0",
+ [MT8189_CLK_TOP_I2SOUT1_M_SEL] = "top_i2sout1",
+ [MT8189_CLK_TOP_FMI2S_M_SEL] = "top_fmi2s",
+ [MT8189_CLK_TOP_TDMOUT_M_SEL] = "top_dptx",
+ /* top 26m*/
+ [MT8189_CLK_TOP_CLK26M] = "clk26m",
+ /* peri */
+ [MT8189_CLK_PERAO_AUDIO_SLV_CK_PERI] = "aud_slv_ck_peri",
+ [MT8189_CLK_PERAO_AUDIO_MST_CK_PERI] = "aud_mst_ck_peri",
+ [MT8189_CLK_PERAO_INTBUS_CK_PERI] = "aud_intbus_ck_peri",
+};
+
+int mt8189_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
+{
+ int ret;
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ dev_err(afe->dev, "failed to enable clk\n");
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt8189_afe_enable_clk);
+
+void mt8189_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
+{
+ if (clk)
+ clk_disable_unprepare(clk);
+ else
+ dev_dbg(afe->dev, "NULL clk\n");
+}
+EXPORT_SYMBOL_GPL(mt8189_afe_disable_clk);
+
+static int mt8189_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
+ unsigned int rate)
+{
+ int ret;
+
+ if (clk) {
+ ret = clk_set_rate(clk, rate);
+ if (ret) {
+ dev_err(afe->dev, "failed to set clk rate\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int mt8189_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
+ struct clk *parent)
+{
+ int ret;
+
+ if (clk && parent) {
+ ret = clk_set_parent(clk, parent);
+ if (ret) {
+ dev_dbg(afe->dev, "failed to set clk parent %d\n", ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static unsigned int get_top_cg_reg(unsigned int cg_type)
+{
+ switch (cg_type) {
+ case MT8189_AUDIO_26M_EN_ON:
+ case MT8189_AUDIO_F3P25M_EN_ON:
+ case MT8189_AUDIO_APLL1_EN_ON:
+ case MT8189_AUDIO_APLL2_EN_ON:
+ return AUDIO_ENGEN_CON0;
+ case MT8189_CG_AUDIO_HOPPING_CK:
+ case MT8189_CG_AUDIO_F26M_CK:
+ case MT8189_CG_APLL1_CK:
+ case MT8189_CG_APLL2_CK:
+ case MT8189_PDN_APLL_TUNER2:
+ case MT8189_PDN_APLL_TUNER1:
+ return AUDIO_TOP_CON4;
+ default:
+ return 0;
+ }
+}
+
+static unsigned int get_top_cg_mask(unsigned int cg_type)
+{
+ switch (cg_type) {
+ case MT8189_AUDIO_26M_EN_ON:
+ return AUDIO_26M_EN_ON_MASK_SFT;
+ case MT8189_AUDIO_F3P25M_EN_ON:
+ return AUDIO_F3P25M_EN_ON_MASK_SFT;
+ case MT8189_AUDIO_APLL1_EN_ON:
+ return AUDIO_APLL1_EN_ON_MASK_SFT;
+ case MT8189_AUDIO_APLL2_EN_ON:
+ return AUDIO_APLL2_EN_ON_MASK_SFT;
+ case MT8189_CG_AUDIO_HOPPING_CK:
+ return CG_AUDIO_HOPPING_CK_MASK_SFT;
+ case MT8189_CG_AUDIO_F26M_CK:
+ return CG_AUDIO_F26M_CK_MASK_SFT;
+ case MT8189_CG_APLL1_CK:
+ return CG_APLL1_CK_MASK_SFT;
+ case MT8189_CG_APLL2_CK:
+ return CG_APLL2_CK_MASK_SFT;
+ case MT8189_PDN_APLL_TUNER2:
+ return PDN_APLL_TUNER2_MASK_SFT;
+ case MT8189_PDN_APLL_TUNER1:
+ return PDN_APLL_TUNER1_MASK_SFT;
+ default:
+ return 0;
+ }
+}
+
+static unsigned int get_top_cg_on_val(unsigned int cg_type)
+{
+ switch (cg_type) {
+ case MT8189_AUDIO_26M_EN_ON:
+ case MT8189_AUDIO_F3P25M_EN_ON:
+ case MT8189_AUDIO_APLL1_EN_ON:
+ case MT8189_AUDIO_APLL2_EN_ON:
+ return get_top_cg_mask(cg_type);
+ case MT8189_CG_AUDIO_HOPPING_CK:
+ case MT8189_CG_AUDIO_F26M_CK:
+ case MT8189_CG_APLL1_CK:
+ case MT8189_CG_APLL2_CK:
+ case MT8189_PDN_APLL_TUNER2:
+ case MT8189_PDN_APLL_TUNER1:
+ return 0;
+ default:
+ return 0;
+ }
+}
+
+static unsigned int get_top_cg_off_val(unsigned int cg_type)
+{
+ switch (cg_type) {
+ case MT8189_AUDIO_26M_EN_ON:
+ case MT8189_AUDIO_F3P25M_EN_ON:
+ case MT8189_AUDIO_APLL1_EN_ON:
+ case MT8189_AUDIO_APLL2_EN_ON:
+ return 0;
+ case MT8189_CG_AUDIO_HOPPING_CK:
+ case MT8189_CG_AUDIO_F26M_CK:
+ case MT8189_CG_APLL1_CK:
+ case MT8189_CG_APLL2_CK:
+ case MT8189_PDN_APLL_TUNER2:
+ case MT8189_PDN_APLL_TUNER1:
+ return get_top_cg_mask(cg_type);
+ default:
+ return get_top_cg_mask(cg_type);
+ }
+}
+
+static int mt8189_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
+{
+ unsigned int reg = get_top_cg_reg(cg_type);
+ unsigned int mask = get_top_cg_mask(cg_type);
+ unsigned int val = get_top_cg_on_val(cg_type);
+
+ if (!afe->regmap) {
+ dev_err(afe->dev, "afe regmap is null !!!\n");
+ return 0;
+ }
+
+ dev_dbg(afe->dev, "reg: 0x%x, mask: 0x%x, val: 0x%x\n", reg, mask, val);
+
+ return regmap_update_bits(afe->regmap, reg, mask, val);
+}
+
+static void mt8189_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
+{
+ unsigned int reg = get_top_cg_reg(cg_type);
+ unsigned int mask = get_top_cg_mask(cg_type);
+ unsigned int val = get_top_cg_off_val(cg_type);
+
+ if (!afe->regmap) {
+ dev_warn(afe->dev, "skip regmap\n");
+ return;
+ }
+
+ dev_dbg(afe->dev, "reg: 0x%x, mask: 0x%x, val: 0x%x\n", reg, mask, val);
+ regmap_update_bits(afe->regmap, reg, mask, val);
+}
+
+static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int ret;
+
+ dev_dbg(afe->dev, "enable: %d\n", enable);
+
+ if (enable) {
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1]);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1],
+ afe_priv->clk[MT8189_CLK_TOP_APLL1_CK]);
+ if (ret)
+ goto clk_ck_mux_aud1_parent_err;
+
+ /* 180.6336 / 4 = 45.1584MHz */
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG1]);
+ if (ret)
+ goto clk_ck_mux_eng1_err;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG1],
+ afe_priv->clk[MT8189_CLK_TOP_APLL1_D4]);
+ if (ret)
+ goto clk_ck_mux_eng1_parent_err;
+
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+ if (ret)
+ goto clk_ck_mux_audio_h_err;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H],
+ afe_priv->clk[MT8189_CLK_TOP_APLL1_CK]);
+ if (ret)
+ goto clk_ck_mux_audio_h_parent_err;
+ } else {
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG1],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG1]);
+
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1]);
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+ }
+
+ return 0;
+
+clk_ck_mux_audio_h_parent_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+clk_ck_mux_audio_h_err:
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG1],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+clk_ck_mux_eng1_parent_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG1]);
+clk_ck_mux_eng1_err:
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+clk_ck_mux_aud1_parent_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1]);
+
+ return ret;
+}
+
+static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int ret;
+
+ dev_dbg(afe->dev, "enable: %d\n", enable);
+
+ if (enable) {
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2]);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2],
+ afe_priv->clk[MT8189_CLK_TOP_APLL2_CK]);
+ if (ret)
+ goto clk_ck_mux_aud2_parent_err;
+
+ /* 196.608 / 4 = 49.152MHz */
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG2]);
+ if (ret)
+ goto clk_ck_mux_eng2_err;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG2],
+ afe_priv->clk[MT8189_CLK_TOP_APLL2_D4]);
+ if (ret)
+ goto clk_ck_mux_eng2_parent_err;
+
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+ if (ret)
+ goto clk_ck_mux_audio_h_err;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H],
+ afe_priv->clk[MT8189_CLK_TOP_APLL2_CK]);
+ if (ret)
+ goto clk_ck_mux_audio_h_parent_err;
+ } else {
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG2],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG2]);
+
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2]);
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+ }
+
+ return 0;
+
+clk_ck_mux_audio_h_parent_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+clk_ck_mux_audio_h_err:
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG2],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+clk_ck_mux_eng2_parent_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_ENG2]);
+clk_ck_mux_eng2_err:
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+clk_ck_mux_aud2_parent_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2]);
+
+ return ret;
+}
+
+static int mt8189_afe_disable_apll(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int ret;
+
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1]);
+ if (ret)
+ goto clk_ck_mux_aud1_err;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+ if (ret)
+ goto clk_ck_mux_aud1_parent_err;
+
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2]);
+ if (ret)
+ goto clk_ck_mux_aud2_err;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+ if (ret)
+ goto clk_ck_mux_aud2_parent_err;
+
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1]);
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2]);
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+
+ return 0;
+
+clk_ck_mux_aud2_parent_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_2]);
+clk_ck_mux_aud2_err:
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1],
+ afe_priv->clk[MT8189_CLK_TOP_APLL1_CK]);
+clk_ck_mux_aud1_parent_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUD_1]);
+clk_ck_mux_aud1_err:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+
+ return ret;
+}
+
+int mt8189_apll1_enable(struct mtk_base_afe *afe)
+{
+ int ret;
+
+ /* setting for APLL */
+ ret = apll1_mux_setting(afe, true);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_enable_top_cg(afe, MT8189_CG_APLL1_CK);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_enable_top_cg(afe, MT8189_PDN_APLL_TUNER1);
+ if (ret)
+ return ret;
+
+ /* sel 44.1kHz:1, apll_div:7, upper bound:3 */
+ regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
+ XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT |
+ UPPER_BOUND_MASK_SFT,
+ (0x1 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
+ (3 << UPPER_BOUND_SFT));
+
+ /* apll1 freq tuner enable */
+ regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
+ FREQ_TUNER_EN_MASK_SFT,
+ 0x1 << FREQ_TUNER_EN_SFT);
+
+ /* audio apll1 on */
+ ret = mt8189_afe_enable_top_cg(afe, MT8189_AUDIO_APLL1_EN_ON);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void mt8189_apll1_disable(struct mtk_base_afe *afe)
+{
+ /* audio apll1 off */
+ mt8189_afe_disable_top_cg(afe, MT8189_AUDIO_APLL1_EN_ON);
+
+ /* apll1 freq tuner disable */
+ regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
+ FREQ_TUNER_EN_MASK_SFT,
+ 0x0);
+
+ mt8189_afe_disable_top_cg(afe, MT8189_PDN_APLL_TUNER1);
+ mt8189_afe_disable_top_cg(afe, MT8189_CG_APLL1_CK);
+ apll1_mux_setting(afe, false);
+}
+
+int mt8189_apll2_enable(struct mtk_base_afe *afe)
+{
+ int ret;
+
+ /* setting for APLL */
+ ret = apll2_mux_setting(afe, true);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_enable_top_cg(afe, MT8189_CG_APLL2_CK);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_enable_top_cg(afe, MT8189_PDN_APLL_TUNER2);
+ if (ret)
+ return ret;
+
+ /* sel 48kHz: 2, apll_div: 7, upper bound: 3*/
+ regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
+ XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT |
+ UPPER_BOUND_MASK_SFT,
+ (0x2 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
+ (3 << UPPER_BOUND_SFT));
+
+ /* apll2 freq tuner enable */
+ regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
+ FREQ_TUNER_EN_MASK_SFT,
+ 0x1 << FREQ_TUNER_EN_SFT);
+
+ /* audio apll2 on */
+ ret = mt8189_afe_enable_top_cg(afe, MT8189_AUDIO_APLL2_EN_ON);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void mt8189_apll2_disable(struct mtk_base_afe *afe)
+{
+ /* audio apll2 off */
+ mt8189_afe_disable_top_cg(afe, MT8189_AUDIO_APLL2_EN_ON);
+
+ /* apll2 freq tuner disable */
+ regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
+ FREQ_TUNER_EN_MASK_SFT,
+ 0x0);
+
+ mt8189_afe_disable_top_cg(afe, MT8189_PDN_APLL_TUNER2);
+ mt8189_afe_disable_top_cg(afe, MT8189_CG_APLL2_CK);
+ apll2_mux_setting(afe, false);
+}
+
+int mt8189_get_apll_rate(struct mtk_base_afe *afe, int apll)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int clk_id;
+
+ if (apll < MT8189_APLL1 || apll > MT8189_APLL2) {
+ dev_warn(afe->dev, "invalid clk id %d\n", apll);
+ return 0;
+ }
+
+ if (apll == MT8189_APLL1)
+ clk_id = MT8189_CLK_TOP_APLL1_CK;
+ else
+ clk_id = MT8189_CLK_TOP_APLL2_CK;
+
+ return clk_get_rate(afe_priv->clk[clk_id]);
+}
+
+int mt8189_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
+{
+ return (rate % 8000) ? MT8189_APLL1 : MT8189_APLL2;
+}
+
+int mt8189_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
+{
+ if (strcmp(name, APLL1_W_NAME) == 0)
+ return MT8189_APLL1;
+
+ return MT8189_APLL2;
+}
+
+int mt8189_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int apll = mt8189_get_apll_by_rate(afe, rate);
+ int apll_clk_id = apll == MT8189_APLL1 ?
+ MT8189_CLK_TOP_MUX_AUD_1 : MT8189_CLK_TOP_MUX_AUD_2;
+ int m_sel_id;
+ int div_clk_id;
+ int ret;
+
+ dev_dbg(afe->dev, "mck_id: %d, rate: %d\n", mck_id, rate);
+
+ if (mck_id >= MT8189_MCK_NUM || mck_id < 0)
+ return -EINVAL;
+
+ m_sel_id = mck_div[mck_id].m_sel_id;
+ div_clk_id = mck_div[mck_id].div_clk_id;
+
+ /* select apll */
+ if (m_sel_id >= 0) {
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[m_sel_id]);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_set_clk_parent(afe, afe_priv->clk[m_sel_id],
+ afe_priv->clk[apll_clk_id]);
+ if (ret)
+ return ret;
+ }
+
+ /* enable div, set rate */
+ if (div_clk_id < 0) {
+ dev_err(afe->dev, "invalid div_clk_id %d\n", div_clk_id);
+ return -EINVAL;
+ }
+
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[div_clk_id]);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_set_clk_rate(afe, afe_priv->clk[div_clk_id], rate);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int mt8189_mck_disable(struct mtk_base_afe *afe, int mck_id)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int m_sel_id;
+ int div_clk_id;
+
+ dev_dbg(afe->dev, "mck_id: %d.\n", mck_id);
+
+ if (mck_id < 0) {
+ dev_err(afe->dev, "mck_id = %d < 0\n", mck_id);
+ return -EINVAL;
+ }
+
+ m_sel_id = mck_div[mck_id].m_sel_id;
+ div_clk_id = mck_div[mck_id].div_clk_id;
+
+ if (div_clk_id < 0) {
+ dev_err(afe->dev, "div_clk_id = %d < 0\n",
+ div_clk_id);
+ return -EINVAL;
+ }
+
+ mt8189_afe_disable_clk(afe, afe_priv->clk[div_clk_id]);
+
+ if (m_sel_id >= 0)
+ mt8189_afe_disable_clk(afe, afe_priv->clk[m_sel_id]);
+
+ return 0;
+}
+
+int mt8189_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+
+ /* bus clock for AFE internal access, like AFE SRAM */
+ mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIOINTBUS]);
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIOINTBUS],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+ /* enable audio clock source */
+ mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+ mt8189_afe_set_clk_parent(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H],
+ afe_priv->clk[MT8189_CLK_TOP_CLK26M]);
+
+ return 0;
+}
+
+int mt8189_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIO_H]);
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_TOP_MUX_AUDIOINTBUS]);
+
+ return 0;
+}
+
+int mt8189_afe_enable_main_clock(struct mtk_base_afe *afe)
+{
+ return mt8189_afe_enable_top_cg(afe, MT8189_AUDIO_26M_EN_ON);
+}
+
+void mt8189_afe_disable_main_clock(struct mtk_base_afe *afe)
+{
+ mt8189_afe_disable_top_cg(afe, MT8189_AUDIO_26M_EN_ON);
+}
+
+static int mt8189_afe_enable_ao_clock(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int ret;
+
+ /* Peri clock AO enable */
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_PERAO_INTBUS_CK_PERI]);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_PERAO_AUDIO_SLV_CK_PERI]);
+ if (ret)
+ goto err_clk_perao_slv;
+
+ ret = mt8189_afe_enable_clk(afe, afe_priv->clk[MT8189_CLK_PERAO_AUDIO_MST_CK_PERI]);
+ if (ret)
+ goto err_clk_perao_mst;
+
+ return 0;
+
+err_clk_perao_mst:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_PERAO_AUDIO_SLV_CK_PERI]);
+err_clk_perao_slv:
+ mt8189_afe_disable_clk(afe, afe_priv->clk[MT8189_CLK_PERAO_INTBUS_CK_PERI]);
+
+ return ret;
+}
+
+int mt8189_init_clock(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int ret;
+ int i;
+
+ afe_priv->clk = devm_kcalloc(afe->dev, MT8189_CLK_NUM, sizeof(*afe_priv->clk),
+ GFP_KERNEL);
+ if (!afe_priv->clk)
+ return -ENOMEM;
+
+ for (i = 0; i < MT8189_CLK_NUM; i++) {
+ afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
+ if (IS_ERR(afe_priv->clk[i])) {
+ dev_err(afe->dev, "devm_clk_get %s fail\n", aud_clks[i]);
+ return PTR_ERR(afe_priv->clk[i]);
+ }
+ }
+
+ ret = mt8189_afe_disable_apll(afe);
+ if (ret)
+ return ret;
+
+ ret = mt8189_afe_enable_ao_clock(afe);
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/sound/soc/mediatek/mt8189/mt8189-afe-clk.h b/sound/soc/mediatek/mt8189/mt8189-afe-clk.h
new file mode 100644
index 000000000000..9ce5d1043feb
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-afe-clk.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt8189-afe-clk.h -- Mediatek 8189 afe clock ctrl definition
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#ifndef _MT8189_AFE_CLOCK_CTRL_H_
+#define _MT8189_AFE_CLOCK_CTRL_H_
+
+/* APLL */
+#define APLL1_W_NAME "APLL1"
+#define APLL2_W_NAME "APLL2"
+
+enum {
+ MT8189_APLL1,
+ MT8189_APLL2,
+};
+
+enum {
+ MT8189_CLK_TOP_MUX_AUDIOINTBUS,
+ MT8189_CLK_TOP_MUX_AUD_ENG1,
+ MT8189_CLK_TOP_MUX_AUD_ENG2,
+ MT8189_CLK_TOP_MUX_AUDIO_H,
+ /* pll */
+ MT8189_CLK_TOP_APLL1_CK,
+ MT8189_CLK_TOP_APLL2_CK,
+ /* divider */
+ MT8189_CLK_TOP_APLL1_D4,
+ MT8189_CLK_TOP_APLL2_D4,
+ MT8189_CLK_TOP_APLL12_DIV_I2SIN0,
+ MT8189_CLK_TOP_APLL12_DIV_I2SIN1,
+ MT8189_CLK_TOP_APLL12_DIV_I2SOUT0,
+ MT8189_CLK_TOP_APLL12_DIV_I2SOUT1,
+ MT8189_CLK_TOP_APLL12_DIV_FMI2S,
+ MT8189_CLK_TOP_APLL12_DIV_TDMOUT_M,
+ MT8189_CLK_TOP_APLL12_DIV_TDMOUT_B,
+ /* mux */
+ MT8189_CLK_TOP_MUX_AUD_1,
+ MT8189_CLK_TOP_MUX_AUD_2,
+ MT8189_CLK_TOP_I2SIN0_M_SEL,
+ MT8189_CLK_TOP_I2SIN1_M_SEL,
+ MT8189_CLK_TOP_I2SOUT0_M_SEL,
+ MT8189_CLK_TOP_I2SOUT1_M_SEL,
+ MT8189_CLK_TOP_FMI2S_M_SEL,
+ MT8189_CLK_TOP_TDMOUT_M_SEL,
+ /* top 26m */
+ MT8189_CLK_TOP_CLK26M,
+ /* peri */
+ MT8189_CLK_PERAO_AUDIO_SLV_CK_PERI,
+ MT8189_CLK_PERAO_AUDIO_MST_CK_PERI,
+ MT8189_CLK_PERAO_INTBUS_CK_PERI,
+ MT8189_CLK_NUM,
+};
+
+struct mtk_base_afe;
+
+int mt8189_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
+int mt8189_mck_disable(struct mtk_base_afe *afe, int mck_id);
+int mt8189_get_apll_rate(struct mtk_base_afe *afe, int apll);
+int mt8189_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
+int mt8189_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
+int mt8189_init_clock(struct mtk_base_afe *afe);
+int mt8189_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
+void mt8189_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
+int mt8189_apll1_enable(struct mtk_base_afe *afe);
+void mt8189_apll1_disable(struct mtk_base_afe *afe);
+int mt8189_apll2_enable(struct mtk_base_afe *afe);
+void mt8189_apll2_disable(struct mtk_base_afe *afe);
+int mt8189_afe_enable_main_clock(struct mtk_base_afe *afe);
+void mt8189_afe_disable_main_clock(struct mtk_base_afe *afe);
+int mt8189_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
+int mt8189_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
+
+#endif
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 03/10] ASoC: mediatek: mt8189: support ADDA in platform driver
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
2025-10-31 7:31 ` [PATCH v3 01/10] ASoC: mediatek: mt8189: add common header Cyril Chao
2025-10-31 7:31 ` [PATCH v3 02/10] ASoC: mediatek: mt8189: support audio clock control Cyril Chao
@ 2025-10-31 7:31 ` Cyril Chao
2025-10-31 7:31 ` [PATCH v3 04/10] ASoC: mediatek: mt8189: support I2S " Cyril Chao
` (7 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:31 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add mt8189 ADDA DAI driver support.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
sound/soc/mediatek/mt8189/mt8189-dai-adda.c | 1228 +++++++++++++++++++
1 file changed, 1228 insertions(+)
create mode 100644 sound/soc/mediatek/mt8189/mt8189-dai-adda.c
diff --git a/sound/soc/mediatek/mt8189/mt8189-dai-adda.c b/sound/soc/mediatek/mt8189/mt8189-dai-adda.c
new file mode 100644
index 000000000000..ad5b9546ff63
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-dai-adda.c
@@ -0,0 +1,1228 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek ALSA SoC Audio DAI ADDA Control
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#include <linux/regmap.h>
+#include <linux/delay.h>
+
+#include "mt8189-afe-clk.h"
+#include "mt8189-afe-common.h"
+#include "mt8189-interconnection.h"
+
+/* mt6363 vs1 voter */
+#define VS1_MT6338_MASK_SFT 0x1
+#define RG_BUCK_VS1_VOTER_EN_LO 0x189a
+#define RG_BUCK_VS1_VOTER_EN_LO_SET 0x189b
+#define RG_BUCK_VS1_VOTER_EN_LO_CLR 0x189c
+
+#define AUDIO_SDM_LEVEL_NORMAL 0x1d
+#define MTK_AFE_ADDA_DL_GAIN_NORMAL 0xf74f
+#define SDM_AUTO_RESET_THRESHOLD 0x190000
+
+enum {
+ SUPPLY_SEQ_ADDA_AFE_ON,
+ SUPPLY_SEQ_ADDA_DL_ON,
+ SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
+ SUPPLY_SEQ_ADDA_MTKAIF_CFG,
+ SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
+ SUPPLY_SEQ_ADDA_FIFO,
+ SUPPLY_SEQ_ADDA_AP_DMIC,
+ SUPPLY_SEQ_ADDA_UL_ON,
+};
+
+enum {
+ UL_IIR_SW,
+ UL_IIR_5HZ,
+ UL_IIR_10HZ,
+ UL_IIR_25HZ,
+ UL_IIR_50HZ,
+ UL_IIR_75HZ,
+};
+
+enum {
+ AUDIO_SDM_2ND,
+ AUDIO_SDM_3RD,
+};
+
+enum {
+ DELAY_DATA_MISO1,
+ DELAY_DATA_MISO2,
+};
+
+enum {
+ MTK_AFE_ADDA_DL_RATE_8K,
+ MTK_AFE_ADDA_DL_RATE_11K,
+ MTK_AFE_ADDA_DL_RATE_12K,
+ MTK_AFE_ADDA_DL_RATE_16K = 4,
+ MTK_AFE_ADDA_DL_RATE_22K,
+ MTK_AFE_ADDA_DL_RATE_24K,
+ MTK_AFE_ADDA_DL_RATE_32K = 8,
+ MTK_AFE_ADDA_DL_RATE_44K,
+ MTK_AFE_ADDA_DL_RATE_48K,
+ MTK_AFE_ADDA_DL_RATE_88K = 13,
+ MTK_AFE_ADDA_DL_RATE_96K,
+ MTK_AFE_ADDA_DL_RATE_176K = 17,
+ MTK_AFE_ADDA_DL_RATE_192K,
+ MTK_AFE_ADDA_DL_RATE_352K = 21,
+ MTK_AFE_ADDA_DL_RATE_384K,
+};
+
+enum {
+ MTK_AFE_ADDA_UL_RATE_8K,
+ MTK_AFE_ADDA_UL_RATE_16K,
+ MTK_AFE_ADDA_UL_RATE_32K,
+ MTK_AFE_ADDA_UL_RATE_48K,
+ MTK_AFE_ADDA_UL_RATE_96K,
+ MTK_AFE_ADDA_UL_RATE_192K,
+ MTK_AFE_ADDA_UL_RATE_48K_HD,
+};
+
+struct mtk_afe_adda_priv {
+ int dl_rate;
+ int ul_rate;
+};
+
+static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
+ unsigned int rate)
+{
+ switch (rate) {
+ case 8000:
+ return MTK_AFE_ADDA_DL_RATE_8K;
+ case 11025:
+ return MTK_AFE_ADDA_DL_RATE_11K;
+ case 12000:
+ return MTK_AFE_ADDA_DL_RATE_12K;
+ case 16000:
+ return MTK_AFE_ADDA_DL_RATE_16K;
+ case 22050:
+ return MTK_AFE_ADDA_DL_RATE_22K;
+ case 24000:
+ return MTK_AFE_ADDA_DL_RATE_24K;
+ case 32000:
+ return MTK_AFE_ADDA_DL_RATE_32K;
+ case 44100:
+ return MTK_AFE_ADDA_DL_RATE_44K;
+ case 48000:
+ return MTK_AFE_ADDA_DL_RATE_48K;
+ case 96000:
+ return MTK_AFE_ADDA_DL_RATE_96K;
+ case 192000:
+ return MTK_AFE_ADDA_DL_RATE_192K;
+ default:
+ dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
+ __func__, rate);
+ return MTK_AFE_ADDA_DL_RATE_48K;
+ }
+}
+
+static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
+ unsigned int rate)
+{
+ switch (rate) {
+ case 8000:
+ return MTK_AFE_ADDA_UL_RATE_8K;
+ case 16000:
+ return MTK_AFE_ADDA_UL_RATE_16K;
+ case 32000:
+ return MTK_AFE_ADDA_UL_RATE_32K;
+ case 48000:
+ return MTK_AFE_ADDA_UL_RATE_48K;
+ case 96000:
+ return MTK_AFE_ADDA_UL_RATE_96K;
+ case 192000:
+ return MTK_AFE_ADDA_UL_RATE_192K;
+ default:
+ dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
+ __func__, rate);
+ return MTK_AFE_ADDA_UL_RATE_48K;
+ }
+}
+
+/* dai component */
+static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN014_1, I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN014_1, I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN014_1, I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN014_1, I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN014_1, I_DL4_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN014_1, I_DL5_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN014_1, I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN014_1, I_DL7_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN014_1, I_DL8_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN014_1, I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN014_2, I_DL24_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN014_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN014_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN014_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN014_0,
+ I_GAIN0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN014_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN014_6,
+ I_SRC_0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN014_6,
+ I_SRC_1_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN014_6,
+ I_SRC_2_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN015_1, I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN015_1, I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN015_1, I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN015_1, I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN015_1, I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN015_1, I_DL4_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN015_1, I_DL5_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN015_1, I_DL6_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN015_1, I_DL7_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN015_1, I_DL8_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN015_1, I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN015_2, I_DL24_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN015_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN015_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN015_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN015_0,
+ I_GAIN0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN015_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN015_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN015_6,
+ I_SRC_0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN015_6,
+ I_SRC_1_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN015_6,
+ I_SRC_2_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN016_1, I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN016_1, I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN016_1, I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN016_1, I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN016_1, I_DL4_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN016_1, I_DL5_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN016_1, I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN016_1, I_DL7_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN016_1, I_DL8_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN016_1, I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH3", AFE_CONN016_1, I_DL_24CH_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN016_2, I_DL24_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN016_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN016_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN016_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN016_0,
+ I_GAIN0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN016_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN016_6,
+ I_SRC_0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN016_6,
+ I_SRC_1_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN016_6,
+ I_SRC_2_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN017_1, I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN017_1, I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN017_1, I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN017_1, I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN017_1, I_DL4_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN017_1, I_DL5_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN017_1, I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN017_1, I_DL7_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN017_1, I_DL8_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN017_1, I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH4", AFE_CONN017_1, I_DL_24CH_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN017_2, I_DL24_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN017_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN017_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN017_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN017_0,
+ I_GAIN0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN017_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN017_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN017_6,
+ I_SRC_0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN017_6,
+ I_SRC_1_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN017_6,
+ I_SRC_2_OUT_CH2, 1, 0),
+};
+
+static int mtk_adda_ul_src_enable_dmic(struct mtk_base_afe *afe, int id)
+{
+ unsigned int reg, reg1;
+
+ switch (id) {
+ case MT8189_DAI_ADDA:
+ reg = AFE_ADDA_UL0_SRC_CON0;
+ reg1 = AFE_ADDA_UL0_SRC_CON1;
+ break;
+ case MT8189_DAI_AP_DMIC:
+ reg = AFE_ADDA_DMIC0_SRC_CON0;
+ reg1 = AFE_ADDA_DMIC0_SRC_CON1;
+ break;
+ case MT8189_DAI_AP_DMIC_CH34:
+ reg = AFE_ADDA_DMIC1_SRC_CON0;
+ reg1 = AFE_ADDA_DMIC1_SRC_CON1;
+ break;
+ default:
+ return -EINVAL;
+ }
+ /* choose Phase */
+ regmap_update_bits(afe->regmap, reg,
+ UL_DMIC_PHASE_SEL_CH1_MASK_SFT,
+ 0x0 << UL_DMIC_PHASE_SEL_CH1_SFT);
+ regmap_update_bits(afe->regmap, reg,
+ UL_DMIC_PHASE_SEL_CH2_MASK_SFT,
+ 0x4 << UL_DMIC_PHASE_SEL_CH2_SFT);
+
+ /* dmic mode, 3.25M*/
+ regmap_update_bits(afe->regmap, reg,
+ DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT,
+ 0x0);
+ regmap_update_bits(afe->regmap, reg,
+ DMIC_LOW_POWER_MODE_CTL_MASK_SFT,
+ 0x0);
+
+ /* turn on dmic, ch1, ch2 */
+ regmap_update_bits(afe->regmap, reg,
+ UL_SDM_3_LEVEL_CTL_MASK_SFT,
+ 0x1 << UL_SDM_3_LEVEL_CTL_SFT);
+ regmap_update_bits(afe->regmap, reg,
+ UL_MODE_3P25M_CH1_CTL_MASK_SFT,
+ 0x1 << UL_MODE_3P25M_CH1_CTL_SFT);
+ regmap_update_bits(afe->regmap, reg,
+ UL_MODE_3P25M_CH2_CTL_MASK_SFT,
+ 0x1 << UL_MODE_3P25M_CH2_CTL_SFT);
+
+ /* ul gain: gain = 0x7fff/positive_gain = 0x0/gain_mode = 0x10 */
+ regmap_update_bits(afe->regmap, reg1,
+ ADDA_UL_GAIN_VALUE_MASK_SFT,
+ 0x7fff << ADDA_UL_GAIN_VALUE_SFT);
+ regmap_update_bits(afe->regmap, reg1,
+ ADDA_UL_POSTIVEGAIN_MASK_SFT,
+ 0x0 << ADDA_UL_POSTIVEGAIN_SFT);
+ /* gain_mode = 0x02: Add 0.5 gain at CIC output */
+ regmap_update_bits(afe->regmap, reg1,
+ GAIN_MODE_MASK_SFT,
+ 0x02 << GAIN_MODE_SFT);
+
+ return 0;
+}
+
+static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int mtkaif_dmic = afe_priv->mtkaif_dmic;
+
+ dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",
+ __func__, w->name, event, mtkaif_dmic);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* update setting to dmic */
+ if (mtkaif_dmic) {
+ /* mtkaif_rxif_data_mode = 1, dmic */
+ regmap_update_bits(afe->regmap, AFE_MTKAIF0_RX_CFG0,
+ RG_MTKAIF0_RXIF_DATA_MODE_MASK_SFT,
+ 0x1);
+
+ /* dmic mode, 3.25M*/
+ regmap_update_bits(afe->regmap, AFE_MTKAIF0_RX_CFG0,
+ RG_MTKAIF0_RXIF_VOICE_MODE_MASK_SFT,
+ 0x0);
+ mtk_adda_ul_src_enable_dmic(afe, MT8189_DAI_ADDA);
+ }
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
+ usleep_range(120, 130);
+
+ /* reset dmic */
+ afe_priv->mtkaif_dmic = 0;
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+
+ if (event == SND_SOC_DAPM_PRE_PMU) {
+ if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
+ regmap_write(afe->regmap, AFE_AUD_PAD_TOP_CFG0, 0xB8);
+ else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2)
+ regmap_write(afe->regmap, AFE_AUD_PAD_TOP_CFG0, 0xB0);
+ else
+ regmap_write(afe->regmap, AFE_AUD_PAD_TOP_CFG0, 0xB0);
+ }
+
+ return 0;
+}
+
+static bool is_adda_mtkaif_need_phase_delay(struct mt8189_afe_private *afe_priv)
+{
+ return afe_priv->mtkaif_chosen_phase[0] >= 0 &&
+ afe_priv->mtkaif_chosen_phase[1] >= 0;
+}
+
+static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int delay_data;
+ int delay_cycle;
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
+ /* set protocol 2 */
+ regmap_write(afe->regmap, AFE_MTKAIF0_CFG0,
+ 0x00010000);
+ regmap_write(afe->regmap, AFE_MTKAIF1_CFG0,
+ 0x00010000);
+
+ /* mtkaif_rxif_clkinv_adc inverse for calibration */
+ regmap_update_bits(afe->regmap, AFE_MTKAIF0_CFG0,
+ RG_MTKAIF0_RXIF_CLKINV_MASK_SFT,
+ 0x1 << RG_MTKAIF0_RXIF_CLKINV_SFT);
+ regmap_update_bits(afe->regmap, AFE_MTKAIF1_CFG0,
+ RG_MTKAIF1_RXIF_CLKINV_ADC_MASK_SFT,
+ 0x1 << RG_MTKAIF1_RXIF_CLKINV_ADC_SFT);
+
+ /* This event align the phase of every miso pin */
+ /* If only 1 miso is used, there is no need to do phase delay. */
+ if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0 &&
+ !is_adda_mtkaif_need_phase_delay(afe_priv)) {
+ dev_dbg(afe->dev,
+ "%s(), check adda mtkaif_chosen_phase[0/1]:%d/%d\n",
+ __func__,
+ afe_priv->mtkaif_chosen_phase[0],
+ afe_priv->mtkaif_chosen_phase[1]);
+ break;
+ } else if (strcmp(w->name, "ADDA6_MTKAIF_CFG") == 0 &&
+ afe_priv->mtkaif_chosen_phase[2] < 0) {
+ dev_dbg(afe->dev,
+ "%s(), check adda6 mtkaif_chosen_phase[2]:%d\n",
+ __func__,
+ afe_priv->mtkaif_chosen_phase[2]);
+ break;
+ }
+
+ /* set delay for ch12 to align phase of miso0 and miso1 */
+ if (afe_priv->mtkaif_phase_cycle[0] >=
+ afe_priv->mtkaif_phase_cycle[1]) {
+ delay_data = DELAY_DATA_MISO1;
+ delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
+ afe_priv->mtkaif_phase_cycle[1];
+ } else {
+ delay_data = DELAY_DATA_MISO2;
+ delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
+ afe_priv->mtkaif_phase_cycle[0];
+ }
+
+ regmap_update_bits(afe->regmap,
+ AFE_MTKAIF0_RX_CFG2,
+ RG_MTKAIF0_RXIF_DELAY_DATA_MASK_SFT,
+ delay_data <<
+ RG_MTKAIF0_RXIF_DELAY_DATA_SFT);
+
+ regmap_update_bits(afe->regmap,
+ AFE_MTKAIF0_RX_CFG2,
+ RG_MTKAIF0_RXIF_DELAY_CYCLE_MASK_SFT,
+ delay_cycle <<
+ RG_MTKAIF0_RXIF_DELAY_CYCLE_SFT);
+
+ /* set delay between ch3 and ch2 */
+ if (afe_priv->mtkaif_phase_cycle[2] >=
+ afe_priv->mtkaif_phase_cycle[1]) {
+ delay_data = DELAY_DATA_MISO1; /* ch3 */
+ delay_cycle = afe_priv->mtkaif_phase_cycle[2] -
+ afe_priv->mtkaif_phase_cycle[1];
+ } else {
+ delay_data = DELAY_DATA_MISO2; /* ch2 */
+ delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
+ afe_priv->mtkaif_phase_cycle[2];
+ }
+
+ regmap_update_bits(afe->regmap,
+ AFE_MTKAIF1_RX_CFG2,
+ RG_MTKAIF1_RXIF_DELAY_DATA_MASK_SFT,
+ delay_data <<
+ RG_MTKAIF1_RXIF_DELAY_DATA_SFT);
+ regmap_update_bits(afe->regmap,
+ AFE_MTKAIF1_RX_CFG2,
+ RG_MTKAIF1_RXIF_DELAY_CYCLE_MASK_SFT,
+ delay_cycle <<
+ RG_MTKAIF1_RXIF_DELAY_CYCLE_SFT);
+ } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
+ regmap_write(afe->regmap, AFE_MTKAIF0_CFG0,
+ 0x00010000);
+ regmap_write(afe->regmap, AFE_MTKAIF1_CFG0,
+ 0x00010000);
+ } else {
+ regmap_write(afe->regmap, AFE_MTKAIF0_CFG0, 0x0);
+ regmap_write(afe->regmap, AFE_MTKAIF1_CFG0, 0x0);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+
+ dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
+ __func__, w->name, event);
+
+ /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
+ if (event == SND_SOC_DAPM_POST_PMD)
+ usleep_range(120, 130);
+
+ return 0;
+}
+
+static void mt6363_vs1_vote(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ bool pre_enable = afe_priv->is_mt6363_vote;
+ bool enable;
+
+ if (!afe_priv->pmic_regmap)
+ return;
+
+ enable = (afe_priv->is_adda_dl_on && afe_priv->is_adda_dl_max_vol) ||
+ (afe_priv->is_adda_ul_on);
+ if (enable == pre_enable) {
+ dev_dbg(afe->dev, "%s() enable == pre_enable = %d\n",
+ __func__, enable);
+ return;
+ }
+
+ afe_priv->is_mt6363_vote = enable;
+ dev_dbg(afe->dev, "%s() enable = %d\n", __func__, enable);
+
+ if (enable)
+ regmap_update_bits(afe_priv->pmic_regmap, RG_BUCK_VS1_VOTER_EN_LO_SET,
+ VS1_MT6338_MASK_SFT, 0x1);
+ else
+ regmap_update_bits(afe_priv->pmic_regmap, RG_BUCK_VS1_VOTER_EN_LO_CLR,
+ VS1_MT6338_MASK_SFT, 0x1);
+}
+
+static int mt_vs1_voter_dl_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+
+ dev_dbg(afe->dev, "%s(), event = 0x%x\n", __func__, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ afe_priv->is_adda_dl_on = true;
+ mt6363_vs1_vote(afe);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ afe_priv->is_adda_dl_on = false;
+ mt6363_vs1_vote(afe);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int mt_vs1_voter_ul_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+
+ dev_dbg(afe->dev, "%s(), event = 0x%x\n", __func__, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ afe_priv->is_adda_ul_on = true;
+ mt6363_vs1_vote(afe);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ afe_priv->is_adda_ul_on = false;
+ mt6363_vs1_vote(afe);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int mt8189_adda_dmic_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+
+ ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
+
+ return 0;
+}
+
+static int mt8189_adda_dmic_set(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int dmic_on;
+
+ dmic_on = !!ucontrol->value.integer.value[0];
+
+ dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
+ __func__, kcontrol->id.name, dmic_on);
+
+ afe_priv->mtkaif_dmic = dmic_on;
+ afe_priv->mtkaif_dmic_ch34 = dmic_on;
+
+ return 0;
+}
+
+static int mt8189_adda_dl_max_vol_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+
+ ucontrol->value.integer.value[0] = afe_priv->is_adda_dl_max_vol;
+
+ return 0;
+}
+
+static int mt8189_adda_dl_max_vol_set(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ bool is_adda_dl_max_vol = ucontrol->value.integer.value[0];
+
+ afe_priv->is_adda_dl_max_vol = is_adda_dl_max_vol;
+ mt6363_vs1_vote(afe);
+
+ return 0;
+}
+
+static const struct snd_kcontrol_new mtk_adda_controls[] = {
+ SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC_CON1,
+ AFE_DL_GAIN1_CTL_PRE_SFT, AFE_DL_GAIN1_CTL_PRE_MASK, 0),
+ SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
+ mt8189_adda_dmic_get, mt8189_adda_dmic_set),
+ SOC_SINGLE_BOOL_EXT("ADDA_DL_MAX_VOL Switch", 0,
+ mt8189_adda_dl_max_vol_get,
+ mt8189_adda_dl_max_vol_set),
+};
+
+static const char *const adda_ul_mux_texts[] = {
+ "MTKAIF", "AP_DMIC", "AP_DMIC_MULTI_CH",
+};
+
+static SOC_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
+ SND_SOC_NOPM,
+ 0,
+ adda_ul_mux_texts);
+
+static const struct snd_kcontrol_new adda_ul_mux_control =
+ SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
+
+static const struct snd_kcontrol_new adda_ch34_ul_mux_control =
+ SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum);
+
+static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
+ /* inter-connections */
+ SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
+ mtk_adda_dl_ch1_mix,
+ ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
+ SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
+ mtk_adda_dl_ch2_mix,
+ ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0,
+ mtk_adda_dl_ch3_mix,
+ ARRAY_SIZE(mtk_adda_dl_ch3_mix)),
+ SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0,
+ mtk_adda_dl_ch4_mix,
+ ARRAY_SIZE(mtk_adda_dl_ch4_mix)),
+
+ SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
+ AUDIO_ENGEN_CON0, AUDIO_F3P25M_EN_ON_SFT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("ADDA_DL0_CG", SUPPLY_SEQ_ADDA_DL_ON,
+ AUDIO_TOP_CON0,
+ PDN_DL0_DAC_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("ADDA_UL0_CG", SUPPLY_SEQ_ADDA_UL_ON,
+ AUDIO_TOP_CON1,
+ PDN_UL0_ADC_SFT, 1,
+ NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
+ AFE_ADDA_DL_SRC_CON0,
+ AFE_DL_SRC_ON_TMP_CTL_PRE_SFT, 0,
+ mtk_adda_dl_event,
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
+ AFE_ADDA_UL0_SRC_CON0,
+ UL_SRC_ON_TMP_CTL_SFT, 0,
+ mtk_adda_ul_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY_S("AP DMIC Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
+ AFE_ADDA_DMIC0_SRC_CON0,
+ UL_SRC_ON_TMP_CTL_SFT, 0,
+ NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY_S("AP DMIC CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
+ AFE_ADDA_DMIC1_SRC_CON0,
+ UL_SRC_ON_TMP_CTL_SFT, 0,
+ NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
+ AFE_AUD_PAD_TOP_CFG0,
+ RG_RX_FIFO_ON_SFT, 0,
+ mtk_adda_pad_top_event,
+ SND_SOC_DAPM_PRE_PMU),
+ SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
+ SND_SOC_NOPM, 0, 0,
+ mtk_adda_mtkaif_cfg_event,
+ SND_SOC_DAPM_PRE_PMU),
+ SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
+ SND_SOC_NOPM, 0, 0,
+ mtk_adda_mtkaif_cfg_event,
+ SND_SOC_DAPM_PRE_PMU),
+ SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
+ AFE_ADDA_DMIC0_SRC_CON0,
+ UL_AP_DMIC_ON_SFT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("AP_DMIC0_CG", SUPPLY_SEQ_ADDA_AP_DMIC,
+ AUDIO_TOP_CON1,
+ PDN_DMIC0_ADC_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
+ AFE_ADDA_DMIC1_SRC_CON0,
+ UL_AP_DMIC_ON_SFT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("AP_DMIC1_CG", SUPPLY_SEQ_ADDA_AP_DMIC,
+ AUDIO_TOP_CON1,
+ PDN_DMIC1_ADC_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
+ AFE_ADDA_UL0_SRC_CON1,
+ FIFO_SOFT_RST_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("AP_DMIC_FIFO", SUPPLY_SEQ_ADDA_FIFO,
+ AFE_ADDA_DMIC0_SRC_CON1,
+ FIFO_SOFT_RST_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO,
+ AFE_ADDA_DMIC1_SRC_CON1,
+ FIFO_SOFT_RST_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("VS1_VOTER_DL", SUPPLY_SEQ_ADDA_AFE_ON,
+ SND_SOC_NOPM, 0, 0,
+ mt_vs1_voter_dl_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY_S("VS1_VOTER_UL", SUPPLY_SEQ_ADDA_AFE_ON,
+ SND_SOC_NOPM, 0, 0,
+ mt_vs1_voter_ul_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
+ &adda_ul_mux_control),
+ SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0,
+ &adda_ch34_ul_mux_control),
+
+ SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
+};
+
+static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
+ /* playback */
+ {"ADDA_DL_CH1", "DL0_CH1", "DL0"},
+ {"ADDA_DL_CH2", "DL0_CH1", "DL0"},
+ {"ADDA_DL_CH2", "DL0_CH2", "DL0"},
+
+ {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
+ {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
+
+ {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
+ {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
+
+ {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
+ {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
+
+ {"ADDA_DL_CH1", "DL4_CH1", "DL4"},
+ {"ADDA_DL_CH2", "DL4_CH2", "DL4"},
+
+ {"ADDA_DL_CH1", "DL5_CH1", "DL5"},
+ {"ADDA_DL_CH2", "DL5_CH2", "DL5"},
+
+ {"ADDA_DL_CH1", "DL6_CH1", "DL6"},
+ {"ADDA_DL_CH2", "DL6_CH2", "DL6"},
+
+ {"ADDA_DL_CH1", "DL7_CH1", "DL7"},
+ {"ADDA_DL_CH2", "DL7_CH2", "DL7"},
+
+ {"ADDA_DL_CH1", "DL8_CH1", "DL8"},
+ {"ADDA_DL_CH2", "DL8_CH2", "DL8"},
+
+ {"ADDA_DL_CH1", "DL_24CH_CH1", "DL_24CH"},
+ {"ADDA_DL_CH2", "DL_24CH_CH2", "DL_24CH"},
+
+ {"ADDA_DL_CH1", "DL24_CH1", "DL24"},
+ {"ADDA_DL_CH2", "DL24_CH2", "DL24"},
+
+ {"ADDA Playback", NULL, "ADDA_DL_CH1"},
+ {"ADDA Playback", NULL, "ADDA_DL_CH2"},
+
+ {"ADDA Playback", NULL, "ADDA Enable"},
+ {"ADDA Playback", NULL, "ADDA Playback Enable"},
+ {"ADDA Playback", NULL, "AUD_PAD_TOP"},
+ {"ADDA Playback", NULL, "VS1_VOTER_DL"},
+ {"ADDA Playback", NULL, "ADDA_DL0_CG"},
+
+ {"ADDA_DL_CH3", "DL0_CH1", "DL0"},
+ {"ADDA_DL_CH4", "DL0_CH2", "DL0"},
+
+ {"ADDA_DL_CH3", "DL1_CH1", "DL1"},
+ {"ADDA_DL_CH4", "DL1_CH2", "DL1"},
+
+ {"ADDA_DL_CH3", "DL2_CH1", "DL2"},
+ {"ADDA_DL_CH4", "DL2_CH2", "DL2"},
+
+ {"ADDA_DL_CH3", "DL3_CH1", "DL3"},
+ {"ADDA_DL_CH4", "DL3_CH2", "DL3"},
+
+ {"ADDA_DL_CH3", "DL4_CH1", "DL4"},
+ {"ADDA_DL_CH4", "DL4_CH2", "DL4"},
+
+ {"ADDA_DL_CH3", "DL5_CH1", "DL5"},
+ {"ADDA_DL_CH4", "DL5_CH2", "DL5"},
+
+ {"ADDA_DL_CH3", "DL6_CH1", "DL6"},
+ {"ADDA_DL_CH4", "DL6_CH2", "DL6"},
+
+ {"ADDA_DL_CH3", "DL7_CH1", "DL7"},
+ {"ADDA_DL_CH4", "DL7_CH2", "DL7"},
+
+ {"ADDA_DL_CH3", "DL8_CH1", "DL8"},
+ {"ADDA_DL_CH4", "DL8_CH2", "DL8"},
+
+ {"ADDA_DL_CH3", "DL_24CH_CH1", "DL_24CH"},
+ {"ADDA_DL_CH4", "DL_24CH_CH2", "DL_24CH"},
+ {"ADDA_DL_CH3", "DL_24CH_CH3", "DL_24CH"},
+ {"ADDA_DL_CH4", "DL_24CH_CH4", "DL_24CH"},
+
+ {"ADDA_DL_CH3", "DL24_CH1", "DL24"},
+ {"ADDA_DL_CH4", "DL24_CH2", "DL24"},
+
+ {"ADDA Capture", NULL, "ADDA Enable"},
+ {"ADDA Capture", NULL, "ADDA Capture Enable"},
+ {"ADDA Capture", NULL, "AUD_PAD_TOP"},
+ {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
+ {"ADDA Capture", NULL, "VS1_VOTER_UL"},
+ {"ADDA Capture", NULL, "ADDA_UL0_CG"},
+
+ /* capture */
+ {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
+ {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
+ {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"},
+
+ {"AP DMIC Capture", NULL, "ADDA Enable"},
+ {"AP DMIC Capture", NULL, "AP DMIC Capture Enable"},
+ {"AP DMIC Capture", NULL, "AP_DMIC_FIFO"},
+ {"AP DMIC Capture", NULL, "AP_DMIC_EN"},
+ {"AP DMIC Capture", NULL, "AP_DMIC0_CG"},
+
+ {"AP DMIC CH34 Capture", NULL, "ADDA Enable"},
+ {"AP DMIC CH34 Capture", NULL, "AP DMIC CH34 Capture Enable"},
+ {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_FIFO"},
+ {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"},
+ {"AP DMIC CH34 Capture", NULL, "AP_DMIC1_CG"},
+
+ {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
+ {"AP DMIC CH34 Capture", NULL, "AP_DMIC_INPUT"},
+};
+
+/* dai ops */
+static int set_playback_hw_params(struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ unsigned int rate = params_rate(params);
+ struct mtk_afe_adda_priv *adda_priv;
+ unsigned int dl_src_con0;
+ unsigned int dl_src_con1;
+ int id = dai->id;
+
+ adda_priv = afe_priv->dai_priv[id];
+ if (!adda_priv)
+ return -EINVAL;
+
+ adda_priv->dl_rate = rate;
+
+ /* set sampling rate */
+ dl_src_con0 = adda_dl_rate_transform(afe, rate) <<
+ AFE_DL_INPUT_MODE_CTL_SFT;
+
+ /* set output mode, UP_SAMPLING_RATE_X8 */
+ dl_src_con0 |= (0x3 << AFE_DL_OUTPUT_SEL_CTL_SFT);
+
+ /* turn off mute function */
+ dl_src_con0 |= (0x01 << AFE_DL_MUTE_CH2_OFF_CTL_PRE_SFT);
+ dl_src_con0 |= (0x01 << AFE_DL_MUTE_CH1_OFF_CTL_PRE_SFT);
+
+ /* set voice input data if input sample rate is 8k or 16k */
+ if (rate == 8000 || rate == 16000)
+ dl_src_con0 |= 0x01 << AFE_DL_VOICE_MODE_CTL_PRE_SFT;
+
+ /* SA suggest apply -0.3db to audio/speech path */
+ dl_src_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
+ AFE_DL_GAIN1_CTL_PRE_SFT;
+ dl_src_con1 |= MTK_AFE_ADDA_DL_GAIN_NORMAL <<
+ AFE_DL_GAIN2_CTL_PRE_SFT;
+
+ /* turn on down-link gain */
+ dl_src_con0 |= (0x01 << AFE_DL_GAIN_ON_CTL_PRE_SFT);
+
+ if (id == MT8189_DAI_ADDA) {
+ /* clean predistortion */
+ regmap_write(afe->regmap, AFE_ADDA_DL_PREDIS_CON0, 0);
+ regmap_write(afe->regmap, AFE_ADDA_DL_PREDIS_CON1, 0);
+
+ regmap_write(afe->regmap,
+ AFE_ADDA_DL_SRC_CON0, dl_src_con0);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DL_SRC_CON1, dl_src_con1);
+
+ /* set sdm gain */
+ regmap_update_bits(afe->regmap,
+ AFE_ADDA_DL_SDM_DCCOMP_CON,
+ AFE_DL_ATTGAIN_CTL_MASK_SFT,
+ AUDIO_SDM_LEVEL_NORMAL <<
+ AFE_DL_ATTGAIN_CTL_SFT);
+
+ /* 2nd sdm */
+ regmap_update_bits(afe->regmap,
+ AFE_ADDA_DL_SDM_DCCOMP_CON,
+ AFE_DL_USE_3RD_SDM_MASK_SFT,
+ AUDIO_SDM_2ND << AFE_DL_USE_3RD_SDM_SFT);
+
+ /* sdm auto reset */
+ regmap_write(afe->regmap,
+ AFE_ADDA_DL_SDM_AUTO_RESET_CON,
+ SDM_AUTO_RESET_THRESHOLD);
+ regmap_update_bits(afe->regmap,
+ AFE_ADDA_DL_SDM_AUTO_RESET_CON,
+ AFE_DL_SDM_AUTO_RESET_TEST_ON_SFT,
+ 0x1 << AFE_DL_SDM_AUTO_RESET_TEST_ON_SFT);
+ }
+
+ return 0;
+}
+
+static int set_capture_hw_params(struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ unsigned int rate = params_rate(params);
+ struct mtk_afe_adda_priv *adda_priv;
+ unsigned int voice_mode;
+ unsigned int ul_src_con0;
+ int id = dai->id;
+
+ adda_priv = afe_priv->dai_priv[id];
+ if (!adda_priv)
+ return -EINVAL;
+
+ adda_priv->ul_rate = rate;
+
+ voice_mode = adda_ul_rate_transform(afe, rate);
+
+ ul_src_con0 = (voice_mode << UL_VOICE_MODE_CH1_CH2_CTL_SFT) &
+ UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT;
+
+ /* enable iir */
+ ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
+ UL_IIR_ON_TMP_CTL_MASK_SFT;
+ ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
+ UL_IIRMODE_CTL_MASK_SFT;
+
+ switch (id) {
+ case MT8189_DAI_ADDA:
+ /* 35Hz @ 48k */
+ regmap_write(afe->regmap,
+ AFE_ADDA_UL0_IIR_COEF_02_01, 0x00000000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_UL0_IIR_COEF_04_03, 0x00003FB8);
+ regmap_write(afe->regmap,
+ AFE_ADDA_UL0_IIR_COEF_06_05, 0x3FB80000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_UL0_IIR_COEF_08_07, 0x3FB80000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_UL0_IIR_COEF_10_09, 0x0000C048);
+
+ regmap_write(afe->regmap,
+ AFE_ADDA_UL0_SRC_CON0, ul_src_con0);
+
+ /* mtkaif_rxif_data_mode = 0, amic */
+ regmap_update_bits(afe->regmap,
+ AFE_MTKAIF0_RX_CFG0,
+ RG_MTKAIF0_RXIF_DATA_MODE_MASK_SFT,
+ 0x0 << RG_MTKAIF0_RXIF_DATA_MODE_SFT);
+ break;
+ case MT8189_DAI_AP_DMIC:
+ /* 35Hz @ 48k */
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC0_IIR_COEF_02_01, 0x00000000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC0_IIR_COEF_04_03, 0x00003FB8);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC0_IIR_COEF_06_05, 0x3FB80000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC0_IIR_COEF_08_07, 0x3FB80000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC0_IIR_COEF_10_09, 0x0000C048);
+
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC0_SRC_CON0, ul_src_con0);
+ break;
+ case MT8189_DAI_AP_DMIC_CH34:
+ /* 35Hz @ 48k */
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC1_IIR_COEF_02_01, 0x00000000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC1_IIR_COEF_04_03, 0x00003FB8);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC1_IIR_COEF_06_05, 0x3FB80000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC1_IIR_COEF_08_07, 0x3FB80000);
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC1_IIR_COEF_10_09, 0x0000C048);
+
+ regmap_write(afe->regmap,
+ AFE_ADDA_DMIC1_SRC_CON0, ul_src_con0);
+ break;
+ default:
+ break;
+ }
+
+ /* ap dmic */
+ if (id == MT8189_DAI_AP_DMIC || id == MT8189_DAI_AP_DMIC_CH34)
+ mtk_adda_ul_src_enable_dmic(afe, id);
+
+ return 0;
+}
+
+static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ int id = dai->id;
+
+ if (id >= MT8189_DAI_NUM || id < 0)
+ return -EINVAL;
+
+ dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
+ __func__, id, substream->stream, params_rate(params));
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ return set_playback_hw_params(params, dai);
+ else
+ return set_capture_hw_params(params, dai);
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
+ .hw_params = mtk_dai_adda_hw_params,
+};
+
+/* dai driver */
+#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000)
+
+#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
+ SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 |\
+ SNDRV_PCM_RATE_48000)
+
+#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE |\
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
+ {
+ .name = "ADDA",
+ .id = MT8189_DAI_ADDA,
+ .playback = {
+ .stream_name = "ADDA Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MTK_ADDA_PLAYBACK_RATES,
+ .formats = MTK_ADDA_FORMATS,
+ },
+ .capture = {
+ .stream_name = "ADDA Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MTK_ADDA_CAPTURE_RATES,
+ .formats = MTK_ADDA_FORMATS,
+ },
+ .ops = &mtk_dai_adda_ops,
+ },
+ {
+ .name = "ADDA_CH34",
+ .id = MT8189_DAI_ADDA_CH34,
+ .playback = {
+ .stream_name = "ADDA CH34 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MTK_ADDA_PLAYBACK_RATES,
+ .formats = MTK_ADDA_FORMATS,
+ },
+ .ops = &mtk_dai_adda_ops,
+ },
+ {
+ .name = "AP_DMIC",
+ .id = MT8189_DAI_AP_DMIC,
+ .capture = {
+ .stream_name = "AP DMIC Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MTK_ADDA_CAPTURE_RATES,
+ .formats = MTK_ADDA_FORMATS,
+ },
+ .ops = &mtk_dai_adda_ops,
+ },
+ {
+ .name = "AP_DMIC_CH34",
+ .id = MT8189_DAI_AP_DMIC_CH34,
+ .capture = {
+ .stream_name = "AP DMIC CH34 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MTK_ADDA_CAPTURE_RATES,
+ .formats = MTK_ADDA_FORMATS,
+ },
+ .ops = &mtk_dai_adda_ops,
+ },
+};
+
+static int init_adda_priv_data(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ struct mtk_afe_adda_priv *adda_priv;
+ static const int adda_dai_list[] = {
+ MT8189_DAI_ADDA,
+ MT8189_DAI_ADDA_CH34,
+ };
+
+ for (int i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
+ adda_priv = devm_kzalloc(afe->dev,
+ sizeof(struct mtk_afe_adda_priv),
+ GFP_KERNEL);
+ if (!adda_priv)
+ return -ENOMEM;
+
+ afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
+ }
+
+ /* ap dmic priv share with adda */
+ afe_priv->dai_priv[MT8189_DAI_AP_DMIC] =
+ afe_priv->dai_priv[MT8189_DAI_ADDA];
+ afe_priv->dai_priv[MT8189_DAI_AP_DMIC_CH34] =
+ afe_priv->dai_priv[MT8189_DAI_ADDA_CH34];
+
+ return 0;
+}
+
+int mt8189_dai_adda_register(struct mtk_base_afe *afe)
+{
+ struct mtk_base_afe_dai *dai;
+ int ret;
+
+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+ if (!dai)
+ return -ENOMEM;
+
+ dai->dai_drivers = mtk_dai_adda_driver;
+ dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
+ dai->controls = mtk_adda_controls;
+ dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
+ dai->dapm_widgets = mtk_dai_adda_widgets;
+ dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
+ dai->dapm_routes = mtk_dai_adda_routes;
+ dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
+
+ ret = init_adda_priv_data(afe);
+ if (ret)
+ return ret;
+
+ list_add(&dai->list, &afe->sub_dais);
+
+ return 0;
+}
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 04/10] ASoC: mediatek: mt8189: support I2S in platform driver
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
` (2 preceding siblings ...)
2025-10-31 7:31 ` [PATCH v3 03/10] ASoC: mediatek: mt8189: support ADDA in platform driver Cyril Chao
@ 2025-10-31 7:31 ` Cyril Chao
2025-10-31 7:31 ` [PATCH v3 05/10] ASoC: mediatek: mt8189: support TDM " Cyril Chao
` (6 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:31 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add mt8189 I2S DAI driver support.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
sound/soc/mediatek/mt8189/mt8189-dai-i2s.c | 1463 ++++++++++++++++++++
1 file changed, 1463 insertions(+)
create mode 100644 sound/soc/mediatek/mt8189/mt8189-dai-i2s.c
diff --git a/sound/soc/mediatek/mt8189/mt8189-dai-i2s.c b/sound/soc/mediatek/mt8189/mt8189-dai-i2s.c
new file mode 100644
index 000000000000..94c49a662e2d
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-dai-i2s.c
@@ -0,0 +1,1463 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek ALSA SoC Audio DAI I2S Control
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#include <linux/bitops.h>
+#include <linux/regmap.h>
+
+#include <sound/pcm_params.h>
+
+#include "mt8189-afe-clk.h"
+#include "mt8189-afe-common.h"
+#include "mt8189-interconnection.h"
+
+#include "../common/mtk-afe-fe-dai.h"
+
+#define I2SIN0_MCLK_EN_W_NAME "I2SIN0_MCLK_EN"
+#define I2SIN1_MCLK_EN_W_NAME "I2SIN1_MCLK_EN"
+#define I2SOUT0_MCLK_EN_W_NAME "I2SOUT0_MCLK_EN"
+#define I2SOUT1_MCLK_EN_W_NAME "I2SOUT1_MCLK_EN"
+#define I2SOUT4_MCLK_EN_W_NAME "I2SOUT4_MCLK_EN"
+
+enum {
+ SUPPLY_SEQ_APLL,
+ SUPPLY_SEQ_I2S_MCLK_EN,
+ SUPPLY_SEQ_I2S_CG_EN,
+ SUPPLY_SEQ_I2S_EN,
+};
+
+/* this enum is merely for mtk_afe_i2s_priv declare */
+enum {
+ DAI_I2SIN0,
+ DAI_I2SIN1,
+ DAI_I2SOUT0,
+ DAI_I2SOUT1,
+ DAI_I2SOUT4,
+ DAI_I2S_NUM,
+};
+
+enum {
+ ETDM_CLK_SOURCE_H26M,
+ ETDM_CLK_SOURCE_APLL,
+ ETDM_CLK_SOURCE_SPDIF,
+ ETDM_CLK_SOURCE_HDMI,
+ ETDM_CLK_SOURCE_EARC,
+ ETDM_CLK_SOURCE_LINEIN,
+};
+
+enum {
+ ETDM_RELATCH_SEL_H26M,
+ ETDM_RELATCH_SEL_APLL,
+};
+
+enum {
+ ETDM_RATE_8K,
+ ETDM_RATE_12K,
+ ETDM_RATE_16K,
+ ETDM_RATE_24K,
+ ETDM_RATE_32K,
+ ETDM_RATE_48K,
+ ETDM_RATE_64K,
+ ETDM_RATE_96K,
+ ETDM_RATE_128K,
+ ETDM_RATE_192K,
+ ETDM_RATE_256K,
+ ETDM_RATE_384K,
+ ETDM_RATE_11025 = 16,
+ ETDM_RATE_22050,
+ ETDM_RATE_44100,
+ ETDM_RATE_88200,
+ ETDM_RATE_176400,
+ ETDM_RATE_352800,
+};
+
+enum {
+ ETDM_CONN_8K,
+ ETDM_CONN_11K,
+ ETDM_CONN_12K,
+ ETDM_CONN_16K = 4,
+ ETDM_CONN_22K,
+ ETDM_CONN_24K,
+ ETDM_CONN_32K = 8,
+ ETDM_CONN_44K,
+ ETDM_CONN_48K,
+ ETDM_CONN_88K = 13,
+ ETDM_CONN_96K,
+ ETDM_CONN_176K = 17,
+ ETDM_CONN_192K,
+ ETDM_CONN_352K = 21,
+ ETDM_CONN_384K,
+};
+
+enum {
+ ETDM_WLEN_8_BIT = 0x7,
+ ETDM_WLEN_16_BIT = 0xf,
+ ETDM_WLEN_32_BIT = 0x1f,
+};
+
+enum {
+ ETDM_SLAVE_SEL_ETDMIN0_MASTER,
+ ETDM_SLAVE_SEL_ETDMIN0_SLAVE,
+ ETDM_SLAVE_SEL_ETDMIN1_MASTER,
+ ETDM_SLAVE_SEL_ETDMIN1_SLAVE,
+ ETDM_SLAVE_SEL_ETDMIN2_MASTER,
+ ETDM_SLAVE_SEL_ETDMIN2_SLAVE,
+ ETDM_SLAVE_SEL_ETDMIN3_MASTER,
+ ETDM_SLAVE_SEL_ETDMIN3_SLAVE,
+ ETDM_SLAVE_SEL_ETDMOUT0_MASTER,
+ ETDM_SLAVE_SEL_ETDMOUT0_SLAVE,
+ ETDM_SLAVE_SEL_ETDMOUT1_MASTER,
+ ETDM_SLAVE_SEL_ETDMOUT1_SLAVE,
+ ETDM_SLAVE_SEL_ETDMOUT2_MASTER,
+ ETDM_SLAVE_SEL_ETDMOUT2_SLAVE,
+ ETDM_SLAVE_SEL_ETDMOUT3_MASTER,
+ ETDM_SLAVE_SEL_ETDMOUT3_SLAVE,
+};
+
+struct mtk_afe_i2s_priv {
+ int id;
+ int rate; /* for determine which apll to use */
+ int low_jitter_en;
+ unsigned int i2s_low_power_mask;
+ const char *share_property_name;
+ int share_i2s_id;
+
+ int mclk_id;
+ int mclk_rate;
+ int mclk_apll;
+
+ int ch_num;
+ int sync;
+ int ip_mode;
+ int slave_mode;
+ int lpbk_mode;
+};
+
+static unsigned int get_etdm_wlen(snd_pcm_format_t format)
+{
+ return snd_pcm_format_physical_width(format) <= 16 ?
+ ETDM_WLEN_16_BIT : ETDM_WLEN_32_BIT;
+}
+
+static unsigned int get_etdm_lrck_width(snd_pcm_format_t format)
+{
+ if (snd_pcm_format_physical_width(format) <= 1)
+ return 0;
+
+ /* The valid data bit number should be larger than 7 due to hardware limitation. */
+ return snd_pcm_format_physical_width(format) - 1;
+}
+
+static unsigned int get_etdm_rate(unsigned int rate)
+{
+ switch (rate) {
+ case 8000:
+ return ETDM_RATE_8K;
+ case 12000:
+ return ETDM_RATE_12K;
+ case 16000:
+ return ETDM_RATE_16K;
+ case 24000:
+ return ETDM_RATE_24K;
+ case 32000:
+ return ETDM_RATE_32K;
+ case 48000:
+ return ETDM_RATE_48K;
+ case 64000:
+ return ETDM_RATE_64K;
+ case 96000:
+ return ETDM_RATE_96K;
+ case 128000:
+ return ETDM_RATE_128K;
+ case 192000:
+ return ETDM_RATE_192K;
+ case 256000:
+ return ETDM_RATE_256K;
+ case 384000:
+ return ETDM_RATE_384K;
+ case 11025:
+ return ETDM_RATE_11025;
+ case 22050:
+ return ETDM_RATE_22050;
+ case 44100:
+ return ETDM_RATE_44100;
+ case 88200:
+ return ETDM_RATE_88200;
+ case 176400:
+ return ETDM_RATE_176400;
+ case 352800:
+ return ETDM_RATE_352800;
+ default:
+ return 0;
+ }
+}
+
+static unsigned int get_etdm_inconn_rate(unsigned int rate)
+{
+ switch (rate) {
+ case 8000:
+ return ETDM_CONN_8K;
+ case 12000:
+ return ETDM_CONN_12K;
+ case 16000:
+ return ETDM_CONN_16K;
+ case 24000:
+ return ETDM_CONN_24K;
+ case 32000:
+ return ETDM_CONN_32K;
+ case 48000:
+ return ETDM_CONN_48K;
+ case 96000:
+ return ETDM_CONN_96K;
+ case 192000:
+ return ETDM_CONN_192K;
+ case 384000:
+ return ETDM_CONN_384K;
+ case 11025:
+ return ETDM_CONN_11K;
+ case 22050:
+ return ETDM_CONN_22K;
+ case 44100:
+ return ETDM_CONN_44K;
+ case 88200:
+ return ETDM_CONN_88K;
+ case 176400:
+ return ETDM_CONN_176K;
+ case 352800:
+ return ETDM_CONN_352K;
+ default:
+ return 0;
+ }
+}
+
+static int get_i2s_id_by_name(struct mtk_base_afe *afe,
+ const char *name)
+{
+ if (strncmp(name, "I2SIN0", 6) == 0)
+ return MT8189_DAI_I2S_IN0;
+ else if (strncmp(name, "I2SIN1", 6) == 0)
+ return MT8189_DAI_I2S_IN1;
+ else if (strncmp(name, "I2SOUT0", 7) == 0)
+ return MT8189_DAI_I2S_OUT0;
+ else if (strncmp(name, "I2SOUT1", 7) == 0)
+ return MT8189_DAI_I2S_OUT1;
+ else if (strncmp(name, "I2SOUT4", 7) == 0)
+ return MT8189_DAI_I2S_OUT4;
+ else
+ return -EINVAL;
+}
+
+static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe,
+ const char *name)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int dai_id = get_i2s_id_by_name(afe, name);
+
+ if (dai_id < 0)
+ return NULL;
+
+ return afe_priv->dai_priv[dai_id];
+}
+
+static const char * const etdm_0_3_loopback_texts[] = {
+ "etdmin0", "etdmin1", "etdmout0", "etdmout1"
+};
+
+static const u32 etdm_loopback_values[] = {
+ 0, 2, 8, 10
+};
+
+static SOC_VALUE_ENUM_SINGLE_DECL(i2sin0_loopback_enum,
+ ETDM_0_3_COWORK_CON1,
+ ETDM_IN0_SDATA0_SEL_SFT,
+ ETDM_IN0_SDATA0_SEL_MASK,
+ etdm_0_3_loopback_texts,
+ etdm_loopback_values);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(i2sin1_loopback_enum,
+ ETDM_0_3_COWORK_CON1,
+ ETDM_IN1_SDATA0_SEL_SFT,
+ ETDM_IN1_SDATA0_SEL_MASK,
+ etdm_0_3_loopback_texts,
+ etdm_loopback_values);
+
+static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = {
+ SOC_ENUM("I2SIN0 Loopback", i2sin0_loopback_enum),
+ SOC_ENUM("I2SIN1 Loopback", i2sin1_loopback_enum),
+};
+
+/*
+ * I2S virtual mux to output widget
+ * If the I2S interface is required but not connected to an actual codec dai,
+ * a Dummy_Widget must be used to establish the connection.
+ */
+static const char *const i2s_mux_map[] = {
+ "Normal", "Dummy_Widget",
+};
+
+static int i2s_mux_map_value[] = {
+ 0, 1,
+};
+
+static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum,
+ SND_SOC_NOPM,
+ 0,
+ 1,
+ i2s_mux_map,
+ i2s_mux_map_value);
+
+static const struct snd_kcontrol_new i2s_in0_mux_control =
+ SOC_DAPM_ENUM("I2S IN0 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_in1_mux_control =
+ SOC_DAPM_ENUM("I2S IN1 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out0_mux_control =
+ SOC_DAPM_ENUM("I2S OUT0 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out1_mux_control =
+ SOC_DAPM_ENUM("I2S OUT1 Select", i2s_mux_map_enum);
+static const struct snd_kcontrol_new i2s_out4_mux_control =
+ SOC_DAPM_ENUM("I2S OUT4 Select", i2s_mux_map_enum);
+
+static const struct snd_kcontrol_new mtk_i2sout0_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN108_1, I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN108_1, I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN108_1, I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN108_1, I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN108_1, I_DL4_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN108_1, I_DL5_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN108_1, I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN108_1, I_DL7_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN108_1, I_DL8_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN108_1, I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN108_0,
+ I_GAIN0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN108_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN108_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout0_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN109_1, I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN109_1, I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN109_1, I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN109_1, I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN109_1, I_DL4_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN109_1, I_DL5_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN109_1, I_DL6_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN109_1, I_DL7_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN109_1, I_DL8_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN109_1, I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN109_0,
+ I_GAIN0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN109_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN109_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN109_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout1_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN110_1, I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN110_1, I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN110_1, I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN110_1, I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN110_1, I_DL4_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN110_1, I_DL5_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN110_1, I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN110_1, I_DL7_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN110_1, I_DL8_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN110_1, I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN110_0,
+ I_GAIN0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN110_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN110_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout1_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN111_1, I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN111_1, I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN111_1, I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN111_1, I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN111_1, I_DL4_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN111_1, I_DL5_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN111_1, I_DL6_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN111_1, I_DL7_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN111_1, I_DL8_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN111_1, I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN111_0,
+ I_GAIN0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN111_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN111_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN111_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN116_1, I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN116_1, I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN116_1, I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN116_1, I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN116_1, I_DL4_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN116_1, I_DL5_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN116_1, I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN116_1, I_DL7_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN116_1, I_DL8_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN116_1, I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH1", AFE_CONN116_2, I_DL24_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN116_0,
+ I_GAIN0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN116_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN116_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN116_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN116_6,
+ I_SRC_2_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN117_1, I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN117_1, I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN117_1, I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN117_1, I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN117_1, I_DL4_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN117_1, I_DL5_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN117_1, I_DL6_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN117_1, I_DL7_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN117_1, I_DL8_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN117_1, I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL24_CH2", AFE_CONN117_2, I_DL24_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN117_0,
+ I_GAIN0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN117_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN117_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN117_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN117_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN117_6,
+ I_SRC_2_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch3_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH3", AFE_CONN118_1, I_DL_24CH_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN118_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch4_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH4", AFE_CONN119_1, I_DL_24CH_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN118_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch5_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH5", AFE_CONN120_1, I_DL_24CH_CH5, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch6_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH6", AFE_CONN121_1, I_DL_24CH_CH6, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch7_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH7", AFE_CONN122_1, I_DL_24CH_CH7, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_i2sout4_ch8_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH8", AFE_CONN123_1, I_DL_24CH_CH8, 1, 0),
+};
+
+static int mtk_apll_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+
+ dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
+ __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (strcmp(w->name, APLL1_W_NAME) == 0)
+ mt8189_apll1_enable(afe);
+ else
+ mt8189_apll2_enable(afe);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ if (strcmp(w->name, APLL1_W_NAME) == 0)
+ mt8189_apll1_disable(afe);
+ else
+ mt8189_apll2_disable(afe);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mtk_afe_i2s_priv *i2s_priv;
+
+ dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
+ __func__, w->name, event);
+
+ i2s_priv = get_i2s_priv_by_name(afe, w->name);
+ if (!i2s_priv)
+ return -EINVAL;
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ mt8189_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ i2s_priv->mclk_rate = 0;
+ mt8189_mck_disable(afe, i2s_priv->mclk_id);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
+ SND_SOC_DAPM_MIXER("I2SOUT0_CH1", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout0_ch1_mix,
+ ARRAY_SIZE(mtk_i2sout0_ch1_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT0_CH2", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout0_ch2_mix,
+ ARRAY_SIZE(mtk_i2sout0_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("I2SOUT1_CH1", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout1_ch1_mix,
+ ARRAY_SIZE(mtk_i2sout1_ch1_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT1_CH2", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout1_ch2_mix,
+ ARRAY_SIZE(mtk_i2sout1_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("I2SOUT4_CH1", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout4_ch1_mix,
+ ARRAY_SIZE(mtk_i2sout4_ch1_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT4_CH2", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout4_ch2_mix,
+ ARRAY_SIZE(mtk_i2sout4_ch2_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT4_CH3", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout4_ch3_mix,
+ ARRAY_SIZE(mtk_i2sout4_ch3_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT4_CH4", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout4_ch4_mix,
+ ARRAY_SIZE(mtk_i2sout4_ch4_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT4_CH5", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout4_ch5_mix,
+ ARRAY_SIZE(mtk_i2sout4_ch5_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT4_CH6", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout4_ch6_mix,
+ ARRAY_SIZE(mtk_i2sout4_ch6_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT4_CH7", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout4_ch7_mix,
+ ARRAY_SIZE(mtk_i2sout4_ch7_mix)),
+ SND_SOC_DAPM_MIXER("I2SOUT4_CH8", SND_SOC_NOPM, 0, 0,
+ mtk_i2sout4_ch8_mix,
+ ARRAY_SIZE(mtk_i2sout4_ch8_mix)),
+
+ /* i2s en*/
+ SND_SOC_DAPM_SUPPLY_S("I2SIN0_EN", SUPPLY_SEQ_I2S_EN,
+ ETDM_IN0_CON0, REG_ETDM_IN_EN_SFT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2SIN1_EN", SUPPLY_SEQ_I2S_EN,
+ ETDM_IN1_CON0, REG_ETDM_IN_EN_SFT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2SOUT0_EN", SUPPLY_SEQ_I2S_EN,
+ ETDM_OUT0_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2SOUT1_EN", SUPPLY_SEQ_I2S_EN,
+ ETDM_OUT1_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2SOUT4_EN", SUPPLY_SEQ_I2S_EN,
+ ETDM_OUT4_CON0, OUT_REG_ETDM_OUT_EN_SFT, 0,
+ NULL, 0),
+
+ /* i2s mclk en */
+ SND_SOC_DAPM_SUPPLY_S(I2SIN0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_mclk_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SUPPLY_S(I2SIN1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_mclk_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SUPPLY_S(I2SOUT0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_mclk_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SUPPLY_S(I2SOUT1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_mclk_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SUPPLY_S(I2SOUT4_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_mclk_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /* cg */
+ SND_SOC_DAPM_SUPPLY_S("I2SOUT0_CG", SUPPLY_SEQ_I2S_CG_EN,
+ AUDIO_TOP_CON2, PDN_ETDM_OUT0_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2SOUT1_CG", SUPPLY_SEQ_I2S_CG_EN,
+ AUDIO_TOP_CON2, PDN_ETDM_OUT1_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2SOUT4_CG", SUPPLY_SEQ_I2S_CG_EN,
+ AUDIO_TOP_CON2, PDN_ETDM_OUT4_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2SIN0_CG", SUPPLY_SEQ_I2S_CG_EN,
+ AUDIO_TOP_CON2, PDN_ETDM_IN0_SFT, 1,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2SIN1_CG", SUPPLY_SEQ_I2S_CG_EN,
+ AUDIO_TOP_CON2, PDN_ETDM_IN1_SFT, 1,
+ NULL, 0),
+
+ /* apll */
+ SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
+ SND_SOC_NOPM, 0, 0,
+ mtk_apll_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
+ SND_SOC_NOPM, 0, 0,
+ mtk_apll_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /* allow i2s on without codec on */
+ SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"),
+ SND_SOC_DAPM_MUX("I2S_OUT0_Mux",
+ SND_SOC_NOPM, 0, 0, &i2s_out0_mux_control),
+ SND_SOC_DAPM_MUX("I2S_OUT1_Mux",
+ SND_SOC_NOPM, 0, 0, &i2s_out1_mux_control),
+ SND_SOC_DAPM_MUX("I2S_OUT4_Mux",
+ SND_SOC_NOPM, 0, 0, &i2s_out4_mux_control),
+
+ SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"),
+ SND_SOC_DAPM_MUX("I2S_IN0_Mux",
+ SND_SOC_NOPM, 0, 0, &i2s_in0_mux_control),
+ SND_SOC_DAPM_MUX("I2S_IN1_Mux",
+ SND_SOC_NOPM, 0, 0, &i2s_in1_mux_control),
+};
+
+static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source,
+ struct snd_soc_dapm_widget *sink)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mtk_afe_i2s_priv *i2s_priv;
+
+ i2s_priv = get_i2s_priv_by_name(afe, sink->name);
+ if (!i2s_priv)
+ return 0;
+
+ if (i2s_priv->share_i2s_id < 0)
+ return 0;
+
+ return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name);
+}
+
+static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source,
+ struct snd_soc_dapm_widget *sink)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mtk_afe_i2s_priv *i2s_priv;
+ int cur_apll;
+ int needed_apll;
+
+ i2s_priv = get_i2s_priv_by_name(afe, sink->name);
+ if (!i2s_priv)
+ return 0;
+
+ /* which apll */
+ cur_apll = mt8189_get_apll_by_name(afe, source->name);
+
+ /* choose APLL from i2s rate */
+ needed_apll = mt8189_get_apll_by_rate(afe, i2s_priv->rate);
+
+ return needed_apll == cur_apll;
+}
+
+static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source,
+ struct snd_soc_dapm_widget *sink)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mtk_afe_i2s_priv *i2s_priv;
+ int i2s_num;
+
+ i2s_priv = get_i2s_priv_by_name(afe, sink->name);
+ if (!i2s_priv)
+ return 0;
+
+ i2s_num = get_i2s_id_by_name(afe, source->name);
+ if (get_i2s_id_by_name(afe, sink->name) == i2s_num)
+ return i2s_priv->mclk_rate > 0;
+
+ /* check if share i2s need mclk */
+ if (i2s_priv->share_i2s_id < 0)
+ return 0;
+
+ if (i2s_priv->share_i2s_id == i2s_num)
+ return i2s_priv->mclk_rate > 0;
+
+ return 0;
+}
+
+static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
+ struct snd_soc_dapm_widget *sink)
+{
+ struct snd_soc_dapm_widget *w = sink;
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mtk_afe_i2s_priv *i2s_priv;
+ int cur_apll;
+
+ i2s_priv = get_i2s_priv_by_name(afe, w->name);
+ if (!i2s_priv)
+ return 0;
+
+ /* which apll */
+ cur_apll = mt8189_get_apll_by_name(afe, source->name);
+
+ return i2s_priv->mclk_apll == cur_apll;
+}
+
+static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
+ /* I2SIN0 */
+ {"I2SIN0", NULL, "I2SIN0_EN"},
+ {"I2SIN0", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+ {"I2SIN0", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+ {"I2SIN0", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+ {"I2SIN0", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+
+ {"I2SIN0", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SIN0", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SIN0", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SIN0", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SIN0", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {I2SIN0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+ {I2SIN0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+ {"I2SIN0", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SIN0", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SIN0", NULL, "I2SOUT0_CG"},
+ {"I2SIN0", NULL, "I2SIN0_CG"},
+
+ /* i2sin1 */
+ {"I2SIN1", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+ {"I2SIN1", NULL, "I2SIN1_EN"},
+ {"I2SIN1", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+ {"I2SIN1", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+ {"I2SIN1", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+
+ {"I2SIN1", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SIN1", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SIN1", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SIN1", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SIN1", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {I2SIN1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+ {I2SIN1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+ {"I2SIN1", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SIN1", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SIN1", NULL, "I2SIN1_CG"},
+ {"I2SIN1", NULL, "I2SOUT1_CG"},
+
+ /* i2sout0 */
+ {"I2SOUT0_CH1", "DL0_CH1", "DL0"},
+ {"I2SOUT0_CH2", "DL0_CH2", "DL0"},
+ {"I2SOUT0_CH1", "DL1_CH1", "DL1"},
+ {"I2SOUT0_CH2", "DL1_CH2", "DL1"},
+ {"I2SOUT0_CH1", "DL2_CH1", "DL2"},
+ {"I2SOUT0_CH2", "DL2_CH2", "DL2"},
+ {"I2SOUT0_CH1", "DL3_CH1", "DL3"},
+ {"I2SOUT0_CH2", "DL3_CH2", "DL3"},
+ {"I2SOUT0_CH1", "DL4_CH1", "DL4"},
+ {"I2SOUT0_CH2", "DL4_CH2", "DL4"},
+ {"I2SOUT0_CH1", "DL5_CH1", "DL5"},
+ {"I2SOUT0_CH2", "DL5_CH2", "DL5"},
+ {"I2SOUT0_CH1", "DL6_CH1", "DL6"},
+ {"I2SOUT0_CH2", "DL6_CH2", "DL6"},
+ {"I2SOUT0_CH1", "DL7_CH1", "DL7"},
+ {"I2SOUT0_CH2", "DL7_CH2", "DL7"},
+ {"I2SOUT0_CH1", "DL8_CH1", "DL8"},
+ {"I2SOUT0_CH2", "DL8_CH2", "DL8"},
+ {"I2SOUT0_CH1", "DL_24CH_CH1", "DL_24CH"},
+ {"I2SOUT0_CH2", "DL_24CH_CH2", "DL_24CH"},
+
+ {"I2SOUT0", NULL, "I2SOUT0_CH1"},
+ {"I2SOUT0", NULL, "I2SOUT0_CH2"},
+
+ {"I2SOUT0", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT0", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT0", NULL, "I2SOUT0_EN"},
+ {"I2SOUT0", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT0", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+
+ {"I2SOUT0", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT0", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT0", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT0", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT0", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {I2SOUT0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+ {I2SOUT0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+ {"I2SOUT0", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SOUT0", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SOUT0", NULL, "I2SOUT0_CG"},
+ {"I2SOUT0", NULL, "I2SIN0_CG"},
+
+ /* i2sout1 */
+ {"I2SOUT1_CH1", "DL0_CH1", "DL0"},
+ {"I2SOUT1_CH2", "DL0_CH2", "DL0"},
+ {"I2SOUT1_CH1", "DL1_CH1", "DL1"},
+ {"I2SOUT1_CH2", "DL1_CH2", "DL1"},
+ {"I2SOUT1_CH1", "DL2_CH1", "DL2"},
+ {"I2SOUT1_CH2", "DL2_CH2", "DL2"},
+ {"I2SOUT1_CH1", "DL3_CH1", "DL3"},
+ {"I2SOUT1_CH2", "DL3_CH2", "DL3"},
+ {"I2SOUT1_CH1", "DL4_CH1", "DL4"},
+ {"I2SOUT1_CH2", "DL4_CH2", "DL4"},
+ {"I2SOUT1_CH1", "DL5_CH1", "DL5"},
+ {"I2SOUT1_CH2", "DL5_CH2", "DL5"},
+ {"I2SOUT1_CH1", "DL6_CH1", "DL6"},
+ {"I2SOUT1_CH2", "DL6_CH2", "DL6"},
+ {"I2SOUT1_CH1", "DL7_CH1", "DL7"},
+ {"I2SOUT1_CH2", "DL7_CH2", "DL7"},
+ {"I2SOUT1_CH1", "DL8_CH1", "DL8"},
+ {"I2SOUT1_CH2", "DL8_CH2", "DL8"},
+ {"I2SOUT1_CH1", "DL_24CH_CH1", "DL_24CH"},
+ {"I2SOUT1_CH2", "DL_24CH_CH2", "DL_24CH"},
+
+ {"I2SOUT1", NULL, "I2SOUT1_CH1"},
+ {"I2SOUT1", NULL, "I2SOUT1_CH2"},
+
+ {"I2SOUT1", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT1", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT1", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT1", NULL, "I2SOUT1_EN"},
+ {"I2SOUT1", NULL, "I2SOUT4_EN", mtk_afe_i2s_share_connect},
+
+ {"I2SOUT1", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT1", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT1", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT1", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT1", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {I2SOUT1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+ {I2SOUT1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+ {"I2SOUT1", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SOUT1", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SOUT1", NULL, "I2SOUT1_CG"},
+ {"I2SOUT1", NULL, "I2SIN1_CG"},
+
+ /* i2sout4 */
+ {"I2SOUT4_CH1", "DL0_CH1", "DL0"},
+ {"I2SOUT4_CH2", "DL0_CH2", "DL0"},
+ {"I2SOUT4_CH1", "DL1_CH1", "DL1"},
+ {"I2SOUT4_CH2", "DL1_CH2", "DL1"},
+ {"I2SOUT4_CH1", "DL2_CH1", "DL2"},
+ {"I2SOUT4_CH2", "DL2_CH2", "DL2"},
+ {"I2SOUT4_CH1", "DL3_CH1", "DL3"},
+ {"I2SOUT4_CH2", "DL3_CH2", "DL3"},
+ {"I2SOUT4_CH1", "DL4_CH1", "DL4"},
+ {"I2SOUT4_CH2", "DL4_CH2", "DL4"},
+ {"I2SOUT4_CH1", "DL5_CH1", "DL5"},
+ {"I2SOUT4_CH2", "DL5_CH2", "DL5"},
+ {"I2SOUT4_CH1", "DL6_CH1", "DL6"},
+ {"I2SOUT4_CH2", "DL6_CH2", "DL6"},
+ {"I2SOUT4_CH1", "DL7_CH1", "DL7"},
+ {"I2SOUT4_CH2", "DL7_CH2", "DL7"},
+ {"I2SOUT4_CH1", "DL8_CH1", "DL8"},
+ {"I2SOUT4_CH2", "DL8_CH2", "DL8"},
+ {"I2SOUT4_CH1", "DL_24CH_CH1", "DL_24CH"},
+ {"I2SOUT4_CH2", "DL_24CH_CH2", "DL_24CH"},
+ {"I2SOUT4_CH3", "DL_24CH_CH3", "DL_24CH"},
+ {"I2SOUT4_CH4", "DL_24CH_CH4", "DL_24CH"},
+ {"I2SOUT4_CH5", "DL_24CH_CH5", "DL_24CH"},
+ {"I2SOUT4_CH6", "DL_24CH_CH6", "DL_24CH"},
+ {"I2SOUT4_CH7", "DL_24CH_CH7", "DL_24CH"},
+ {"I2SOUT4_CH8", "DL_24CH_CH8", "DL_24CH"},
+ {"I2SOUT4_CH1", "DL24_CH1", "DL24"},
+ {"I2SOUT4_CH2", "DL24_CH2", "DL24"},
+
+ {"I2SOUT4", NULL, "I2SOUT4_CH1"},
+ {"I2SOUT4", NULL, "I2SOUT4_CH2"},
+ {"I2SOUT4", NULL, "I2SOUT4_CH3"},
+ {"I2SOUT4", NULL, "I2SOUT4_CH4"},
+ {"I2SOUT4", NULL, "I2SOUT4_CH5"},
+ {"I2SOUT4", NULL, "I2SOUT4_CH6"},
+ {"I2SOUT4", NULL, "I2SOUT4_CH7"},
+ {"I2SOUT4", NULL, "I2SOUT4_CH8"},
+
+ {"I2SOUT4", NULL, "I2SIN0_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT4", NULL, "I2SIN1_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT4", NULL, "I2SOUT0_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT4", NULL, "I2SOUT1_EN", mtk_afe_i2s_share_connect},
+ {"I2SOUT4", NULL, "I2SOUT4_EN"},
+
+ {"I2SOUT4", NULL, I2SIN0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT4", NULL, I2SIN1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT4", NULL, I2SOUT0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT4", NULL, I2SOUT1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {"I2SOUT4", NULL, I2SOUT4_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
+ {I2SOUT4_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
+ {I2SOUT4_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
+ {"I2SOUT4", NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
+ {"I2SOUT4", NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
+ /* CG */
+ {"I2SOUT4", NULL, "I2SOUT4_CG"},
+
+ /* allow i2s on without codec on */
+ {"I2SIN0", NULL, "I2S_IN0_Mux"},
+ {"I2S_IN0_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
+
+ {"I2SIN1", NULL, "I2S_IN1_Mux"},
+ {"I2S_IN1_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
+
+ {"I2S_OUT0_Mux", "Dummy_Widget", "I2SOUT0"},
+ {"I2S_DUMMY_OUT", NULL, "I2S_OUT0_Mux"},
+
+ {"I2S_OUT1_Mux", "Dummy_Widget", "I2SOUT1"},
+ {"I2S_DUMMY_OUT", NULL, "I2S_OUT1_Mux"},
+
+ {"I2S_OUT4_Mux", "Dummy_Widget", "I2SOUT4"},
+ {"I2S_DUMMY_OUT", NULL, "I2S_OUT4_Mux"},
+};
+
+/* i2s dai ops*/
+static int mtk_dai_i2s_config(struct mtk_base_afe *afe,
+ struct snd_pcm_hw_params *params,
+ int i2s_id)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ struct mtk_afe_i2s_priv *i2s_priv;
+ unsigned int rate = params_rate(params);
+ snd_pcm_format_t format = params_format(params);
+ int ret;
+
+ if (i2s_id >= MT8189_DAI_NUM || i2s_id < 0)
+ return -EINVAL;
+
+ i2s_priv = afe_priv->dai_priv[i2s_id];
+ if (!i2s_priv)
+ return -EINVAL;
+
+ i2s_priv->rate = rate;
+
+ dev_dbg(afe->dev, "%s(), id %d, rate %d, format %d\n",
+ __func__, i2s_id, rate, format);
+
+ switch (i2s_id) {
+ case MT8189_DAI_I2S_IN0:
+ /* ---etdm in --- */
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON1,
+ REG_INITIAL_COUNT_MASK_SFT,
+ 0x5 << REG_INITIAL_COUNT_SFT);
+ /* 3: pad top 5: no pad top */
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON1,
+ REG_INITIAL_POINT_MASK_SFT,
+ 0x5 << REG_INITIAL_POINT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON1,
+ REG_LRCK_RESET_MASK_SFT,
+ 0x1 << REG_LRCK_RESET_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON2,
+ REG_CLOCK_SOURCE_SEL_MASK_SFT,
+ ETDM_CLK_SOURCE_APLL <<
+ REG_CLOCK_SOURCE_SEL_SFT);
+ /* 0: manual 1: auto */
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON2,
+ REG_CK_EN_SEL_AUTO_MASK_SFT,
+ 0x1 << REG_CK_EN_SEL_AUTO_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON3,
+ REG_FS_TIMING_SEL_MASK_SFT,
+ get_etdm_rate(rate) <<
+ REG_FS_TIMING_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON4,
+ REG_RELATCH_1X_EN_SEL_MASK_SFT,
+ get_etdm_inconn_rate(rate) <<
+ REG_RELATCH_1X_EN_SEL_SFT);
+
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON8,
+ REG_ETDM_USE_AFIFO_MASK_SFT,
+ 0x0 << REG_ETDM_USE_AFIFO_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON8,
+ REG_AFIFO_MODE_MASK_SFT,
+ 0x0 << REG_AFIFO_MODE_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON9,
+ REG_ALMOST_END_CH_COUNT_MASK_SFT,
+ 0x0 << REG_ALMOST_END_CH_COUNT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON9,
+ REG_ALMOST_END_BIT_COUNT_MASK_SFT,
+ 0x0 << REG_ALMOST_END_BIT_COUNT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON9,
+ REG_OUT2LATCH_TIME_MASK_SFT,
+ 0x6 << REG_OUT2LATCH_TIME_SFT);
+
+ /* 5: TDM Mode */
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON0,
+ REG_FMT_MASK_SFT, 0x0 << REG_FMT_SFT);
+
+ /* APLL */
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON0,
+ REG_RELATCH_1X_EN_DOMAIN_SEL_MASK_SFT,
+ ETDM_RELATCH_SEL_APLL
+ << REG_RELATCH_1X_EN_DOMAIN_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON0,
+ REG_BIT_LENGTH_MASK_SFT,
+ get_etdm_lrck_width(format) <<
+ REG_BIT_LENGTH_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN0_CON0,
+ REG_WORD_LENGTH_MASK_SFT,
+ get_etdm_wlen(format) <<
+ REG_WORD_LENGTH_SFT);
+
+ /* ---etdm cowork --- */
+ regmap_update_bits(afe->regmap, ETDM_0_3_COWORK_CON0,
+ ETDM_IN0_SLAVE_SEL_MASK_SFT,
+ ETDM_SLAVE_SEL_ETDMOUT0_MASTER
+ << ETDM_IN0_SLAVE_SEL_SFT);
+ break;
+ case MT8189_DAI_I2S_IN1:
+ /* ---etdm in --- */
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON1,
+ REG_INITIAL_COUNT_MASK_SFT,
+ 0x5 << REG_INITIAL_COUNT_SFT);
+ /* 3: pad top 5: no pad top */
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON1,
+ REG_INITIAL_POINT_MASK_SFT,
+ 0x5 << REG_INITIAL_POINT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON1,
+ REG_LRCK_RESET_MASK_SFT,
+ 0x1 << REG_LRCK_RESET_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON2,
+ REG_CLOCK_SOURCE_SEL_MASK_SFT,
+ ETDM_CLK_SOURCE_APLL <<
+ REG_CLOCK_SOURCE_SEL_SFT);
+ /* 0: manual 1: auto */
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON2,
+ REG_CK_EN_SEL_AUTO_MASK_SFT,
+ 0x1 << REG_CK_EN_SEL_AUTO_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON3,
+ REG_FS_TIMING_SEL_MASK_SFT,
+ get_etdm_rate(rate) <<
+ REG_FS_TIMING_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON4,
+ REG_RELATCH_1X_EN_SEL_MASK_SFT,
+ get_etdm_inconn_rate(rate) <<
+ REG_RELATCH_1X_EN_SEL_SFT);
+
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON8,
+ REG_ETDM_USE_AFIFO_MASK_SFT,
+ 0x0 << REG_ETDM_USE_AFIFO_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON8,
+ REG_AFIFO_MODE_MASK_SFT,
+ 0x0 << REG_AFIFO_MODE_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON9,
+ REG_ALMOST_END_CH_COUNT_MASK_SFT,
+ 0x0 << REG_ALMOST_END_CH_COUNT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON9,
+ REG_ALMOST_END_BIT_COUNT_MASK_SFT,
+ 0x0 << REG_ALMOST_END_BIT_COUNT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON9,
+ REG_OUT2LATCH_TIME_MASK_SFT,
+ 0x6 << REG_OUT2LATCH_TIME_SFT);
+
+ /* 5: TDM Mode */
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON0,
+ REG_FMT_MASK_SFT, 0x0 << REG_FMT_SFT);
+
+ /* APLL */
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON0,
+ REG_RELATCH_1X_EN_DOMAIN_SEL_MASK_SFT,
+ ETDM_RELATCH_SEL_APLL
+ << REG_RELATCH_1X_EN_DOMAIN_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON0,
+ REG_BIT_LENGTH_MASK_SFT,
+ get_etdm_lrck_width(format) <<
+ REG_BIT_LENGTH_SFT);
+ regmap_update_bits(afe->regmap, ETDM_IN1_CON0,
+ REG_WORD_LENGTH_MASK_SFT,
+ get_etdm_wlen(format) <<
+ REG_WORD_LENGTH_SFT);
+
+ /* ---etdm cowork --- */
+ regmap_update_bits(afe->regmap, ETDM_0_3_COWORK_CON1,
+ ETDM_IN1_SLAVE_SEL_MASK_SFT,
+ ETDM_SLAVE_SEL_ETDMOUT1_MASTER
+ << ETDM_IN1_SLAVE_SEL_SFT);
+ break;
+ case MT8189_DAI_I2S_OUT0:
+ /* ---etdm out --- */
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON1,
+ OUT_REG_INITIAL_COUNT_MASK_SFT,
+ 0x5 << OUT_REG_INITIAL_COUNT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON1,
+ OUT_REG_INITIAL_POINT_MASK_SFT,
+ 0x6 << OUT_REG_INITIAL_POINT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON1,
+ OUT_REG_LRCK_RESET_MASK_SFT,
+ 0x1 << OUT_REG_LRCK_RESET_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON4,
+ OUT_REG_FS_TIMING_SEL_MASK_SFT,
+ get_etdm_rate(rate) <<
+ OUT_REG_FS_TIMING_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON4,
+ OUT_REG_CLOCK_SOURCE_SEL_MASK_SFT,
+ ETDM_CLK_SOURCE_APLL <<
+ OUT_REG_CLOCK_SOURCE_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON4,
+ OUT_REG_RELATCH_EN_SEL_MASK_SFT,
+ get_etdm_inconn_rate(rate) <<
+ OUT_REG_RELATCH_EN_SEL_SFT);
+ /* 5: TDM Mode */
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON0,
+ OUT_REG_FMT_MASK_SFT,
+ 0x0 << OUT_REG_FMT_SFT);
+
+ /* APLL */
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON0,
+ OUT_REG_RELATCH_DOMAIN_SEL_MASK_SFT,
+ ETDM_RELATCH_SEL_APLL
+ << OUT_REG_RELATCH_DOMAIN_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON0,
+ OUT_REG_BIT_LENGTH_MASK_SFT,
+ get_etdm_lrck_width(format) <<
+ OUT_REG_BIT_LENGTH_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT0_CON0,
+ OUT_REG_WORD_LENGTH_MASK_SFT,
+ get_etdm_wlen(format) <<
+ OUT_REG_WORD_LENGTH_SFT);
+
+ /* ---etdm cowork --- */
+ regmap_update_bits(afe->regmap, ETDM_0_3_COWORK_CON0,
+ ETDM_OUT0_SLAVE_SEL_MASK_SFT,
+ ETDM_SLAVE_SEL_ETDMIN0_MASTER
+ << ETDM_OUT0_SLAVE_SEL_SFT);
+ break;
+ case MT8189_DAI_I2S_OUT1:
+ /* ---etdm out --- */
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON1,
+ OUT_REG_INITIAL_COUNT_MASK_SFT,
+ 0x5 << OUT_REG_INITIAL_COUNT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON1,
+ OUT_REG_INITIAL_POINT_MASK_SFT,
+ 0x6 << OUT_REG_INITIAL_POINT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON1,
+ OUT_REG_LRCK_RESET_MASK_SFT,
+ 0x1 << OUT_REG_LRCK_RESET_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON4,
+ OUT_REG_FS_TIMING_SEL_MASK_SFT,
+ get_etdm_rate(rate) <<
+ OUT_REG_FS_TIMING_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON4,
+ OUT_REG_CLOCK_SOURCE_SEL_MASK_SFT,
+ ETDM_CLK_SOURCE_APLL <<
+ OUT_REG_CLOCK_SOURCE_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON4,
+ OUT_REG_RELATCH_EN_SEL_MASK_SFT,
+ get_etdm_inconn_rate(rate) <<
+ OUT_REG_RELATCH_EN_SEL_SFT);
+ /* 5: TDM Mode */
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON0,
+ OUT_REG_FMT_MASK_SFT,
+ 0x0 << OUT_REG_FMT_SFT);
+
+ /* APLL */
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON0,
+ OUT_REG_RELATCH_DOMAIN_SEL_MASK_SFT,
+ ETDM_RELATCH_SEL_APLL
+ << OUT_REG_RELATCH_DOMAIN_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON0,
+ OUT_REG_BIT_LENGTH_MASK_SFT,
+ get_etdm_lrck_width(format) <<
+ OUT_REG_BIT_LENGTH_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT1_CON0,
+ OUT_REG_WORD_LENGTH_MASK_SFT,
+ get_etdm_wlen(format) <<
+ OUT_REG_WORD_LENGTH_SFT);
+
+ /* ---etdm cowork --- */
+ regmap_update_bits(afe->regmap, ETDM_0_3_COWORK_CON0,
+ ETDM_OUT1_SLAVE_SEL_MASK_SFT,
+ ETDM_SLAVE_SEL_ETDMIN1_MASTER
+ << ETDM_OUT1_SLAVE_SEL_SFT);
+ break;
+ case MT8189_DAI_I2S_OUT4:
+ /* ---etdm out --- */
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON1,
+ OUT_REG_INITIAL_COUNT_MASK_SFT,
+ 0x5 << OUT_REG_INITIAL_COUNT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON1,
+ OUT_REG_INITIAL_POINT_MASK_SFT,
+ 0x6 << OUT_REG_INITIAL_POINT_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON1,
+ OUT_REG_LRCK_RESET_MASK_SFT,
+ 0x1 << OUT_REG_LRCK_RESET_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON4,
+ OUT_REG_FS_TIMING_SEL_MASK_SFT,
+ get_etdm_rate(rate) <<
+ OUT_REG_FS_TIMING_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON4,
+ OUT_REG_CLOCK_SOURCE_SEL_MASK_SFT,
+ ETDM_CLK_SOURCE_APLL <<
+ OUT_REG_CLOCK_SOURCE_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON4,
+ OUT_REG_RELATCH_EN_SEL_MASK_SFT,
+ get_etdm_inconn_rate(rate) <<
+ OUT_REG_RELATCH_EN_SEL_SFT);
+ /* 5: TDM Mode */
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON0,
+ OUT_REG_FMT_MASK_SFT,
+ 0x0 << OUT_REG_FMT_SFT);
+
+ /* APLL */
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON0,
+ OUT_REG_RELATCH_DOMAIN_SEL_MASK_SFT,
+ ETDM_RELATCH_SEL_APLL
+ << OUT_REG_RELATCH_DOMAIN_SEL_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON0,
+ OUT_REG_BIT_LENGTH_MASK_SFT,
+ get_etdm_lrck_width(format) <<
+ OUT_REG_BIT_LENGTH_SFT);
+ regmap_update_bits(afe->regmap, ETDM_OUT4_CON0,
+ OUT_REG_WORD_LENGTH_MASK_SFT,
+ get_etdm_wlen(format) <<
+ OUT_REG_WORD_LENGTH_SFT);
+ break;
+ default:
+ dev_err(afe->dev, "%s(), id %d not support\n",
+ __func__, i2s_id);
+ return -EINVAL;
+ }
+
+ /* set share i2s */
+ if (i2s_priv->share_i2s_id >= 0) {
+ ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+
+ return mtk_dai_i2s_config(afe, params, dai->id);
+}
+
+static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ struct mtk_afe_i2s_priv *i2s_priv;
+ int apll;
+ int apll_rate;
+
+ if (dai->id >= MT8189_DAI_NUM || dai->id < 0 ||
+ dir != SND_SOC_CLOCK_OUT)
+ return -EINVAL;
+
+ i2s_priv = afe_priv->dai_priv[dai->id];
+ if (!i2s_priv)
+ return -EINVAL;
+
+ dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);
+
+ apll = mt8189_get_apll_by_rate(afe, freq);
+ apll_rate = mt8189_get_apll_rate(afe, apll);
+
+ if (freq > apll_rate || apll_rate % freq) {
+ dev_err(afe->dev, "%s(), freq %d, apll_rate %d\n",
+ __func__, freq, apll_rate);
+ return -EINVAL;
+ }
+
+ i2s_priv->mclk_rate = freq;
+ i2s_priv->mclk_apll = apll;
+
+ if (i2s_priv->share_i2s_id > 0) {
+ struct mtk_afe_i2s_priv *share_i2s_priv;
+
+ share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
+ if (!share_i2s_priv)
+ return -EINVAL;
+
+ share_i2s_priv->mclk_rate = i2s_priv->mclk_rate;
+ share_i2s_priv->mclk_apll = i2s_priv->mclk_apll;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops mtk_dai_i2s_ops = {
+ .hw_params = mtk_dai_i2s_hw_params,
+ .set_sysclk = mtk_dai_i2s_set_sysclk,
+};
+
+/* dai driver */
+#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_192000)
+#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\
+ SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE |\
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+#define MT8189_I2S_DAI(_name, _id, max_ch, dir) \
+{ \
+ .name = #_name, \
+ .id = _id, \
+ .dir = { \
+ .stream_name = #_name, \
+ .channels_min = 1, \
+ .channels_max = max_ch, \
+ .rates = MTK_ETDM_RATES, \
+ .formats = MTK_ETDM_FORMATS, \
+ }, \
+ .ops = &mtk_dai_i2s_ops, \
+}
+
+static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
+ /* capture */
+ MT8189_I2S_DAI(I2SIN0, MT8189_DAI_I2S_IN0, 2, capture),
+ MT8189_I2S_DAI(I2SIN1, MT8189_DAI_I2S_IN1, 2, capture),
+ /* playback */
+ MT8189_I2S_DAI(I2SOUT0, MT8189_DAI_I2S_OUT0, 2, playback),
+ MT8189_I2S_DAI(I2SOUT1, MT8189_DAI_I2S_OUT1, 2, playback),
+ MT8189_I2S_DAI(I2SOUT4, MT8189_DAI_I2S_OUT4, 8, playback),
+};
+
+static const struct mtk_afe_i2s_priv mt8189_i2s_priv[DAI_I2S_NUM] = {
+ [DAI_I2SIN0] = {
+ .id = MT8189_DAI_I2S_IN0,
+ .mclk_id = MT8189_I2SIN0_MCK,
+ .share_property_name = "i2sin0-share",
+ .share_i2s_id = MT8189_DAI_I2S_OUT0,
+ },
+ [DAI_I2SIN1] = {
+ .id = MT8189_DAI_I2S_IN1,
+ .mclk_id = MT8189_I2SIN1_MCK,
+ .share_property_name = "i2sin1-share",
+ .share_i2s_id = MT8189_DAI_I2S_OUT1,
+ },
+ [DAI_I2SOUT0] = {
+ .id = MT8189_DAI_I2S_OUT0,
+ .mclk_id = MT8189_I2SOUT0_MCK,
+ .share_property_name = "i2sout0-share",
+ .share_i2s_id = -1,
+ },
+ [DAI_I2SOUT1] = {
+ .id = MT8189_DAI_I2S_OUT1,
+ .mclk_id = MT8189_I2SOUT1_MCK,
+ .share_property_name = "i2sout1-share",
+ .share_i2s_id = -1,
+ },
+ [DAI_I2SOUT4] = {
+ .id = MT8189_DAI_I2S_OUT4,
+ .mclk_id = MT8189_I2SIN1_MCK,
+ .share_property_name = "i2sout4-share",
+ .share_i2s_id = -1,
+ },
+};
+
+static int mt8189_dai_i2s_get_share(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ const struct device_node *of_node = afe->dev->of_node;
+
+ for (int i = 0; i < DAI_I2S_NUM; i++) {
+ const char *of_str;
+ struct mtk_afe_i2s_priv *i2s_priv =
+ afe_priv->dai_priv[mt8189_i2s_priv[i].id];
+ const char *property_name =
+ mt8189_i2s_priv[i].share_property_name;
+
+ if (of_property_read_string(of_node, property_name, &of_str))
+ continue;
+
+ i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str);
+ }
+
+ return 0;
+}
+
+static int init_i2s_priv_data(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ struct mtk_afe_i2s_priv *i2s_priv;
+
+ for (int i = 0; i < DAI_I2S_NUM; i++) {
+ int id = mt8189_i2s_priv[i].id;
+ size_t size = sizeof(struct mtk_afe_i2s_priv);
+
+ if (id >= MT8189_DAI_NUM || id < 0)
+ return -EINVAL;
+
+ i2s_priv = devm_kzalloc(afe->dev, size, GFP_KERNEL);
+ if (!i2s_priv)
+ return -ENOMEM;
+
+ memcpy(i2s_priv, &mt8189_i2s_priv[i], size);
+
+ afe_priv->dai_priv[id] = i2s_priv;
+ }
+
+ return 0;
+}
+
+int mt8189_dai_i2s_register(struct mtk_base_afe *afe)
+{
+ struct mtk_base_afe_dai *dai;
+ int ret;
+
+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+ if (!dai)
+ return -ENOMEM;
+
+ dai->dai_drivers = mtk_dai_i2s_driver;
+ dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
+
+ dai->controls = mtk_dai_i2s_controls;
+ dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls);
+ dai->dapm_widgets = mtk_dai_i2s_widgets;
+ dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
+ dai->dapm_routes = mtk_dai_i2s_routes;
+ dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
+
+ /* set all dai i2s private data */
+ ret = init_i2s_priv_data(afe);
+ if (ret)
+ return ret;
+
+ /* parse share i2s */
+ ret = mt8189_dai_i2s_get_share(afe);
+ if (ret)
+ return ret;
+
+ list_add(&dai->list, &afe->sub_dais);
+
+ return 0;
+}
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 05/10] ASoC: mediatek: mt8189: support TDM in platform driver
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
` (3 preceding siblings ...)
2025-10-31 7:31 ` [PATCH v3 04/10] ASoC: mediatek: mt8189: support I2S " Cyril Chao
@ 2025-10-31 7:31 ` Cyril Chao
2025-10-31 7:32 ` [PATCH v3 06/10] ASoC: mediatek: mt8189: support PCM " Cyril Chao
` (5 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:31 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add mt8189 TDM DAI driver support.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
sound/soc/mediatek/mt8189/mt8189-dai-tdm.c | 672 +++++++++++++++++++++
1 file changed, 672 insertions(+)
create mode 100644 sound/soc/mediatek/mt8189/mt8189-dai-tdm.c
diff --git a/sound/soc/mediatek/mt8189/mt8189-dai-tdm.c b/sound/soc/mediatek/mt8189/mt8189-dai-tdm.c
new file mode 100644
index 000000000000..5d68a55ccc45
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-dai-tdm.c
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek ALSA SoC Audio DAI TDM Control
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#include <linux/regmap.h>
+
+#include <sound/pcm_params.h>
+
+#include "mt8189-afe-clk.h"
+#include "mt8189-afe-common.h"
+#include "mt8189-interconnection.h"
+
+#define DPTX_CH_EN_MASK_2CH (0x3)
+#define DPTX_CH_EN_MASK_4CH (0xf)
+#define DPTX_CH_EN_MASK_6CH (0x3f)
+#define DPTX_CH_EN_MASK_8CH (0xff)
+
+enum {
+ SUPPLY_SEQ_APLL,
+ SUPPLY_SEQ_TDM_MCK_EN,
+ SUPPLY_SEQ_TDM_BCK_EN,
+ SUPPLY_SEQ_TDM_DPTX_MCK_EN,
+ SUPPLY_SEQ_TDM_DPTX_BCK_EN,
+ SUPPLY_SEQ_TDM_CG_EN,
+};
+
+enum {
+ TDM_WLEN_8_BIT,
+ TDM_WLEN_16_BIT,
+ TDM_WLEN_24_BIT,
+ TDM_WLEN_32_BIT,
+};
+
+enum {
+ TDM_CHANNEL_BCK_16,
+ TDM_CHANNEL_BCK_24,
+ TDM_CHANNEL_BCK_32
+};
+
+enum {
+ TDM_CHANNEL_NUM_2,
+ TDM_CHANNEL_NUM_4,
+ TDM_CHANNEL_NUM_8
+};
+
+enum {
+ TDM_CH_START_O30_O31,
+ TDM_CH_START_O32_O33,
+ TDM_CH_START_O34_O35,
+ TDM_CH_START_O36_O37,
+ TDM_CH_ZERO,
+};
+
+enum {
+ DPTX_CHANNEL_2,
+ DPTX_CHANNEL_8,
+};
+
+enum {
+ DPTX_WLEN_24_BIT,
+ DPTX_WLEN_16_BIT,
+};
+
+struct mtk_afe_tdm_priv {
+ int bck_id;
+ int bck_rate;
+
+ int mclk_id;
+ int mclk_multiple; /* according to sample rate */
+ int mclk_rate;
+ int mclk_apll;
+};
+
+static unsigned int get_tdm_wlen(snd_pcm_format_t format)
+{
+ return snd_pcm_format_physical_width(format) <= 16 ?
+ TDM_WLEN_16_BIT : TDM_WLEN_32_BIT;
+}
+
+static unsigned int get_tdm_channel_bck(snd_pcm_format_t format)
+{
+ return snd_pcm_format_physical_width(format) <= 16 ?
+ TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32;
+}
+
+static unsigned int get_tdm_lrck_width(snd_pcm_format_t format)
+{
+ return snd_pcm_format_physical_width(format) - 1;
+}
+
+static unsigned int get_tdm_ch(unsigned int ch)
+{
+ switch (ch) {
+ case 1:
+ case 2:
+ return TDM_CHANNEL_NUM_2;
+ case 3:
+ case 4:
+ return TDM_CHANNEL_NUM_4;
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ default:
+ return TDM_CHANNEL_NUM_8;
+ }
+}
+
+static unsigned int get_dptx_ch_enable_mask(unsigned int ch)
+{
+ switch (ch) {
+ case 1:
+ case 2:
+ return DPTX_CH_EN_MASK_2CH;
+ case 3:
+ case 4:
+ return DPTX_CH_EN_MASK_4CH;
+ case 5:
+ case 6:
+ return DPTX_CH_EN_MASK_6CH;
+ case 7:
+ case 8:
+ return DPTX_CH_EN_MASK_8CH;
+ default:
+ return DPTX_CH_EN_MASK_2CH;
+ }
+}
+
+static unsigned int get_dptx_ch(unsigned int ch)
+{
+ if (ch == 2)
+ return DPTX_CHANNEL_2;
+
+ return DPTX_CHANNEL_8;
+}
+
+static unsigned int get_dptx_wlen(snd_pcm_format_t format)
+{
+ return snd_pcm_format_physical_width(format) <= 16 ?
+ DPTX_WLEN_16_BIT : DPTX_WLEN_24_BIT;
+}
+
+/* interconnection */
+enum {
+ HDMI_CONN_CH0,
+ HDMI_CONN_CH1,
+ HDMI_CONN_CH2,
+ HDMI_CONN_CH3,
+ HDMI_CONN_CH4,
+ HDMI_CONN_CH5,
+ HDMI_CONN_CH6,
+ HDMI_CONN_CH7,
+};
+
+static const char *const hdmi_conn_mux_map[] = {
+ "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7",
+};
+
+static int hdmi_conn_mux_map_value[] = {
+ HDMI_CONN_CH0, HDMI_CONN_CH1, HDMI_CONN_CH2, HDMI_CONN_CH3,
+ HDMI_CONN_CH4, HDMI_CONN_CH5, HDMI_CONN_CH6, HDMI_CONN_CH7,
+};
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
+ AFE_HDMI_CONN0,
+ HDMI_O_0_SFT,
+ HDMI_O_0_MASK,
+ hdmi_conn_mux_map,
+ hdmi_conn_mux_map_value);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
+ AFE_HDMI_CONN0,
+ HDMI_O_1_SFT,
+ HDMI_O_1_MASK,
+ hdmi_conn_mux_map,
+ hdmi_conn_mux_map_value);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
+ AFE_HDMI_CONN0,
+ HDMI_O_2_SFT,
+ HDMI_O_2_MASK,
+ hdmi_conn_mux_map,
+ hdmi_conn_mux_map_value);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
+ AFE_HDMI_CONN0,
+ HDMI_O_3_SFT,
+ HDMI_O_3_MASK,
+ hdmi_conn_mux_map,
+ hdmi_conn_mux_map_value);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
+ AFE_HDMI_CONN0,
+ HDMI_O_4_SFT,
+ HDMI_O_4_MASK,
+ hdmi_conn_mux_map,
+ hdmi_conn_mux_map_value);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
+ AFE_HDMI_CONN0,
+ HDMI_O_5_SFT,
+ HDMI_O_5_MASK,
+ hdmi_conn_mux_map,
+ hdmi_conn_mux_map_value);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
+ AFE_HDMI_CONN0,
+ HDMI_O_6_SFT,
+ HDMI_O_6_MASK,
+ hdmi_conn_mux_map,
+ hdmi_conn_mux_map_value);
+
+static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
+ AFE_HDMI_CONN0,
+ HDMI_O_7_SFT,
+ HDMI_O_7_MASK,
+ hdmi_conn_mux_map,
+ hdmi_conn_mux_map_value);
+
+static const struct snd_kcontrol_new mtk_dai_tdm_controls[] = {
+ SOC_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum),
+ SOC_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum),
+ SOC_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum),
+ SOC_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum),
+ SOC_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum),
+ SOC_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum),
+ SOC_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum),
+ SOC_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum),
+};
+
+static const char *const tdm_out_demux_texts[] = {
+ "NONE", "TDMOUT", "DPTXOUT",
+};
+
+static SOC_ENUM_SINGLE_DECL(tdm_out_demux_enum,
+ SND_SOC_NOPM,
+ 0,
+ tdm_out_demux_texts);
+
+static const struct snd_kcontrol_new tdm_out_demux_control =
+ SOC_DAPM_ENUM("TDM Playback Route", tdm_out_demux_enum);
+
+static int get_tdm_id_by_name(const char *name)
+{
+ if (strstr(name, "DPTX"))
+ return MT8189_DAI_TDM_DPTX;
+
+ return MT8189_DAI_TDM;
+}
+
+static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int dai_id = get_tdm_id_by_name(w->name);
+ struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
+
+ dev_dbg(cmpnt->dev, "name %s, event 0x%x, dai_id %d, bck: %d\n",
+ w->name, event, dai_id, tdm_priv->bck_rate);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ mt8189_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ mt8189_mck_disable(afe, tdm_priv->bck_id);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int dai_id = get_tdm_id_by_name(w->name);
+ struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
+
+ dev_dbg(cmpnt->dev, "name %s, event 0x%x, dai_id %d, mclk %d\n",
+ w->name, event, dai_id, tdm_priv->mclk_rate);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ mt8189_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ tdm_priv->mclk_rate = 0;
+ mt8189_mck_disable(afe, tdm_priv->mclk_id);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {
+ SND_SOC_DAPM_DEMUX("TDM Playback Route", SND_SOC_NOPM, 0, 0,
+ &tdm_out_demux_control),
+
+ SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_tdm_bck_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_tdm_mck_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY_S("TDM_DPTX_BCK", SUPPLY_SEQ_TDM_DPTX_BCK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_tdm_bck_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY_S("TDM_DPTX_MCK", SUPPLY_SEQ_TDM_DPTX_MCK_EN,
+ SND_SOC_NOPM, 0, 0,
+ mtk_tdm_mck_en_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY_S("TDM_CG", SUPPLY_SEQ_TDM_CG_EN,
+ AUDIO_TOP_CON2, PDN_TDM_OUT_SFT, 1,
+ NULL, 0),
+};
+
+static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,
+ struct snd_soc_dapm_widget *sink)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(sink->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int dai_id = get_tdm_id_by_name(sink->name);
+ struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
+ int cur_apll;
+
+ /* which apll */
+ cur_apll = mt8189_get_apll_by_name(afe, source->name);
+
+ return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;
+}
+
+static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {
+ {"TDM Playback Route", NULL, "HDMI"},
+
+ {"TDM", "TDMOUT", "TDM Playback Route"},
+ {"TDM", NULL, "TDM_BCK"},
+ {"TDM", NULL, "TDM_CG"},
+
+ {"TDM_DPTX", "DPTXOUT", "TDM Playback Route"},
+ {"TDM_DPTX", NULL, "TDM_DPTX_BCK"},
+ {"TDM_DPTX", NULL, "TDM_CG"},
+
+ {"TDM_BCK", NULL, "TDM_MCK"},
+ {"TDM_DPTX_BCK", NULL, "TDM_DPTX_MCK"},
+ {"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
+ {"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
+ {"TDM_DPTX_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
+ {"TDM_DPTX_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
+};
+
+/* dai ops */
+static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,
+ struct mtk_afe_tdm_priv *tdm_priv,
+ int freq)
+{
+ int apll;
+ int apll_rate;
+
+ apll = mt8189_get_apll_by_rate(afe, freq);
+ apll_rate = mt8189_get_apll_rate(afe, apll);
+
+ if (freq > apll_rate)
+ return -EINVAL;
+
+ if (apll_rate % freq != 0)
+ return -EINVAL;
+
+ tdm_priv->mclk_rate = freq;
+ tdm_priv->mclk_apll = apll;
+
+ return 0;
+}
+
+static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int tdm_id = dai->id;
+ struct mtk_afe_tdm_priv *tdm_priv;
+ unsigned int rate = params_rate(params);
+ unsigned int channels = params_channels(params);
+ snd_pcm_format_t format = params_format(params);
+ unsigned int tdm_con;
+
+ if (tdm_id >= MT8189_DAI_NUM || tdm_id < 0)
+ return -EINVAL;
+
+ tdm_priv = afe_priv->dai_priv[tdm_id];
+
+ /* calculate mclk_rate, if not set explicitly */
+ if (!tdm_priv->mclk_rate) {
+ tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;
+ mtk_dai_tdm_cal_mclk(afe,
+ tdm_priv,
+ tdm_priv->mclk_rate);
+ }
+
+ /* calculate bck */
+ tdm_priv->bck_rate = rate *
+ channels *
+ snd_pcm_format_physical_width(format);
+
+ if (tdm_priv->bck_rate > tdm_priv->mclk_rate)
+ return -EINVAL;
+
+ if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0)
+ return -EINVAL;
+
+ dev_dbg(afe->dev, "id %d, rate %d, ch %d, fmt %d, mclk %d, bck %d\n",
+ tdm_id, rate, channels, format,
+ tdm_priv->mclk_rate, tdm_priv->bck_rate);
+
+ /* set tdm */
+ tdm_con = 1 << LEFT_ALIGN_SFT;
+ tdm_con |= get_tdm_wlen(format) << WLEN_SFT;
+ tdm_con |= get_tdm_ch(channels) << CHANNEL_NUM_SFT;
+ tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT;
+ tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT;
+ regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con);
+
+ /* set dptx */
+ if (tdm_id == MT8189_DAI_TDM_DPTX) {
+ regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+ DPTX_CHANNEL_ENABLE_MASK_SFT,
+ get_dptx_ch_enable_mask(channels) <<
+ DPTX_CHANNEL_ENABLE_SFT);
+ regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+ DPTX_CHANNEL_NUMBER_MASK_SFT,
+ get_dptx_ch(channels) <<
+ DPTX_CHANNEL_NUMBER_SFT);
+ regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+ DPTX_16BIT_MASK_SFT,
+ get_dptx_wlen(format) << DPTX_16BIT_SFT);
+ }
+ switch (channels) {
+ case 1:
+ case 2:
+ tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
+ tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
+ tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
+ tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
+ break;
+ case 3:
+ case 4:
+ tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
+ tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
+ tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
+ tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
+ break;
+ case 5:
+ case 6:
+ tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
+ tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
+ tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
+ tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
+ break;
+ case 7:
+ case 8:
+ tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
+ tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
+ tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
+ tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT;
+ break;
+ default:
+ tdm_con = 0;
+ }
+ regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con);
+ regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
+ HDMI_CH_NUM_MASK_SFT,
+ channels << HDMI_CH_NUM_SFT);
+
+ return 0;
+}
+
+static int mtk_dai_tdm_trigger(struct snd_pcm_substream *substream,
+ int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ int tdm_id = dai->id;
+
+ dev_dbg(afe->dev, "%s(), cmd %d, tdm_id %d\n", __func__, cmd, tdm_id);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ /* enable Out control */
+ regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
+ HDMI_OUT_ON_MASK_SFT,
+ 0x1 << HDMI_OUT_ON_SFT);
+
+ /* enable dptx */
+ if (tdm_id == MT8189_DAI_TDM_DPTX) {
+ regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+ DPTX_ON_MASK_SFT, 0x1 <<
+ DPTX_ON_SFT);
+ }
+
+ /* enable tdm */
+ regmap_update_bits(afe->regmap, AFE_TDM_CON1,
+ TDM_EN_MASK_SFT, 0x1 << TDM_EN_SFT);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ /* disable tdm */
+ regmap_update_bits(afe->regmap, AFE_TDM_CON1,
+ TDM_EN_MASK_SFT, 0);
+
+ /* disable dptx */
+ if (tdm_id == MT8189_DAI_TDM_DPTX) {
+ regmap_update_bits(afe->regmap, AFE_DPTX_CON,
+ DPTX_ON_MASK_SFT, 0);
+ }
+
+ /* disable Out control */
+ regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
+ HDMI_OUT_ON_MASK_SFT, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ struct mtk_afe_tdm_priv *tdm_priv;
+
+ if (dai->id >= MT8189_DAI_NUM || dai->id < 0)
+ return -EINVAL;
+
+ tdm_priv = afe_priv->dai_priv[dai->id];
+
+ if (!tdm_priv)
+ return -EINVAL;
+
+ if (dir != SND_SOC_CLOCK_OUT)
+ return -EINVAL;
+
+ dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);
+
+ return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);
+}
+
+static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {
+ .hw_params = mtk_dai_tdm_hw_params,
+ .trigger = mtk_dai_tdm_trigger,
+ .set_sysclk = mtk_dai_tdm_set_sysclk,
+};
+
+/* dai driver */
+#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
+ SNDRV_PCM_RATE_88200 |\
+ SNDRV_PCM_RATE_96000 |\
+ SNDRV_PCM_RATE_176400 |\
+ SNDRV_PCM_RATE_192000)
+
+#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE |\
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {
+ {
+ .name = "TDM",
+ .id = MT8189_DAI_TDM,
+ .playback = {
+ .stream_name = "TDM",
+ .channels_min = 2,
+ .channels_max = 8,
+ .rates = MTK_TDM_RATES,
+ .formats = MTK_TDM_FORMATS,
+ },
+ .ops = &mtk_dai_tdm_ops,
+ },
+ {
+ .name = "TDM_DPTX",
+ .id = MT8189_DAI_TDM_DPTX,
+ .playback = {
+ .stream_name = "TDM_DPTX",
+ .channels_min = 2,
+ .channels_max = 8,
+ .rates = MTK_TDM_RATES,
+ .formats = MTK_TDM_FORMATS,
+ },
+ .ops = &mtk_dai_tdm_ops,
+ },
+};
+
+static struct mtk_afe_tdm_priv *init_tdm_priv_data(struct mtk_base_afe *afe,
+ int id)
+{
+ struct mtk_afe_tdm_priv *tdm_priv;
+
+ tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),
+ GFP_KERNEL);
+ if (!tdm_priv)
+ return NULL;
+
+ if (id == MT8189_DAI_TDM_DPTX)
+ tdm_priv->mclk_multiple = 256;
+ else
+ tdm_priv->mclk_multiple = 128;
+
+ tdm_priv->bck_id = MT8189_TDMOUT_BCK;
+ tdm_priv->mclk_id = MT8189_TDMOUT_MCK;
+
+ return tdm_priv;
+}
+
+int mt8189_dai_tdm_register(struct mtk_base_afe *afe)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ struct mtk_afe_tdm_priv *tdm_priv, *tdm_dptx_priv;
+ struct mtk_base_afe_dai *dai;
+
+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+ if (!dai)
+ return -ENOMEM;
+
+ dai->dai_drivers = mtk_dai_tdm_driver;
+ dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);
+ dai->controls = mtk_dai_tdm_controls;
+ dai->num_controls = ARRAY_SIZE(mtk_dai_tdm_controls);
+ dai->dapm_widgets = mtk_dai_tdm_widgets;
+ dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);
+ dai->dapm_routes = mtk_dai_tdm_routes;
+ dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);
+
+ tdm_priv = init_tdm_priv_data(afe, MT8189_DAI_TDM);
+ if (!tdm_priv)
+ return -ENOMEM;
+
+ tdm_dptx_priv = init_tdm_priv_data(afe, MT8189_DAI_TDM_DPTX);
+ if (!tdm_dptx_priv)
+ return -ENOMEM;
+
+ list_add(&dai->list, &afe->sub_dais);
+
+ afe_priv->dai_priv[MT8189_DAI_TDM] = tdm_priv;
+ afe_priv->dai_priv[MT8189_DAI_TDM_DPTX] = tdm_dptx_priv;
+
+ return 0;
+}
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 06/10] ASoC: mediatek: mt8189: support PCM in platform driver
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
` (4 preceding siblings ...)
2025-10-31 7:31 ` [PATCH v3 05/10] ASoC: mediatek: mt8189: support TDM " Cyril Chao
@ 2025-10-31 7:32 ` Cyril Chao
2025-10-31 7:32 ` [PATCH v3 07/10] ASoC: dt-bindings: mediatek,mt8189-afe-pcm: add audio afe document Cyril Chao
` (4 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:32 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add mt8189 PCM DAI driver support.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
sound/soc/mediatek/mt8189/mt8189-dai-pcm.c | 332 +++++++++++++++++++++
1 file changed, 332 insertions(+)
create mode 100644 sound/soc/mediatek/mt8189/mt8189-dai-pcm.c
diff --git a/sound/soc/mediatek/mt8189/mt8189-dai-pcm.c b/sound/soc/mediatek/mt8189/mt8189-dai-pcm.c
new file mode 100644
index 000000000000..21317c0413e5
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-dai-pcm.c
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek ALSA SoC Audio DAI I2S Control
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#include <linux/regmap.h>
+
+#include <sound/pcm_params.h>
+
+#include "mt8189-afe-common.h"
+#include "mt8189-interconnection.h"
+#include "mt8189-afe-clk.h"
+
+enum AUD_TX_LCH_RPT {
+ AUD_TX_LCH_RPT_NO_REPEAT,
+ AUD_TX_LCH_RPT_REPEAT
+};
+
+enum AUD_VBT_16K_MODE {
+ AUD_VBT_16K_MODE_DISABLE,
+ AUD_VBT_16K_MODE_ENABLE
+};
+
+enum AUD_EXT_MODEM {
+ AUD_EXT_MODEM_SELECT_INTERNAL,
+ AUD_EXT_MODEM_SELECT_EXTERNAL
+};
+
+enum AUD_PCM_SYNC_TYPE {
+ /* bck sync length = 1 */
+ AUD_PCM_ONE_BCK_CYCLE_SYNC,
+ /* bck sync length = PCM_INTF_CON1[9:13] */
+ AUD_PCM_EXTENDED_BCK_CYCLE_SYNC
+};
+
+enum AUD_BT_MODE {
+ AUD_BT_MODE_DUAL_MIC_ON_TX,
+ AUD_BT_MODE_SINGLE_MIC_ON_TX
+};
+
+enum AUD_PCM_AFIFO_SRC {
+ /* slave mode & external modem uses different crystal */
+ AUD_PCM_AFIFO_ASRC,
+ /* slave mode & external modem uses the same crystal */
+ AUD_PCM_AFIFO_AFIFO
+};
+
+enum AUD_PCM_CLOCK_SOURCE {
+ AUD_PCM_CLOCK_MASTER_MODE,
+ AUD_PCM_CLOCK_SLAVE_MODE
+};
+
+enum AUD_PCM_WLEN {
+ AUD_PCM_WLEN_PCM_32_BCK_CYCLES,
+ AUD_PCM_WLEN_PCM_64_BCK_CYCLES
+};
+
+enum AUD_PCM_MODE {
+ AUD_PCM_MODE_PCM_MODE_8K,
+ AUD_PCM_MODE_PCM_MODE_16K,
+ AUD_PCM_MODE_PCM_MODE_32K,
+ AUD_PCM_MODE_PCM_MODE_48K
+};
+
+enum AUD_PCM_FMT {
+ AUD_PCM_FMT_I2S,
+ AUD_PCM_FMT_EIAJ,
+ AUD_PCM_FMT_PCM_MODE_A,
+ AUD_PCM_FMT_PCM_MODE_B
+};
+
+enum AUD_BCLK_OUT_INV {
+ AUD_BCLK_OUT_INV_NO_INVERSE,
+ AUD_BCLK_OUT_INV_INVERSE
+};
+
+enum AUD_PCM_EN {
+ AUD_PCM_EN_DISABLE,
+ AUD_PCM_EN_ENABLE
+};
+
+enum AUD_PCM1_1X_EN_DOMAIN {
+ HOPPING_26M,
+ APLL,
+ SLAVE = 6
+};
+
+enum AUD_PCM1_1X_EN_SLAVE_MODE {
+ PCM0_SLAVE_1X_EN,
+ PCM1_SLAVE_1X_EN
+};
+
+enum {
+ PCM_8K,
+ PCM_16K = 4,
+ PCM_32K = 8,
+ PCM_48K = 10
+};
+
+static unsigned int pcm_1x_rate_transform(struct device *dev,
+ unsigned int rate)
+{
+ switch (rate) {
+ case 8000:
+ return PCM_8K;
+ case 16000:
+ return PCM_16K;
+ case 32000:
+ return PCM_32K;
+ case 48000:
+ return PCM_48K;
+ default:
+ dev_warn(dev, "rate %u invalid, use %d!!!\n",
+ rate, PCM_48K);
+ return PCM_48K;
+ }
+}
+
+static unsigned int pcm_rate_transform(struct device *dev,
+ unsigned int rate)
+{
+ switch (rate) {
+ case 8000:
+ return MTK_AFE_PCM_RATE_8K;
+ case 16000:
+ return MTK_AFE_PCM_RATE_16K;
+ case 32000:
+ return MTK_AFE_PCM_RATE_32K;
+ case 48000:
+ return MTK_AFE_PCM_RATE_48K;
+ default:
+ dev_warn(dev, "rate %u invalid, use %d\n",
+ rate, MTK_AFE_PCM_RATE_48K);
+ return MTK_AFE_PCM_RATE_48K;
+ }
+}
+
+/* dai component */
+static const struct snd_kcontrol_new mtk_pcm_0_playback_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN096_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN096_1,
+ I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN096_1,
+ I_DL_24CH_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_pcm_0_playback_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN097_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN097_1,
+ I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN097_1,
+ I_DL_24CH_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new mtk_pcm_0_playback_ch4_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN099_4,
+ I_I2SIN1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN099_4,
+ I_I2SIN1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN099_1,
+ I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN099_1,
+ I_DL_24CH_CH1, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
+ /* inter-connections */
+ SND_SOC_DAPM_MIXER("PCM_0_PB_CH1", SND_SOC_NOPM, 0, 0,
+ mtk_pcm_0_playback_ch1_mix,
+ ARRAY_SIZE(mtk_pcm_0_playback_ch1_mix)),
+ SND_SOC_DAPM_MIXER("PCM_0_PB_CH2", SND_SOC_NOPM, 0, 0,
+ mtk_pcm_0_playback_ch2_mix,
+ ARRAY_SIZE(mtk_pcm_0_playback_ch2_mix)),
+ SND_SOC_DAPM_MIXER("PCM_0_PB_CH4", SND_SOC_NOPM, 0, 0,
+ mtk_pcm_0_playback_ch4_mix,
+ ARRAY_SIZE(mtk_pcm_0_playback_ch4_mix)),
+
+ SND_SOC_DAPM_SUPPLY("PCM_0_EN",
+ AFE_PCM0_INTF_CON0, PCM0_EN_SFT, 0,
+ NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY("PCM0_CG", AUDIO_TOP_CON0, PDN_PCM0_SFT, 1,
+ NULL, 0),
+
+ SND_SOC_DAPM_INPUT("AFE_PCM_INPUT"),
+ SND_SOC_DAPM_OUTPUT("AFE_PCM_OUTPUT"),
+};
+
+static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
+ {"PCM 0 Playback", NULL, "PCM_0_PB_CH1"},
+ {"PCM 0 Playback", NULL, "PCM_0_PB_CH2"},
+ {"PCM 0 Playback", NULL, "PCM_0_PB_CH4"},
+
+ {"PCM 0 Playback", NULL, "PCM_0_EN"},
+ {"PCM 0 Capture", NULL, "PCM_0_EN"},
+ {"PCM 0 Playback", NULL, "PCM0_CG"},
+ {"PCM 0 Capture", NULL, "PCM0_CG"},
+
+ {"AFE_PCM_OUTPUT", NULL, "PCM 0 Playback"},
+ {"PCM 0 Capture", NULL, "AFE_PCM_INPUT"},
+
+ {"PCM_0_PB_CH1", "DL2_CH1", "DL2"},
+ {"PCM_0_PB_CH2", "DL2_CH2", "DL2"},
+ {"PCM_0_PB_CH4", "DL0_CH1", "DL0"},
+
+ {"PCM_0_PB_CH1", "DL_24CH_CH1", "DL_24CH"},
+ {"PCM_0_PB_CH2", "DL_24CH_CH2", "DL_24CH"},
+ {"PCM_0_PB_CH4", "DL_24CH_CH1", "DL_24CH"},
+};
+
+/* dai ops */
+static int mtk_dai_pcm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ unsigned int rate = params_rate(params);
+ unsigned int rate_reg = pcm_rate_transform(afe->dev, rate);
+ unsigned int x_rate_reg = pcm_1x_rate_transform(afe->dev, rate);
+ unsigned int pcm_con0;
+ unsigned int pcm_con1;
+ unsigned int playback_active = 0;
+ unsigned int capture_active = 0;
+ struct snd_soc_dapm_widget *playback_widget =
+ snd_soc_dai_get_widget(dai, SNDRV_PCM_STREAM_PLAYBACK);
+ struct snd_soc_dapm_widget *capture_widget =
+ snd_soc_dai_get_widget(dai, SNDRV_PCM_STREAM_CAPTURE);
+
+ if (playback_widget)
+ playback_active = playback_widget->active;
+ if (capture_widget)
+ capture_active = capture_widget->active;
+ dev_dbg(afe->dev,
+ "id %d, stream %d, rate %d, rate_reg %d, active p %d, c %d\n",
+ dai->id, substream->stream, rate, rate_reg,
+ playback_active, capture_active);
+
+ if (playback_active || capture_active)
+ return 0;
+ switch (dai->id) {
+ case MT8189_DAI_PCM_0:
+ pcm_con0 = AUD_BCLK_OUT_INV_NO_INVERSE << PCM0_BCLK_OUT_INV_SFT;
+ pcm_con0 |= AUD_TX_LCH_RPT_NO_REPEAT << PCM0_TX_LCH_RPT_SFT;
+ pcm_con0 |= AUD_VBT_16K_MODE_DISABLE << PCM0_VBT_16K_MODE_SFT;
+ pcm_con0 |= 0 << PCM0_SYNC_LENGTH_SFT;
+ pcm_con0 |= AUD_PCM_ONE_BCK_CYCLE_SYNC << PCM0_SYNC_TYPE_SFT;
+ pcm_con0 |= AUD_PCM_AFIFO_AFIFO << PCM0_BYP_ASRC_SFT;
+ pcm_con0 |= AUD_PCM_CLOCK_MASTER_MODE << PCM0_SLAVE_SFT;
+ pcm_con0 |= rate_reg << PCM0_MODE_SFT;
+ pcm_con0 |= AUD_PCM_FMT_I2S << PCM0_FMT_SFT;
+
+ pcm_con1 = AUD_EXT_MODEM_SELECT_INTERNAL << PCM0_EXT_MODEM_SFT;
+ pcm_con1 |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM0_BT_MODE_SFT;
+ pcm_con1 |= HOPPING_26M << PCM0_1X_EN_DOMAIN_SFT;
+ pcm_con1 |= x_rate_reg << PCM0_1X_EN_MODE_SFT;
+
+ regmap_update_bits(afe->regmap, AFE_PCM0_INTF_CON0,
+ ~(unsigned int)PCM0_EN_MASK_SFT, pcm_con0);
+ regmap_update_bits(afe->regmap, AFE_PCM0_INTF_CON1,
+ AFE_PCM0_INTF_CON1_MASK_MON_MASK_SFT,
+ pcm_con1);
+ break;
+ default:
+ dev_err(afe->dev, "%s(), id %d not support\n",
+ __func__, dai->id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
+ .hw_params = mtk_dai_pcm_hw_params,
+};
+
+/* dai driver */
+#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000 |\
+ SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 |\
+ SNDRV_PCM_RATE_48000)
+
+#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE |\
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
+ {
+ .name = "PCM 0",
+ .id = MT8189_DAI_PCM_0,
+ .playback = {
+ .stream_name = "PCM 0 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MTK_PCM_RATES,
+ .formats = MTK_PCM_FORMATS,
+ },
+ .capture = {
+ .stream_name = "PCM 0 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MTK_PCM_RATES,
+ .formats = MTK_PCM_FORMATS,
+ },
+ .ops = &mtk_dai_pcm_ops,
+ .symmetric_rate = 1,
+ .symmetric_sample_bits = 1,
+ },
+};
+
+int mt8189_dai_pcm_register(struct mtk_base_afe *afe)
+{
+ struct mtk_base_afe_dai *dai;
+
+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+ if (!dai)
+ return -ENOMEM;
+
+ dai->dai_drivers = mtk_dai_pcm_driver;
+ dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
+ dai->dapm_widgets = mtk_dai_pcm_widgets;
+ dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
+ dai->dapm_routes = mtk_dai_pcm_routes;
+ dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
+
+ list_add(&dai->list, &afe->sub_dais);
+
+ return 0;
+}
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 07/10] ASoC: dt-bindings: mediatek,mt8189-afe-pcm: add audio afe document
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
` (5 preceding siblings ...)
2025-10-31 7:32 ` [PATCH v3 06/10] ASoC: mediatek: mt8189: support PCM " Cyril Chao
@ 2025-10-31 7:32 ` Cyril Chao
2025-10-31 7:32 ` [PATCH v3 08/10] ASoC: mediatek: mt8189: add platform driver Cyril Chao
` (3 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:32 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao, Krzysztof Kozlowski
Add mt8189 audio afe document.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../sound/mediatek,mt8189-afe-pcm.yaml | 178 ++++++++++++++++++
1 file changed, 178 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8189-afe-pcm.yaml
diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8189-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8189-afe-pcm.yaml
new file mode 100644
index 000000000000..9c9f21652af9
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt8189-afe-pcm.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mediatek,mt8189-afe-pcm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Audio Front End PCM controller for MT8189
+
+maintainers:
+ - Darren Ye <darren.ye@mediatek.com>
+ - Cyril Chao <cyril.chao@mediatek.com>
+
+properties:
+ compatible:
+ const: mediatek,mt8189-afe-pcm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ memory-region:
+ maxItems: 1
+
+ mediatek,apmixedsys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: To set up the apll12 tuner
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: mux for audio intbus
+ - description: mux for audio engen1
+ - description: mux for audio engen2
+ - description: mux for audio h
+ - description: audio apll1 clock
+ - description: audio apll2 clock
+ - description: audio apll1 divide4
+ - description: audio apll2 divide4
+ - description: audio apll12 divide for i2sin0
+ - description: audio apll12 divide for i2sin1
+ - description: audio apll12 divide for i2sout0
+ - description: audio apll12 divide for i2sout1
+ - description: audio apll12 divide for fmi2s
+ - description: audio apll12 divide for tdmout mck
+ - description: audio apll12 divide for tdmout bck
+ - description: mux for audio apll1
+ - description: mux for audio apll2
+ - description: mux for i2sin0 mck
+ - description: mux for i2sin1 mck
+ - description: mux for i2sout0 mck
+ - description: mux for i2sout1 mck
+ - description: mux for fmi2s mck
+ - description: mux for tdmout mck
+ - description: 26m clock
+ - description: audio slv clock
+ - description: audio mst clock
+ - description: audio intbus clock
+
+ clock-names:
+ items:
+ - const: top_aud_intbus
+ - const: top_aud_eng1
+ - const: top_aud_eng2
+ - const: top_aud_h
+ - const: apll1
+ - const: apll2
+ - const: apll1_d4
+ - const: apll2_d4
+ - const: apll12_div_i2sin0
+ - const: apll12_div_i2sin1
+ - const: apll12_div_i2sout0
+ - const: apll12_div_i2sout1
+ - const: apll12_div_fmi2s
+ - const: apll12_div_tdmout_m
+ - const: apll12_div_tdmout_b
+ - const: top_apll1
+ - const: top_apll2
+ - const: top_i2sin0
+ - const: top_i2sin1
+ - const: top_i2sout0
+ - const: top_i2sout1
+ - const: top_fmi2s
+ - const: top_dptx
+ - const: clk26m
+ - const: aud_slv_ck_peri
+ - const: aud_mst_ck_peri
+ - const: aud_intbus_ck_peri
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - memory-region
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ afe@11050000 {
+ compatible = "mediatek,mt8189-afe-pcm";
+ reg = <0 0x11050000 0 0x10000>;
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
+ memory-region = <&afe_dma_mem_reserved>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&aud_pins_default>;
+ power-domains = <&scpsys 1>; //MT8189_POWER_DOMAIN_AUDIO
+ clocks = <&topckgen_clk 23>, //CLK_TOP_AUD_INTBUS_SEL
+ <&topckgen_clk 39>, //CLK_TOP_AUD_ENGEN1_SEL
+ <&topckgen_clk 40>, //CLK_TOP_AUD_ENGEN2_SEL
+ <&topckgen_clk 49>, //CLK_TOP_AUDIO_H_SEL
+ <&topckgen_clk 146>, //CLK_TOP_APLL1
+ <&topckgen_clk 151>, //CLK_TOP_APLL2
+ <&topckgen_clk 148>, //CLK_TOP_APLL1_D4
+ <&topckgen_clk 153>, //CLK_TOP_APLL2_D4
+ <&topckgen_clk 93>, //CLK_TOP_APLL12_CK_DIV_I2SIN0
+ <&topckgen_clk 94>, //CLK_TOP_APLL12_CK_DIV_I2SIN1
+ <&topckgen_clk 95>, //CLK_TOP_APLL12_CK_DIV_I2SOUT0
+ <&topckgen_clk 96>, //CLK_TOP_APLL12_CK_DIV_I2SOUT1
+ <&topckgen_clk 97>, //CLK_TOP_APLL12_CK_DIV_FMI2S
+ <&topckgen_clk 98>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M
+ <&topckgen_clk 99>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_B
+ <&topckgen_clk 44>, //CLK_TOP_AUD_1_SEL
+ <&topckgen_clk 45>, //CLK_TOP_AUD_2_SEL
+ <&topckgen_clk 78>, //CLK_TOP_APLL_I2SIN0_MCK_SEL
+ <&topckgen_clk 79>, //CLK_TOP_APLL_I2SIN1_MCK_SEL
+ <&topckgen_clk 84>, //CLK_TOP_APLL_I2SOUT0_MCK_SEL
+ <&topckgen_clk 85>, //CLK_TOP_APLL_I2SOUT1_MCK_SEL
+ <&topckgen_clk 90>, //CLK_TOP_APLL_FMI2S_MCK_SEL
+ <&topckgen_clk 91>, //CLK_TOP_APLL_TDMOUT_MCK_SEL
+ <&topckgen_clk 191>, //CLK_TOP_TCK_26M_MX9
+ <&pericfg_ao_clk 77>, //CLK_PERAO_AUDIO0
+ <&pericfg_ao_clk 78>, //CLK_PERAO_AUDIO1
+ <&pericfg_ao_clk 79>; //CLK_PERAO_AUDIO2
+ clock-names = "top_aud_intbus",
+ "top_aud_eng1",
+ "top_aud_eng2",
+ "top_aud_h",
+ "apll1",
+ "apll2",
+ "apll1_d4",
+ "apll2_d4",
+ "apll12_div_i2sin0",
+ "apll12_div_i2sin1",
+ "apll12_div_i2sout0",
+ "apll12_div_i2sout1",
+ "apll12_div_fmi2s",
+ "apll12_div_tdmout_m",
+ "apll12_div_tdmout_b",
+ "top_apll1",
+ "top_apll2",
+ "top_i2sin0",
+ "top_i2sin1",
+ "top_i2sout0",
+ "top_i2sout1",
+ "top_fmi2s",
+ "top_dptx",
+ "clk26m",
+ "aud_slv_ck_peri",
+ "aud_mst_ck_peri",
+ "aud_intbus_ck_peri";
+ };
+ };
+
+...
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 08/10] ASoC: mediatek: mt8189: add platform driver
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
` (6 preceding siblings ...)
2025-10-31 7:32 ` [PATCH v3 07/10] ASoC: dt-bindings: mediatek,mt8189-afe-pcm: add audio afe document Cyril Chao
@ 2025-10-31 7:32 ` Cyril Chao
2025-10-31 7:32 ` [PATCH v3 09/10] ASoC: dt-bindings: mediatek,mt8189-nau8825: add mt8189-nau8825 document Cyril Chao
` (2 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:32 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add mt8189 platform driver.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
sound/soc/mediatek/Kconfig | 10 +
sound/soc/mediatek/Makefile | 1 +
sound/soc/mediatek/mt8189/Makefile | 15 +
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c | 2617 ++++++++++++++++++++
4 files changed, 2643 insertions(+)
create mode 100644 sound/soc/mediatek/mt8189/Makefile
create mode 100644 sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index 10ca8bccabdd..b28648e0d913 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -246,6 +246,16 @@ config SND_SOC_MT8188_MT6359
Select Y if you have such device.
If unsure select "N".
+config SND_SOC_MT8189
+ tristate "ASoC support for Mediatek MT8189 chip"
+ depends on ARCH_MEDIATEK
+ select SND_SOC_MEDIATEK
+ help
+ This adds ASoC driver for Mediatek MT8189 boards
+ that can be used with other codecs.
+ Select Y if you have such device.
+ If unsure select "N".
+
config SND_SOC_MT8192
tristate "ASoC support for Mediatek MT8192 chip"
depends on ARCH_MEDIATEK
diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile
index 4b55434f2168..7cd67bce92e9 100644
--- a/sound/soc/mediatek/Makefile
+++ b/sound/soc/mediatek/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_SND_SOC_MT8188) += mt8188/
obj-$(CONFIG_SND_SOC_MT8192) += mt8192/
obj-$(CONFIG_SND_SOC_MT8195) += mt8195/
obj-$(CONFIG_SND_SOC_MT8365) += mt8365/
+obj-$(CONFIG_SND_SOC_MT8189) += mt8189/
diff --git a/sound/soc/mediatek/mt8189/Makefile b/sound/soc/mediatek/mt8189/Makefile
new file mode 100644
index 000000000000..795b1869bd27
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0
+
+# common include path
+subdir-ccflags-y += -I$(srctree)/sound/soc/mediatek/common
+
+# platform driver
+snd-soc-mt8189-afe-objs += \
+ mt8189-afe-pcm.o \
+ mt8189-afe-clk.o \
+ mt8189-dai-adda.o \
+ mt8189-dai-i2s.o \
+ mt8189-dai-pcm.o \
+ mt8189-dai-tdm.o
+
+obj-$(CONFIG_SND_SOC_MT8189) += snd-soc-mt8189-afe.o
diff --git a/sound/soc/mediatek/mt8189/mt8189-afe-pcm.c b/sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
new file mode 100644
index 000000000000..dcee8e11eca8
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
@@ -0,0 +1,2617 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek ALSA SoC AFE platform driver for 8189
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include "mt8189-afe-clk.h"
+#include "mt8189-afe-common.h"
+#include "mt8189-interconnection.h"
+
+#include "../common/mtk-afe-fe-dai.h"
+#include "../common/mtk-afe-platform-driver.h"
+
+static const struct snd_pcm_hardware mt8189_afe_hardware = {
+ .info = (SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_NO_PERIOD_WAKEUP |
+ SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_MMAP_VALID),
+ .formats = (SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE),
+ .period_bytes_min = 96,
+ .period_bytes_max = 4 * 48 * 1024,
+ .periods_min = 2,
+ .periods_max = 256,
+ .buffer_bytes_max = 256 * 1024,
+ .fifo_size = 0,
+};
+
+static unsigned int mt8189_rate_transform(struct device *dev, unsigned int rate)
+{
+ switch (rate) {
+ case 8000:
+ return MTK_AFE_IPM2P0_RATE_8K;
+ case 11025:
+ return MTK_AFE_IPM2P0_RATE_11K;
+ case 12000:
+ return MTK_AFE_IPM2P0_RATE_12K;
+ case 16000:
+ return MTK_AFE_IPM2P0_RATE_16K;
+ case 22050:
+ return MTK_AFE_IPM2P0_RATE_22K;
+ case 24000:
+ return MTK_AFE_IPM2P0_RATE_24K;
+ case 32000:
+ return MTK_AFE_IPM2P0_RATE_32K;
+ case 44100:
+ return MTK_AFE_IPM2P0_RATE_44K;
+ case 48000:
+ return MTK_AFE_IPM2P0_RATE_48K;
+ case 88200:
+ return MTK_AFE_IPM2P0_RATE_88K;
+ case 96000:
+ return MTK_AFE_IPM2P0_RATE_96K;
+ case 176400:
+ return MTK_AFE_IPM2P0_RATE_176K;
+ case 192000:
+ return MTK_AFE_IPM2P0_RATE_192K;
+ /* not support 260K */
+ case 352800:
+ return MTK_AFE_IPM2P0_RATE_352K;
+ case 384000:
+ return MTK_AFE_IPM2P0_RATE_384K;
+ default:
+ dev_warn(dev, "rate %u invalid, use %d!!!\n",
+ rate, MTK_AFE_IPM2P0_RATE_48K);
+ return MTK_AFE_IPM2P0_RATE_48K;
+ }
+}
+
+static inline unsigned int calculate_cm_update(unsigned int rate,
+ unsigned int ch)
+{
+ return (((26000000 / rate) - 10) / (ch / 2)) - 1;
+}
+
+static int mt8189_set_cm(struct mtk_base_afe *afe, int id,
+ bool update, bool swap, unsigned int ch)
+{
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ unsigned int rate = afe_priv->cm_rate[id];
+ unsigned int rate_val = mt8189_rate_transform(afe->dev, rate);
+ unsigned int update_val = update ? calculate_cm_update(rate, ch) : 0x64;
+ int reg = AFE_CM0_CON0 + 0x10 * id;
+
+ dev_dbg(afe->dev, "%s()-0, CM%d, rate %d, update %d, swap %d, ch %d\n",
+ __func__, id, rate, update, swap, ch);
+
+ /* update cnt */
+ regmap_update_bits(afe->regmap, reg,
+ AFE_CM_UPDATE_CNT_MASK << AFE_CM_UPDATE_CNT_SFT,
+ update_val << AFE_CM_UPDATE_CNT_SFT);
+
+ /* rate */
+ regmap_update_bits(afe->regmap, reg,
+ AFE_CM_1X_EN_SEL_FS_MASK << AFE_CM_1X_EN_SEL_FS_SFT,
+ rate_val << AFE_CM_1X_EN_SEL_FS_SFT);
+
+ /* ch num */
+ regmap_update_bits(afe->regmap, reg,
+ AFE_CM_CH_NUM_MASK << AFE_CM_CH_NUM_SFT,
+ (ch - 1) << AFE_CM_CH_NUM_SFT);
+
+ /* swap */
+ regmap_update_bits(afe->regmap, reg,
+ AFE_CM_BYTE_SWAP_MASK << AFE_CM_BYTE_SWAP_SFT,
+ swap << AFE_CM_BYTE_SWAP_SFT);
+
+ return 0;
+}
+
+static int mt8189_enable_cm_bypass(struct mtk_base_afe *afe, int id, bool en)
+{
+ return regmap_update_bits(afe->regmap, AFE_CM0_CON0 + 0x10 * id,
+ AFE_CM_BYPASS_MODE_MASK <<
+ AFE_CM_BYPASS_MODE_SFT,
+ en << AFE_CM_BYPASS_MODE_SFT);
+}
+
+static int mt8189_fe_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ int memif_num = cpu_dai->id;
+ struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
+ const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware;
+ int ret;
+
+ dev_dbg(afe->dev, "%s(), memif_num: %d.\n", __func__, memif_num);
+
+ memif->substream = substream;
+
+ snd_pcm_hw_constraint_step(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
+
+ snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware);
+
+ ret = snd_pcm_hw_constraint_integer(runtime,
+ SNDRV_PCM_HW_PARAM_PERIODS);
+ if (ret < 0)
+ dev_warn(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
+
+ /* dynamic allocate irq to memif */
+ if (memif->irq_usage < 0) {
+ int irq_id = mtk_dynamic_irq_acquire(afe);
+
+ if (irq_id != afe->irqs_size) {
+ /* link */
+ memif->irq_usage = irq_id;
+ } else {
+ dev_err(afe->dev, "%s() error: no more asys irq\n",
+ __func__);
+ ret = -EBUSY;
+ }
+ }
+
+ return ret;
+}
+
+static void mt8189_fe_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ int memif_num = cpu_dai->id;
+ struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
+ int irq_id = memif->irq_usage;
+
+ dev_dbg(afe->dev, "%s(), memif_num: %d.\n", __func__, memif_num);
+
+ memif->substream = NULL;
+
+ if (!memif->const_irq) {
+ mtk_dynamic_irq_release(afe, irq_id);
+ memif->irq_usage = -1;
+ memif->substream = NULL;
+ }
+}
+
+static int mt8189_fe_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ int id = dai->id;
+ int cm;
+
+ switch (id) {
+ case MT8189_MEMIF_VUL8:
+ case MT8189_MEMIF_VUL_CM0:
+ cm = CM0;
+ break;
+ case MT8189_MEMIF_VUL9:
+ case MT8189_MEMIF_VUL_CM1:
+ cm = CM1;
+ break;
+ default:
+ cm = CM0;
+ break;
+ }
+
+ afe_priv->cm_rate[cm] = params_rate(params);
+ afe_priv->cm_channels = params_channels(params);
+
+ return mtk_afe_fe_hw_params(substream, params, dai);
+}
+
+static int mt8189_fe_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ struct snd_pcm_runtime *const runtime = substream->runtime;
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ int id = cpu_dai->id;
+ struct mtk_base_afe_memif *memif = &afe->memif[id];
+ int irq_id = memif->irq_usage;
+ struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
+ const struct mtk_base_irq_data *irq_data = irqs->irq_data;
+ unsigned int counter = runtime->period_size;
+ unsigned int rate = runtime->rate;
+ unsigned int tmp_reg;
+ int fs;
+ int ret;
+
+ dev_dbg(afe->dev, "%s(), %s cmd %d, irq_id %d, dai_id %d\n", __func__,
+ memif->data->name, cmd, irq_id, id);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ ret = mtk_memif_set_enable(afe, id);
+ if (ret) {
+ dev_err(afe->dev, "id %d, memif enable fail.\n", id);
+ return ret;
+ }
+
+ /*
+ * for small latency record
+ * ul memif need read some data before irq enable
+ * the context of this triger ops is atmoic, so it cannot sleep
+ */
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+ if ((runtime->period_size * 1000) / rate <= 10)
+ udelay(300);
+
+ regmap_update_bits(afe->regmap,
+ irq_data->irq_cnt_reg,
+ irq_data->irq_cnt_maskbit <<
+ irq_data->irq_cnt_shift,
+ counter << irq_data->irq_cnt_shift);
+
+ /* set irq fs */
+ fs = afe->irq_fs(substream, rate);
+ if (fs < 0)
+ return -EINVAL;
+
+ if (irq_data->irq_fs_reg >= 0)
+ regmap_update_bits(afe->regmap,
+ irq_data->irq_fs_reg,
+ irq_data->irq_fs_maskbit <<
+ irq_data->irq_fs_shift,
+ fs << irq_data->irq_fs_shift);
+
+ /* enable interrupt */
+ regmap_update_bits(afe->regmap,
+ irq_data->irq_en_reg,
+ 1 << irq_data->irq_en_shift,
+ 1 << irq_data->irq_en_shift);
+
+ return 0;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ ret = mtk_memif_set_disable(afe, id);
+ if (ret)
+ dev_warn(afe->dev, "id %d, memif disable fail\n", id);
+
+ /* disable interrupt */
+ regmap_update_bits(afe->regmap,
+ irq_data->irq_en_reg,
+ 1 << irq_data->irq_en_shift,
+ 0 << irq_data->irq_en_shift);
+
+ /*
+ * clear pending IRQ, if the register read as one, there is no
+ * need to write one to clear operation.
+ */
+ regmap_read(afe->regmap, irq_data->irq_clr_reg, &tmp_reg);
+ regmap_update_bits(afe->regmap, irq_data->irq_clr_reg,
+ AFE_IRQ_CLR_CFG_MASK_SFT |
+ AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
+ tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
+ AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
+
+ return ret;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int mt8189_memif_fs(struct snd_pcm_substream *substream,
+ unsigned int rate)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ struct snd_soc_component *component =
+ snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
+ struct mtk_base_afe *afe = NULL;
+
+ if (!component)
+ return -EINVAL;
+
+ afe = snd_soc_component_get_drvdata(component);
+ if (!afe)
+ return -EINVAL;
+
+ return mt8189_rate_transform(afe->dev, rate);
+}
+
+static int mt8189_get_dai_fs(struct mtk_base_afe *afe,
+ int dai_id, unsigned int rate)
+{
+ return mt8189_rate_transform(afe->dev, rate);
+}
+
+static int mt8189_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ struct snd_soc_component *component =
+ snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
+ struct mtk_base_afe *afe = NULL;
+
+ if (!component)
+ return -EINVAL;
+ afe = snd_soc_component_get_drvdata(component);
+
+ return mt8189_rate_transform(afe->dev, rate);
+}
+
+static int mt8189_get_memif_pbuf_size(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+
+ if ((runtime->period_size * 1000) / runtime->rate > 10)
+ return MT8189_MEMIF_PBUF_SIZE_256_BYTES;
+
+ return MT8189_MEMIF_PBUF_SIZE_32_BYTES;
+}
+
+/* FE DAIs */
+static const struct snd_soc_dai_ops mt8189_memif_dai_ops = {
+ .startup = mt8189_fe_startup,
+ .shutdown = mt8189_fe_shutdown,
+ .hw_params = mt8189_fe_hw_params,
+ .hw_free = mtk_afe_fe_hw_free,
+ .prepare = mtk_afe_fe_prepare,
+ .trigger = mt8189_fe_trigger,
+};
+
+#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 | \
+ SNDRV_PCM_RATE_88200 | \
+ SNDRV_PCM_RATE_96000 | \
+ SNDRV_PCM_RATE_176400 | \
+ SNDRV_PCM_RATE_192000)
+
+#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 | \
+ SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_48000)
+
+#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+#define MT8189_FE_DAI_PLAYBACK(_name, _id, max_ch) \
+{ \
+ .name = #_name, \
+ .id = _id, \
+ .playback = { \
+ .stream_name = #_name, \
+ .channels_min = 1, \
+ .channels_max = max_ch, \
+ .rates = MTK_PCM_RATES, \
+ .formats = MTK_PCM_FORMATS, \
+ }, \
+ .ops = &mt8189_memif_dai_ops, \
+}
+
+#define MT8189_FE_DAI_CAPTURE(_name, _id, max_ch) \
+{ \
+ .name = #_name, \
+ .id = _id, \
+ .capture = { \
+ .stream_name = #_name, \
+ .channels_min = 1, \
+ .channels_max = max_ch, \
+ .rates = MTK_PCM_RATES, \
+ .formats = MTK_PCM_FORMATS, \
+ }, \
+ .ops = &mt8189_memif_dai_ops, \
+}
+
+static struct snd_soc_dai_driver mt8189_memif_dai_driver[] = {
+ /* FE DAIs: memory interfaces to CPU */
+ /* Playback */
+ MT8189_FE_DAI_PLAYBACK(DL0, MT8189_MEMIF_DL0, 2),
+ MT8189_FE_DAI_PLAYBACK(DL1, MT8189_MEMIF_DL1, 2),
+ MT8189_FE_DAI_PLAYBACK(DL2, MT8189_MEMIF_DL2, 2),
+ MT8189_FE_DAI_PLAYBACK(DL3, MT8189_MEMIF_DL3, 2),
+ MT8189_FE_DAI_PLAYBACK(DL4, MT8189_MEMIF_DL4, 2),
+ MT8189_FE_DAI_PLAYBACK(DL5, MT8189_MEMIF_DL5, 2),
+ MT8189_FE_DAI_PLAYBACK(DL6, MT8189_MEMIF_DL6, 2),
+ MT8189_FE_DAI_PLAYBACK(DL7, MT8189_MEMIF_DL7, 2),
+ MT8189_FE_DAI_PLAYBACK(DL8, MT8189_MEMIF_DL8, 2),
+ MT8189_FE_DAI_PLAYBACK(DL23, MT8189_MEMIF_DL23, 2),
+ MT8189_FE_DAI_PLAYBACK(DL24, MT8189_MEMIF_DL24, 2),
+ MT8189_FE_DAI_PLAYBACK(DL25, MT8189_MEMIF_DL25, 2),
+ MT8189_FE_DAI_PLAYBACK(DL_24CH, MT8189_MEMIF_DL_24CH, 8),
+ MT8189_FE_DAI_PLAYBACK(HDMI, MT8189_MEMIF_HDMI, 8),
+ /* Capture */
+ MT8189_FE_DAI_CAPTURE(UL0, MT8189_MEMIF_VUL0, 2),
+ MT8189_FE_DAI_CAPTURE(UL1, MT8189_MEMIF_VUL1, 2),
+ MT8189_FE_DAI_CAPTURE(UL2, MT8189_MEMIF_VUL2, 2),
+ MT8189_FE_DAI_CAPTURE(UL3, MT8189_MEMIF_VUL3, 2),
+ MT8189_FE_DAI_CAPTURE(UL4, MT8189_MEMIF_VUL4, 2),
+ MT8189_FE_DAI_CAPTURE(UL5, MT8189_MEMIF_VUL5, 2),
+ MT8189_FE_DAI_CAPTURE(UL6, MT8189_MEMIF_VUL6, 2),
+ MT8189_FE_DAI_CAPTURE(UL7, MT8189_MEMIF_VUL7, 2),
+ MT8189_FE_DAI_CAPTURE(UL8, MT8189_MEMIF_VUL8, 2),
+ MT8189_FE_DAI_CAPTURE(UL9, MT8189_MEMIF_VUL9, 16),
+ MT8189_FE_DAI_CAPTURE(UL10, MT8189_MEMIF_VUL10, 2),
+ MT8189_FE_DAI_CAPTURE(UL24, MT8189_MEMIF_VUL24, 2),
+ MT8189_FE_DAI_CAPTURE(UL25, MT8189_MEMIF_VUL25, 2),
+ MT8189_FE_DAI_CAPTURE(UL_CM0, MT8189_MEMIF_VUL_CM0, 8),
+ MT8189_FE_DAI_CAPTURE(UL_CM1, MT8189_MEMIF_VUL_CM1, 16),
+ MT8189_FE_DAI_CAPTURE(UL_ETDM_IN0, MT8189_MEMIF_ETDM_IN0, 2),
+ MT8189_FE_DAI_CAPTURE(UL_ETDM_IN1, MT8189_MEMIF_ETDM_IN1, 2),
+};
+
+static int ul_cm0_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ unsigned int channels = afe_priv->cm_channels;
+
+ dev_dbg(afe->dev, "%s(), event 0x%x, name %s, channels %d\n",
+ __func__, event, w->name, channels);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ mt8189_enable_cm_bypass(afe, CM0, false);
+ mt8189_set_cm(afe, CM0, true, false, channels);
+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
+ PDN_CM0_MASK_SFT, 0 << PDN_CM0_SFT);
+
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ mt8189_enable_cm_bypass(afe, CM0, true);
+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
+ PDN_CM0_MASK_SFT, 1 << PDN_CM0_SFT);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int ul_cm1_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+ struct mt8189_afe_private *afe_priv = afe->platform_priv;
+ unsigned int channels = afe_priv->cm_channels;
+
+ dev_dbg(afe->dev, "%s(), event 0x%x, name %s, channels %d\n",
+ __func__, event, w->name, channels);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ mt8189_enable_cm_bypass(afe, CM1, false);
+ mt8189_set_cm(afe, CM1, true, false, channels);
+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
+ PDN_CM1_MASK_SFT, 0 << PDN_CM1_SFT);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ mt8189_enable_cm_bypass(afe, CM1, true);
+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
+ PDN_CM1_MASK_SFT, 1 << PDN_CM1_SFT);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * dma widget & routes
+ * The mixer controls and routes are by no means fully implemented,
+ * only the ones that are intended to be used are, as other wise a fully
+ * interconnected switch bar mixer would introduce way too many unused
+ * controls.
+ */
+static const struct snd_kcontrol_new memif_ul0_ch1_mix[] = {
+ /* Normal record */
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN018_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN018_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN018_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN018_0,
+ I_ADDA_UL_CH4, 1, 0),
+ /* AP DMIC */
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH1", AFE_CONN018_0,
+ I_DMIC0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH2", AFE_CONN018_0,
+ I_DMIC0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN018_1,
+ I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN018_1,
+ I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN018_1,
+ I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN018_1,
+ I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN018_1,
+ I_DL4_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN018_1,
+ I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN018_1,
+ I_DL7_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN018_2,
+ I_DL23_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN018_1,
+ I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN018_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN018_4,
+ I_I2SIN0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN018_4,
+ I_I2SIN1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN018_6,
+ I_SRC_0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN018_6,
+ I_SRC_2_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul0_ch2_mix[] = {
+ /* Normal record */
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN019_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN019_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN019_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN019_0,
+ I_ADDA_UL_CH4, 1, 0),
+ /* AP DMIC */
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH2", AFE_CONN019_0,
+ I_DMIC0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN019_1,
+ I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN019_1,
+ I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN019_1,
+ I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN019_1,
+ I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN019_1,
+ I_DL4_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN019_1,
+ I_DL6_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN019_1,
+ I_DL7_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN018_2,
+ I_DL23_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN019_1,
+ I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN019_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN019_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN019_4,
+ I_I2SIN0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN019_4,
+ I_I2SIN1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN019_6,
+ I_SRC_0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN019_6,
+ I_SRC_2_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN020_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN020_1,
+ I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN020_1,
+ I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN020_1,
+ I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN020_1,
+ I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN020_1,
+ I_DL4_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN020_1,
+ I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN020_1,
+ I_DL7_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN020_2,
+ I_DL23_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN020_1,
+ I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN020_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN020_4,
+ I_I2SIN0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN020_4,
+ I_I2SIN1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN020_6,
+ I_SRC_0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN020_6,
+ I_SRC_2_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN021_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN021_1,
+ I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN021_1,
+ I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN021_1,
+ I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN021_1,
+ I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN021_1,
+ I_DL4_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN021_1,
+ I_DL6_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN021_1,
+ I_DL7_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN021_2,
+ I_DL23_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN021_1,
+ I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN021_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN021_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN021_4,
+ I_I2SIN0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN021_4,
+ I_I2SIN1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN021_6,
+ I_SRC_0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN021_6,
+ I_SRC_2_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN022_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN022_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN022_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN022_0,
+ I_ADDA_UL_CH4, 1, 0),
+ /* AP DMIC */
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH3", AFE_CONN022_0,
+ I_DMIC1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN1_OUT_CH1", AFE_CONN022_0,
+ I_GAIN1_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN022_6,
+ I_SRC_1_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN023_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN023_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN023_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN023_0,
+ I_ADDA_UL_CH4, 1, 0),
+ /* AP DMIC */
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH4", AFE_CONN023_0,
+ I_DMIC1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN1_OUT_CH2", AFE_CONN023_0,
+ I_GAIN1_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN023_6,
+ I_SRC_1_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN024_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN024_4,
+ I_I2SIN1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH1", AFE_CONN024_6,
+ I_SRC_3_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN025_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN025_4,
+ I_I2SIN1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH2", AFE_CONN025_6,
+ I_SRC_3_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN026_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN026_1,
+ I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN026_1,
+ I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN026_1,
+ I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN026_1,
+ I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN026_1,
+ I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN026_1,
+ I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN026_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN026_0,
+ I_GAIN0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH1", AFE_CONN026_6,
+ I_SRC_3_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN027_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN027_1,
+ I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN027_1,
+ I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN027_1,
+ I_DL6_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN027_1,
+ I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN027_1,
+ I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN027_1,
+ I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN027_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN027_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN027_0,
+ I_GAIN0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH2", AFE_CONN027_6,
+ I_SRC_3_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN028_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN028_1,
+ I_DL0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN028_1,
+ I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN028_1,
+ I_DL6_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN028_1,
+ I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN028_1,
+ I_DL3_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN028_1,
+ I_DL_24CH_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("GAIN0_OUT_CH1", AFE_CONN028_0,
+ I_GAIN0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH1", AFE_CONN028_6,
+ I_SRC_3_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN029_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN029_1,
+ I_DL0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN029_1,
+ I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN029_1,
+ I_DL6_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN029_1,
+ I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN029_1,
+ I_DL3_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN029_1,
+ I_DL_24CH_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN029_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN029_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("GAIN0_OUT_CH2", AFE_CONN029_0,
+ I_GAIN0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH2", AFE_CONN029_6,
+ I_SRC_3_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN030_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH1", AFE_CONN030_0,
+ I_DMIC0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN030_1,
+ I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN030_1,
+ I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN030_4,
+ I_I2SIN0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH1", AFE_CONN030_6,
+ I_SRC_4_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN031_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH2", AFE_CONN031_0,
+ I_DMIC0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN031_1,
+ I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN031_1,
+ I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN031_4,
+ I_I2SIN0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH2", AFE_CONN031_6,
+ I_SRC_4_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN032_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN032_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH3", AFE_CONN032_0,
+ I_DMIC1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN032_1,
+ I_DL1_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN032_1,
+ I_DL2_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN032_4,
+ I_I2SIN0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH1", AFE_CONN032_6,
+ I_SRC_4_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN033_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN033_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH4", AFE_CONN033_0,
+ I_DMIC1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN033_1,
+ I_DL1_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN033_1,
+ I_DL2_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN033_4,
+ I_I2SIN0_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH2", AFE_CONN033_6,
+ I_SRC_4_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN034_0,
+ I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN035_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN035_4,
+ I_PCM_0_CAP_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN035_4,
+ I_PCM_0_CAP_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul9_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN036_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN036_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN036_0,
+ I_ADDA_UL_CH3, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul9_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN037_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN037_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN037_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN037_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul24_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN066_0,
+ I_ADDA_UL_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul24_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN067_0,
+ I_ADDA_UL_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN040_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN040_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN040_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN040_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH1", AFE_CONN040_0,
+ I_DMIC0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN1_OUT_CH1", AFE_CONN040_0,
+ I_GAIN1_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN040_6,
+ I_SRC_0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN040_6,
+ I_SRC_1_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN041_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN041_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN041_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN041_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH2", AFE_CONN041_0,
+ I_DMIC0_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN1_OUT_CH2", AFE_CONN041_0,
+ I_GAIN1_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN041_6,
+ I_SRC_0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN041_6,
+ I_SRC_1_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch3_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN042_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN042_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN042_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN042_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH3", AFE_CONN042_0,
+ I_DMIC1_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch4_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN043_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN043_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN043_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN043_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH4", AFE_CONN043_0,
+ I_DMIC1_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch5_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN044_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN044_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN044_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN044_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch6_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN045_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN045_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN045_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN045_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch7_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN046_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN046_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN046_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN046_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm0_ch8_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN047_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN047_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN047_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN047_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch1_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN048_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN048_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN048_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN048_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN048_0,
+ I_ADDA_UL_CH5, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN048_0,
+ I_ADDA_UL_CH6, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN048_6,
+ I_SRC_0_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH1", AFE_CONN048_6,
+ I_SRC_3_OUT_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH1", AFE_CONN048_6,
+ I_SRC_4_OUT_CH1, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch2_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN049_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN049_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN049_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN049_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN049_0,
+ I_ADDA_UL_CH5, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN049_0,
+ I_ADDA_UL_CH6, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN049_6,
+ I_SRC_0_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH2", AFE_CONN049_6,
+ I_SRC_3_OUT_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH2", AFE_CONN049_6,
+ I_SRC_4_OUT_CH2, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch3_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN050_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN050_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN050_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN050_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN050_0,
+ I_ADDA_UL_CH5, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN050_0,
+ I_ADDA_UL_CH6, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch4_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN051_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN051_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN051_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN051_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN051_0,
+ I_ADDA_UL_CH5, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN051_0,
+ I_ADDA_UL_CH6, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch5_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN052_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN052_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN052_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN052_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN052_0,
+ I_ADDA_UL_CH5, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN052_0,
+ I_ADDA_UL_CH6, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch6_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN053_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN053_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN053_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN053_0,
+ I_ADDA_UL_CH4, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN053_0,
+ I_ADDA_UL_CH5, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN053_0,
+ I_ADDA_UL_CH6, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch7_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN054_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN054_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN054_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN054_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch8_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN055_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN055_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN055_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN055_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch9_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN056_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN056_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN056_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN056_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch10_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN057_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN057_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN057_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN057_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch11_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN058_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN058_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN058_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN058_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch12_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN059_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN059_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN059_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN059_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch13_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN060_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN060_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN060_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN060_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch14_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN061_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN061_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN061_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN061_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch15_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN062_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN062_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN062_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN062_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const struct snd_kcontrol_new memif_ul_cm1_ch16_mix[] = {
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN063_0,
+ I_ADDA_UL_CH1, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN063_0,
+ I_ADDA_UL_CH2, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN063_0,
+ I_ADDA_UL_CH3, 1, 0),
+ SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN063_0,
+ I_ADDA_UL_CH4, 1, 0),
+};
+
+static const char * const cm0_mux_texts[] = {
+ "CM0_2CH_PATH",
+ "CM0_8CH_PATH",
+};
+
+static const char * const cm1_mux_map_texts[] = {
+ "CM1_2CH_PATH",
+ "CM1_16CH_PATH",
+};
+
+static SOC_ENUM_SINGLE_DECL(ul_cm0_mux_map_enum,
+ AFE_CM0_CON0,
+ AFE_CM0_OUTPUT_MUX_SFT,
+ cm0_mux_texts);
+static SOC_ENUM_SINGLE_DECL(ul_cm1_mux_map_enum,
+ AFE_CM1_CON0,
+ AFE_CM1_OUTPUT_MUX_SFT,
+ cm1_mux_map_texts);
+
+static const struct snd_kcontrol_new ul_cm0_mux_control =
+ SOC_DAPM_ENUM("CM0_UL_MUX Route", ul_cm0_mux_map_enum);
+static const struct snd_kcontrol_new ul_cm1_mux_control =
+ SOC_DAPM_ENUM("CM1_UL_MUX Route", ul_cm1_mux_map_enum);
+
+static const struct snd_soc_dapm_widget mt8189_memif_widgets[] = {
+ /* inter-connections */
+ SND_SOC_DAPM_MIXER("UL0_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul0_ch1_mix, ARRAY_SIZE(memif_ul0_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL0_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul0_ch2_mix, ARRAY_SIZE(memif_ul0_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL9_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul9_ch1_mix, ARRAY_SIZE(memif_ul9_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL9_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul9_ch2_mix, ARRAY_SIZE(memif_ul9_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL24_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul24_ch1_mix, ARRAY_SIZE(memif_ul24_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL24_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul24_ch2_mix, ARRAY_SIZE(memif_ul24_ch2_mix)),
+
+ SND_SOC_DAPM_MIXER("UL_CM0_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm0_ch1_mix, ARRAY_SIZE(memif_ul_cm0_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM0_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm0_ch2_mix, ARRAY_SIZE(memif_ul_cm0_ch2_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM0_CH3", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm0_ch3_mix, ARRAY_SIZE(memif_ul_cm0_ch3_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM0_CH4", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm0_ch4_mix, ARRAY_SIZE(memif_ul_cm0_ch4_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM0_CH5", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm0_ch5_mix, ARRAY_SIZE(memif_ul_cm0_ch5_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM0_CH6", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm0_ch6_mix, ARRAY_SIZE(memif_ul_cm0_ch6_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM0_CH7", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm0_ch7_mix, ARRAY_SIZE(memif_ul_cm0_ch7_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM0_CH8", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm0_ch8_mix, ARRAY_SIZE(memif_ul_cm0_ch8_mix)),
+ SND_SOC_DAPM_MUX_E("CM0_UL_MUX", SND_SOC_NOPM, 0, 0,
+ &ul_cm0_mux_control,
+ ul_cm0_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+
+ SND_SOC_DAPM_MIXER("UL_CM1_CH1", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch1_mix, ARRAY_SIZE(memif_ul_cm1_ch1_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH2", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch2_mix, ARRAY_SIZE(memif_ul_cm1_ch2_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH3", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch3_mix, ARRAY_SIZE(memif_ul_cm1_ch3_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH4", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch4_mix, ARRAY_SIZE(memif_ul_cm1_ch4_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH5", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch5_mix, ARRAY_SIZE(memif_ul_cm1_ch5_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH6", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch6_mix, ARRAY_SIZE(memif_ul_cm1_ch6_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH7", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch7_mix, ARRAY_SIZE(memif_ul_cm1_ch7_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH8", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch8_mix, ARRAY_SIZE(memif_ul_cm1_ch8_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH9", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch9_mix, ARRAY_SIZE(memif_ul_cm1_ch9_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH10", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch10_mix, ARRAY_SIZE(memif_ul_cm1_ch10_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH11", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch11_mix, ARRAY_SIZE(memif_ul_cm1_ch11_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH12", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch12_mix, ARRAY_SIZE(memif_ul_cm1_ch12_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH13", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch13_mix, ARRAY_SIZE(memif_ul_cm1_ch13_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH14", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch14_mix, ARRAY_SIZE(memif_ul_cm1_ch14_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH15", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch15_mix, ARRAY_SIZE(memif_ul_cm1_ch15_mix)),
+ SND_SOC_DAPM_MIXER("UL_CM1_CH16", SND_SOC_NOPM, 0, 0,
+ memif_ul_cm1_ch16_mix, ARRAY_SIZE(memif_ul_cm1_ch16_mix)),
+ SND_SOC_DAPM_MUX("CM1_UL_MUX", SND_SOC_NOPM, 0, 0,
+ &ul_cm1_mux_control),
+ SND_SOC_DAPM_SUPPLY("CM0_Enable",
+ AFE_CM0_CON0, AFE_CM0_ON_SFT, 0,
+ ul_cm0_event,
+ SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_PRE_PMD),
+
+ SND_SOC_DAPM_SUPPLY("CM1_Enable",
+ AFE_CM1_CON0, AFE_CM0_ON_SFT, 0,
+ ul_cm1_event,
+ SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_PRE_PMD),
+
+ /* dynamic pinctrl */
+ SND_SOC_DAPM_PINCTRL("I2S0_PIN", "aud-gpio-i2s0-on", "aud-gpio-i2s0-off"),
+ SND_SOC_DAPM_PINCTRL("I2S1_PIN", "aud-gpio-i2s1-on", "aud-gpio-i2s1-off"),
+ SND_SOC_DAPM_PINCTRL("PCM0_PIN", "aud-gpio-pcm-on", "aud-gpio-pcm-off"),
+ SND_SOC_DAPM_PINCTRL("AP_DMIC0_PIN", "aud-gpio-ap-dmic-on", "aud-gpio-ap-dmic-off"),
+ SND_SOC_DAPM_PINCTRL("AP_DMIC1_PIN", "aud-gpio-ap-dmic1-on", "aud-gpio-ap-dmic1-off"),
+};
+
+static const struct snd_soc_dapm_route mt8189_memif_routes[] = {
+ {"UL0", NULL, "UL0_CH1"},
+ {"UL0", NULL, "UL0_CH2"},
+ /* Normal record */
+ {"UL0_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+ {"UL0_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+ {"UL0_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
+ {"UL0_CH1", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
+ {"UL0_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+ {"UL0_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+ {"UL0_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
+ {"UL0_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
+
+ {"UL0_CH1", "AP_DMIC_UL_CH1", "AP DMIC Capture"},
+ {"UL0_CH1", "AP_DMIC_UL_CH2", "AP DMIC Capture"},
+ {"UL0_CH2", "AP_DMIC_UL_CH2", "AP DMIC Capture"},
+
+ {"UL0_CH1", "I2SIN0_CH1", "I2SIN0"},
+ {"UL0_CH2", "I2SIN0_CH2", "I2SIN0"},
+ {"UL0_CH1", "I2SIN1_CH1", "I2SIN1"},
+ {"UL0_CH2", "I2SIN1_CH2", "I2SIN1"},
+
+ {"UL0_CH1", "PCM_0_CAP_CH1", "PCM 0 Capture"},
+ {"UL0_CH2", "PCM_0_CAP_CH1", "PCM 0 Capture"},
+
+ {"UL1", NULL, "UL1_CH1"},
+ {"UL1", NULL, "UL1_CH2"},
+
+ {"UL1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+ {"UL1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+
+ {"UL1_CH1", "I2SIN0_CH1", "I2SIN0"},
+ {"UL1_CH2", "I2SIN0_CH2", "I2SIN0"},
+ {"UL1_CH1", "I2SIN1_CH1", "I2SIN1"},
+ {"UL1_CH2", "I2SIN1_CH2", "I2SIN1"},
+
+ {"UL1_CH1", "PCM_0_CAP_CH1", "PCM 0 Capture"},
+ {"UL1_CH2", "PCM_0_CAP_CH1", "PCM 0 Capture"},
+
+ {"UL2", NULL, "UL2_CH1"},
+ {"UL2", NULL, "UL2_CH2"},
+
+ {"UL2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+ {"UL2_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+ {"UL2_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
+ {"UL2_CH1", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
+ {"UL2_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"},
+ {"UL2_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
+ {"UL2_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
+ {"UL2_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
+
+ {"UL2_CH1", "AP_DMIC_UL_CH3", "AP DMIC CH34 Capture"},
+ {"UL2_CH2", "AP_DMIC_UL_CH4", "AP DMIC CH34 Capture"},
+
+ {"UL3", NULL, "UL3_CH1"},
+ {"UL3", NULL, "UL3_CH2"},
+
+ {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL3_CH1", "I2SIN1_CH1", "I2SIN1"},
+ {"UL3_CH2", "I2SIN1_CH2", "I2SIN1"},
+
+ {"UL4", NULL, "UL4_CH1"},
+ {"UL4", NULL, "UL4_CH2"},
+ {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
+
+ {"UL4_CH1", "PCM_0_CAP_CH1", "PCM 0 Capture"},
+ {"UL4_CH2", "PCM_0_CAP_CH1", "PCM 0 Capture"},
+
+ {"UL5", NULL, "UL5_CH1"},
+ {"UL5", NULL, "UL5_CH2"},
+
+ {"UL5_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL5_CH2", "ADDA_UL_CH2", "ADDA Capture"},
+
+ {"UL6", NULL, "UL6_CH1"},
+ {"UL6", NULL, "UL6_CH2"},
+ {"UL6_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL6_CH2", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL6_CH1", "I2SIN0_CH1", "I2SIN0"},
+ {"UL6_CH2", "I2SIN0_CH2", "I2SIN0"},
+ {"UL6_CH1", "AP_DMIC_UL_CH1", "AP DMIC Capture"},
+ {"UL6_CH2", "AP_DMIC_UL_CH2", "AP DMIC Capture"},
+
+ {"UL7", NULL, "UL7_CH1"},
+ {"UL7", NULL, "UL7_CH2"},
+ {"UL7_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL7_CH1", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL7_CH2", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL7_CH2", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL7_CH1", "I2SIN0_CH1", "I2SIN0"},
+ {"UL7_CH2", "I2SIN0_CH2", "I2SIN0"},
+ {"UL7_CH1", "AP_DMIC_UL_CH3", "AP DMIC CH34 Capture"},
+ {"UL7_CH2", "AP_DMIC_UL_CH4", "AP DMIC CH34 Capture"},
+
+ {"UL8", NULL, "CM0_UL_MUX"},
+ {"CM0_UL_MUX", "CM0_2CH_PATH", "UL8_CH1"},
+ {"CM0_UL_MUX", "CM0_2CH_PATH", "UL8_CH2"},
+ {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH1"},
+ {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH2"},
+ {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH3"},
+ {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH4"},
+ {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH5"},
+ {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH6"},
+ {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH7"},
+ {"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH8"},
+
+ {"UL_CM0", NULL, "CM0_Enable"},
+
+ {"UL9", NULL, "CM1_UL_MUX"},
+ {"CM1_UL_MUX", "CM1_2CH_PATH", "UL9_CH1"},
+ {"CM1_UL_MUX", "CM1_2CH_PATH", "UL9_CH2"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH1"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH2"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH3"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH4"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH5"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH6"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH7"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH8"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH9"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH10"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH11"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH12"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH13"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH14"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH15"},
+ {"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH16"},
+
+ {"UL_CM1", NULL, "CM1_Enable"},
+
+ /* UL9 o36o37 <- ADDA */
+ {"UL9_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL9_CH1", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL9_CH2", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL9_CH2", "ADDA_UL_CH2", "ADDA Capture"},
+
+ {"UL24", NULL, "UL24_CH1"},
+ {"UL24", NULL, "UL24_CH2"},
+ {"UL24_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+
+ {"UL_CM0", NULL, "UL_CM0_CH1"},
+ {"UL_CM0", NULL, "UL_CM0_CH2"},
+ {"UL_CM0", NULL, "UL_CM0_CH3"},
+ {"UL_CM0", NULL, "UL_CM0_CH4"},
+ {"UL_CM0", NULL, "UL_CM0_CH5"},
+ {"UL_CM0", NULL, "UL_CM0_CH6"},
+ {"UL_CM0", NULL, "UL_CM0_CH7"},
+ {"UL_CM0", NULL, "UL_CM0_CH8"},
+ {"UL_CM0_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM0_CH1", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM0_CH2", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM0_CH2", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM0_CH3", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM0_CH3", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM0_CH4", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM0_CH4", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM0_CH1", "AP_DMIC_UL_CH1", "AP DMIC Capture"},
+ {"UL_CM0_CH2", "AP_DMIC_UL_CH2", "AP DMIC Capture"},
+ {"UL_CM0_CH3", "AP_DMIC_UL_CH3", "AP DMIC CH34 Capture"},
+ {"UL_CM0_CH4", "AP_DMIC_UL_CH4", "AP DMIC CH34 Capture"},
+
+ {"UL_CM1", NULL, "UL_CM1_CH1"},
+ {"UL_CM1", NULL, "UL_CM1_CH2"},
+ {"UL_CM1", NULL, "UL_CM1_CH3"},
+ {"UL_CM1", NULL, "UL_CM1_CH4"},
+ {"UL_CM1", NULL, "UL_CM1_CH5"},
+ {"UL_CM1", NULL, "UL_CM1_CH6"},
+ {"UL_CM1", NULL, "UL_CM1_CH7"},
+ {"UL_CM1", NULL, "UL_CM1_CH8"},
+ {"UL_CM1", NULL, "UL_CM1_CH9"},
+ {"UL_CM1", NULL, "UL_CM1_CH10"},
+ {"UL_CM1", NULL, "UL_CM1_CH11"},
+ {"UL_CM1", NULL, "UL_CM1_CH12"},
+ {"UL_CM1", NULL, "UL_CM1_CH13"},
+ {"UL_CM1", NULL, "UL_CM1_CH14"},
+ {"UL_CM1", NULL, "UL_CM1_CH15"},
+ {"UL_CM1", NULL, "UL_CM1_CH16"},
+ {"UL_CM1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM1_CH2", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM1_CH3", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM1_CH3", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM1_CH4", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM1_CH4", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM1_CH5", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM1_CH5", "ADDA_UL_CH2", "ADDA Capture"},
+ {"UL_CM1_CH6", "ADDA_UL_CH1", "ADDA Capture"},
+ {"UL_CM1_CH6", "ADDA_UL_CH2", "ADDA Capture"},
+
+ /* Audio Pin */
+ {"I2SOUT0", NULL, "I2S0_PIN"},
+ {"I2SIN0", NULL, "I2S0_PIN"},
+ {"I2SOUT1", NULL, "I2S1_PIN"},
+ {"I2SIN1", NULL, "I2S1_PIN"},
+ {"PCM 0 Playback", NULL, "PCM0_PIN"},
+ {"AP DMIC Capture", NULL, "AP_DMIC0_PIN"},
+ {"AP DMIC CH34 Capture", NULL, "AP_DMIC1_PIN"},
+};
+
+#define MT8189_DL_MEMIF(_id) \
+ [MT8189_MEMIF_##_id] = { \
+ .name = #_id, \
+ .id = MT8189_MEMIF_##_id, \
+ .reg_ofs_base = AFE_##_id##_BASE, \
+ .reg_ofs_cur = AFE_##_id##_CUR, \
+ .reg_ofs_end = AFE_##_id##_END, \
+ .reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
+ .reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
+ .reg_ofs_end_msb = AFE_##_id##_END_MSB, \
+ .fs_reg = AFE_##_id##_CON0, \
+ .fs_shift = _id##_SEL_FS_SFT, \
+ .fs_maskbit = _id##_SEL_FS_MASK, \
+ .mono_reg = AFE_##_id##_CON0, \
+ .mono_shift = _id##_MONO_SFT, \
+ .enable_reg = AFE_##_id##_CON0, \
+ .enable_shift = _id##_ON_SFT, \
+ .hd_reg = AFE_##_id##_CON0, \
+ .hd_shift = _id##_HD_MODE_SFT, \
+ .hd_align_reg = AFE_##_id##_CON0, \
+ .hd_align_mshift = _id##_HALIGN_SFT, \
+ .agent_disable_reg = -1, \
+ .agent_disable_shift = -1, \
+ .msb_reg = -1, \
+ .msb_shift = -1, \
+ .pbuf_reg = AFE_##_id##_CON0, \
+ .pbuf_mask = _id##_PBUF_SIZE_MASK, \
+ .pbuf_shift = _id##_PBUF_SIZE_SFT, \
+ .minlen_reg = AFE_##_id##_CON0, \
+ .minlen_mask = _id##_MINLEN_MASK, \
+ .minlen_shift = _id##_MINLEN_SFT, \
+}
+
+#define MT8189_MULTI_DL_MEMIF(_id) \
+ [MT8189_MEMIF_##_id] = { \
+ .name = #_id, \
+ .id = MT8189_MEMIF_##_id, \
+ .reg_ofs_base = AFE_##_id##_BASE, \
+ .reg_ofs_cur = AFE_##_id##_CUR, \
+ .reg_ofs_end = AFE_##_id##_END, \
+ .reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
+ .reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
+ .reg_ofs_end_msb = AFE_##_id##_END_MSB, \
+ .fs_reg = AFE_##_id##_CON0, \
+ .fs_shift = _id##_SEL_FS_SFT, \
+ .fs_maskbit = _id##_SEL_FS_MASK, \
+ .mono_reg = -1, \
+ .mono_shift = -1, \
+ .enable_reg = AFE_##_id##_CON0, \
+ .enable_shift = _id##_ON_SFT, \
+ .hd_reg = AFE_##_id##_CON0, \
+ .hd_shift = _id##_HD_MODE_SFT, \
+ .hd_align_reg = AFE_##_id##_CON0, \
+ .hd_align_mshift = _id##_HALIGN_SFT, \
+ .agent_disable_reg = -1, \
+ .agent_disable_shift = -1, \
+ .msb_reg = -1, \
+ .msb_shift = -1, \
+ .pbuf_reg = AFE_##_id##_CON0, \
+ .pbuf_mask = _id##_PBUF_SIZE_MASK, \
+ .pbuf_shift = _id##_PBUF_SIZE_SFT, \
+ .minlen_reg = AFE_##_id##_CON0, \
+ .minlen_mask = _id##_MINLEN_MASK, \
+ .minlen_shift = _id##_MINLEN_SFT, \
+ .ch_num_reg = AFE_##_id##_CON0, \
+ .ch_num_maskbit = _id##_NUM_MASK, \
+ .ch_num_shift = _id##_NUM_SFT, \
+}
+
+#define MT8189_UL_MEMIF(_id, _fs_shift, _fs_maskbit, _mono_shift) \
+ [MT8189_MEMIF_##_id] = { \
+ .name = #_id, \
+ .id = MT8189_MEMIF_##_id, \
+ .reg_ofs_base = AFE_##_id##_BASE, \
+ .reg_ofs_cur = AFE_##_id##_CUR, \
+ .reg_ofs_end = AFE_##_id##_END, \
+ .reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
+ .reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
+ .reg_ofs_end_msb = AFE_##_id##_END_MSB, \
+ .fs_reg = AFE_##_id##_CON0, \
+ .fs_shift = _fs_shift, \
+ .fs_maskbit = _fs_maskbit, \
+ .mono_reg = AFE_##_id##_CON0, \
+ .mono_shift = _mono_shift, \
+ .enable_reg = AFE_##_id##_CON0, \
+ .enable_shift = _id##_ON_SFT, \
+ .hd_reg = AFE_##_id##_CON0, \
+ .hd_shift = _id##_HD_MODE_SFT, \
+ .hd_align_reg = AFE_##_id##_CON0, \
+ .hd_align_mshift = _id##_HALIGN_SFT, \
+ .agent_disable_reg = -1, \
+ .agent_disable_shift = -1, \
+ .msb_reg = -1, \
+ .msb_shift = -1, \
+ }
+
+/* For convenience with macros: missing register fields */
+#define HDMI_SEL_FS_SFT -1
+#define HDMI_SEL_FS_MASK -1
+
+/* For convenience with macros: register name differences */
+#define AFE_HDMI_BASE AFE_HDMI_OUT_BASE
+#define AFE_HDMI_CUR AFE_HDMI_OUT_CUR
+#define AFE_HDMI_END AFE_HDMI_OUT_END
+#define AFE_HDMI_BASE_MSB AFE_HDMI_OUT_BASE_MSB
+#define AFE_HDMI_CUR_MSB AFE_HDMI_OUT_CUR_MSB
+#define AFE_HDMI_END_MSB AFE_HDMI_OUT_END_MSB
+#define AFE_HDMI_CON0 AFE_HDMI_OUT_CON0
+#define HDMI_ON_SFT HDMI_OUT_ON_SFT
+#define HDMI_HD_MODE_SFT HDMI_OUT_HD_MODE_SFT
+#define HDMI_HALIGN_SFT HDMI_OUT_HALIGN_SFT
+#define HDMI_PBUF_SIZE_MASK HDMI_OUT_PBUF_SIZE_MASK
+#define HDMI_PBUF_SIZE_SFT HDMI_OUT_PBUF_SIZE_SFT
+#define HDMI_MINLEN_MASK HDMI_OUT_MINLEN_MASK
+#define HDMI_MINLEN_SFT HDMI_OUT_MINLEN_SFT
+#define HDMI_NUM_MASK HDMI_CH_NUM_MASK
+#define HDMI_NUM_SFT HDMI_CH_NUM_SFT
+
+static const struct mtk_base_memif_data memif_data[MT8189_MEMIF_NUM] = {
+ MT8189_DL_MEMIF(DL0),
+ MT8189_DL_MEMIF(DL1),
+ MT8189_DL_MEMIF(DL2),
+ MT8189_DL_MEMIF(DL3),
+ MT8189_DL_MEMIF(DL4),
+ MT8189_DL_MEMIF(DL5),
+ MT8189_DL_MEMIF(DL6),
+ MT8189_DL_MEMIF(DL7),
+ MT8189_DL_MEMIF(DL8),
+ MT8189_DL_MEMIF(DL23),
+ MT8189_DL_MEMIF(DL24),
+ MT8189_DL_MEMIF(DL25),
+ MT8189_MULTI_DL_MEMIF(DL_24CH),
+ MT8189_MULTI_DL_MEMIF(HDMI),
+ MT8189_UL_MEMIF(VUL0, VUL0_SEL_FS_SFT, VUL0_SEL_FS_MASK, VUL0_MONO_SFT),
+ MT8189_UL_MEMIF(VUL1, VUL1_SEL_FS_SFT, VUL1_SEL_FS_MASK, VUL1_MONO_SFT),
+ MT8189_UL_MEMIF(VUL2, VUL2_SEL_FS_SFT, VUL2_SEL_FS_MASK, VUL2_MONO_SFT),
+ MT8189_UL_MEMIF(VUL3, VUL3_SEL_FS_SFT, VUL3_SEL_FS_MASK, VUL3_MONO_SFT),
+ MT8189_UL_MEMIF(VUL4, VUL4_SEL_FS_SFT, VUL4_SEL_FS_MASK, VUL4_MONO_SFT),
+ MT8189_UL_MEMIF(VUL5, VUL5_SEL_FS_SFT, VUL5_SEL_FS_MASK, VUL5_MONO_SFT),
+ MT8189_UL_MEMIF(VUL6, VUL6_SEL_FS_SFT, VUL6_SEL_FS_MASK, VUL6_MONO_SFT),
+ MT8189_UL_MEMIF(VUL7, VUL7_SEL_FS_SFT, VUL7_SEL_FS_MASK, VUL7_MONO_SFT),
+ MT8189_UL_MEMIF(VUL8, VUL8_SEL_FS_SFT, VUL8_SEL_FS_MASK, VUL8_MONO_SFT),
+ MT8189_UL_MEMIF(VUL9, VUL9_SEL_FS_SFT, VUL9_SEL_FS_MASK, VUL9_MONO_SFT),
+ MT8189_UL_MEMIF(VUL10, VUL10_SEL_FS_SFT, VUL10_SEL_FS_MASK, VUL10_MONO_SFT),
+ MT8189_UL_MEMIF(VUL24, VUL24_SEL_FS_SFT, VUL24_SEL_FS_MASK, VUL24_MONO_SFT),
+ MT8189_UL_MEMIF(VUL25, VUL25_SEL_FS_SFT, VUL25_SEL_FS_MASK, VUL25_MONO_SFT),
+ MT8189_UL_MEMIF(VUL_CM0, -1, -1, -1),
+ MT8189_UL_MEMIF(VUL_CM1, -1, -1, -1),
+ MT8189_UL_MEMIF(ETDM_IN0, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
+ MT8189_UL_MEMIF(ETDM_IN1, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
+};
+
+#define MT8189_AFE_IRQ(_id) \
+ [MT8189_IRQ_##_id] = { \
+ .id = MT8189_IRQ_##_id, \
+ .irq_cnt_reg = AFE_IRQ##_id##_MCU_CFG1, \
+ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, \
+ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, \
+ .irq_fs_reg = AFE_IRQ##_id##_MCU_CFG0, \
+ .irq_fs_shift = AFE_IRQ##_id##_MCU_FS_SFT, \
+ .irq_fs_maskbit = AFE_IRQ##_id##_MCU_FS_MASK, \
+ .irq_en_reg = AFE_IRQ##_id##_MCU_CFG0, \
+ .irq_en_shift = AFE_IRQ##_id##_MCU_ON_SFT, \
+ .irq_clr_reg = AFE_IRQ##_id##_MCU_CFG1, \
+ .irq_clr_shift = AFE_IRQ##_id##_CLR_CFG_SFT, \
+ }
+
+#define MT8189_AFE_TDM_IRQ(_id) \
+ [MT8189_IRQ_##_id] = { \
+ .id = MT8189_CUS_IRQ_TDM, \
+ .irq_cnt_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, \
+ .irq_cnt_shift = AFE_CUSTOM_IRQ0_MCU_CNT_SFT, \
+ .irq_cnt_maskbit = AFE_CUSTOM_IRQ0_MCU_CNT_MASK, \
+ .irq_fs_reg = -1, \
+ .irq_fs_shift = -1, \
+ .irq_fs_maskbit = -1, \
+ .irq_en_reg = AFE_CUSTOM_IRQ0_MCU_CFG0, \
+ .irq_en_shift = AFE_CUSTOM_IRQ0_MCU_ON_SFT, \
+ .irq_clr_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, \
+ .irq_clr_shift = AFE_CUSTOM_IRQ0_CLR_CFG_SFT, \
+ }
+
+static const struct mtk_base_irq_data irq_data[MT8189_IRQ_NUM] = {
+ MT8189_AFE_IRQ(0),
+ MT8189_AFE_IRQ(1),
+ MT8189_AFE_IRQ(2),
+ MT8189_AFE_IRQ(3),
+ MT8189_AFE_IRQ(4),
+ MT8189_AFE_IRQ(5),
+ MT8189_AFE_IRQ(6),
+ MT8189_AFE_IRQ(7),
+ MT8189_AFE_IRQ(8),
+ MT8189_AFE_IRQ(9),
+ MT8189_AFE_IRQ(10),
+ MT8189_AFE_IRQ(11),
+ MT8189_AFE_IRQ(12),
+ MT8189_AFE_IRQ(13),
+ MT8189_AFE_IRQ(14),
+ MT8189_AFE_IRQ(15),
+ MT8189_AFE_IRQ(16),
+ MT8189_AFE_IRQ(17),
+ MT8189_AFE_IRQ(18),
+ MT8189_AFE_IRQ(19),
+ MT8189_AFE_IRQ(20),
+ MT8189_AFE_IRQ(21),
+ MT8189_AFE_IRQ(22),
+ MT8189_AFE_IRQ(23),
+ MT8189_AFE_IRQ(24),
+ MT8189_AFE_IRQ(25),
+ MT8189_AFE_IRQ(26),
+ MT8189_AFE_TDM_IRQ(31),
+};
+
+static const int memif_irq_usage[MT8189_MEMIF_NUM] = {
+ /* TODO: verify each memif & irq */
+ [MT8189_MEMIF_DL0] = MT8189_IRQ_0,
+ [MT8189_MEMIF_DL1] = MT8189_IRQ_1,
+ [MT8189_MEMIF_DL2] = MT8189_IRQ_2,
+ [MT8189_MEMIF_DL3] = MT8189_IRQ_3,
+ [MT8189_MEMIF_DL4] = MT8189_IRQ_4,
+ [MT8189_MEMIF_DL5] = MT8189_IRQ_5,
+ [MT8189_MEMIF_DL6] = MT8189_IRQ_6,
+ [MT8189_MEMIF_DL7] = MT8189_IRQ_7,
+ [MT8189_MEMIF_DL8] = MT8189_IRQ_8,
+ [MT8189_MEMIF_DL23] = MT8189_IRQ_9,
+ [MT8189_MEMIF_DL24] = MT8189_IRQ_10,
+ [MT8189_MEMIF_DL25] = MT8189_IRQ_11,
+ [MT8189_MEMIF_DL_24CH] = MT8189_IRQ_12,
+ [MT8189_MEMIF_VUL0] = MT8189_IRQ_13,
+ [MT8189_MEMIF_VUL1] = MT8189_IRQ_14,
+ [MT8189_MEMIF_VUL2] = MT8189_IRQ_15,
+ [MT8189_MEMIF_VUL3] = MT8189_IRQ_16,
+ [MT8189_MEMIF_VUL4] = MT8189_IRQ_17,
+ [MT8189_MEMIF_VUL5] = MT8189_IRQ_18,
+ [MT8189_MEMIF_VUL6] = MT8189_IRQ_19,
+ [MT8189_MEMIF_VUL7] = MT8189_IRQ_20,
+ [MT8189_MEMIF_VUL8] = MT8189_IRQ_21,
+ [MT8189_MEMIF_VUL9] = MT8189_IRQ_22,
+ [MT8189_MEMIF_VUL10] = MT8189_IRQ_23,
+ [MT8189_MEMIF_VUL24] = MT8189_IRQ_24,
+ [MT8189_MEMIF_VUL25] = MT8189_IRQ_25,
+ [MT8189_MEMIF_VUL_CM0] = MT8189_IRQ_26,
+ [MT8189_MEMIF_VUL_CM1] = MT8189_IRQ_0,
+ [MT8189_MEMIF_ETDM_IN0] = MT8189_IRQ_0,
+ [MT8189_MEMIF_ETDM_IN1] = MT8189_IRQ_0,
+ [MT8189_MEMIF_HDMI] = MT8189_IRQ_31
+};
+
+static bool mt8189_is_volatile_reg(struct device *dev, unsigned int reg)
+{
+ /* these auto-gen reg has read-only bit, so put it as volatile */
+ /* volatile reg cannot be cached, so cannot be set when power off */
+ switch (reg) {
+ case AUDIO_TOP_CON0:
+ case AUDIO_TOP_CON1:
+ case AUDIO_TOP_CON2:
+ case AUDIO_TOP_CON3:
+ case AUDIO_TOP_CON4:
+ case AFE_APLL1_TUNER_MON0:
+ case AFE_APLL2_TUNER_MON0:
+ case AFE_SPM_CONTROL_ACK:
+ case AUDIO_TOP_IP_VERSION:
+ case AUDIO_ENGEN_CON0_MON:
+ case AFE_CONNSYS_I2S_IPM_VER_MON:
+ case AFE_CONNSYS_I2S_MON:
+ case AFE_PCM_INTF_MON:
+ case AFE_PCM_TOP_IP_VERSION:
+ case AFE_IRQ_MCU_STATUS:
+ case AFE_CUSTOM_IRQ_MCU_STATUS:
+ case AFE_IRQ_MCU_MON0:
+ case AFE_IRQ_MCU_MON1:
+ case AFE_IRQ_MCU_MON2:
+ case AFE_IRQ0_CNT_MON:
+ case AFE_IRQ1_CNT_MON:
+ case AFE_IRQ2_CNT_MON:
+ case AFE_IRQ3_CNT_MON:
+ case AFE_IRQ4_CNT_MON:
+ case AFE_IRQ5_CNT_MON:
+ case AFE_IRQ6_CNT_MON:
+ case AFE_IRQ7_CNT_MON:
+ case AFE_IRQ8_CNT_MON:
+ case AFE_IRQ9_CNT_MON:
+ case AFE_IRQ10_CNT_MON:
+ case AFE_IRQ11_CNT_MON:
+ case AFE_IRQ12_CNT_MON:
+ case AFE_IRQ13_CNT_MON:
+ case AFE_IRQ14_CNT_MON:
+ case AFE_IRQ15_CNT_MON:
+ case AFE_IRQ16_CNT_MON:
+ case AFE_IRQ17_CNT_MON:
+ case AFE_IRQ18_CNT_MON:
+ case AFE_IRQ19_CNT_MON:
+ case AFE_IRQ20_CNT_MON:
+ case AFE_IRQ21_CNT_MON:
+ case AFE_IRQ22_CNT_MON:
+ case AFE_IRQ23_CNT_MON:
+ case AFE_IRQ24_CNT_MON:
+ case AFE_IRQ25_CNT_MON:
+ case AFE_IRQ26_CNT_MON:
+ case AFE_CM0_MON:
+ case AFE_CM0_IP_VERSION:
+ case AFE_CM1_MON:
+ case AFE_CM1_IP_VERSION:
+ case AFE_ADDA_UL0_SRC_DEBUG_MON0:
+ case AFE_ADDA_UL0_SRC_MON0:
+ case AFE_ADDA_UL0_SRC_MON1:
+ case AFE_ADDA_UL0_IP_VERSION:
+ case AFE_ADDA_DMIC0_SRC_DEBUG_MON0:
+ case AFE_ADDA_DMIC0_SRC_MON0:
+ case AFE_ADDA_DMIC0_SRC_MON1:
+ case AFE_ADDA_DMIC0_IP_VERSION:
+ case AFE_ADDA_DMIC1_SRC_DEBUG_MON0:
+ case AFE_ADDA_DMIC1_SRC_MON0:
+ case AFE_ADDA_DMIC1_SRC_MON1:
+ case AFE_ADDA_DMIC1_IP_VERSION:
+ case AFE_MTKAIF_IPM_VER_MON:
+ case AFE_MTKAIF_MON:
+ case AFE_AUD_PAD_TOP_MON:
+ case AFE_ADDA_MTKAIFV4_MON0:
+ case AFE_ADDA_MTKAIFV4_MON1:
+ case AFE_ADDA6_MTKAIFV4_MON0:
+ case ETDM_IN0_MON:
+ case ETDM_IN1_MON:
+ case ETDM_OUT0_MON:
+ case ETDM_OUT1_MON:
+ case ETDM_OUT4_MON:
+ case AFE_CONN_MON0:
+ case AFE_CONN_MON1:
+ case AFE_CONN_MON2:
+ case AFE_CONN_MON3:
+ case AFE_CONN_MON4:
+ case AFE_CONN_MON5:
+ case AFE_CBIP_SLV_DECODER_MON0:
+ case AFE_CBIP_SLV_DECODER_MON1:
+ case AFE_CBIP_SLV_MUX_MON0:
+ case AFE_CBIP_SLV_MUX_MON1:
+ case AFE_DL0_CUR_MSB:
+ case AFE_DL0_CUR:
+ case AFE_DL0_RCH_MON:
+ case AFE_DL0_LCH_MON:
+ case AFE_DL1_CUR_MSB:
+ case AFE_DL1_CUR:
+ case AFE_DL1_RCH_MON:
+ case AFE_DL1_LCH_MON:
+ case AFE_DL2_CUR_MSB:
+ case AFE_DL2_CUR:
+ case AFE_DL2_RCH_MON:
+ case AFE_DL2_LCH_MON:
+ case AFE_DL3_CUR_MSB:
+ case AFE_DL3_CUR:
+ case AFE_DL3_RCH_MON:
+ case AFE_DL3_LCH_MON:
+ case AFE_DL4_CUR_MSB:
+ case AFE_DL4_CUR:
+ case AFE_DL4_RCH_MON:
+ case AFE_DL4_LCH_MON:
+ case AFE_DL5_CUR_MSB:
+ case AFE_DL5_CUR:
+ case AFE_DL5_RCH_MON:
+ case AFE_DL5_LCH_MON:
+ case AFE_DL6_CUR_MSB:
+ case AFE_DL6_CUR:
+ case AFE_DL6_RCH_MON:
+ case AFE_DL6_LCH_MON:
+ case AFE_DL7_CUR_MSB:
+ case AFE_DL7_CUR:
+ case AFE_DL7_RCH_MON:
+ case AFE_DL7_LCH_MON:
+ case AFE_DL8_CUR_MSB:
+ case AFE_DL8_CUR:
+ case AFE_DL8_RCH_MON:
+ case AFE_DL8_LCH_MON:
+ case AFE_DL_24CH_CUR_MSB:
+ case AFE_DL_24CH_CUR:
+ case AFE_DL23_CUR_MSB:
+ case AFE_DL23_CUR:
+ case AFE_DL23_RCH_MON:
+ case AFE_DL23_LCH_MON:
+ case AFE_DL24_CUR_MSB:
+ case AFE_DL24_CUR:
+ case AFE_DL24_RCH_MON:
+ case AFE_DL24_LCH_MON:
+ case AFE_DL25_CUR_MSB:
+ case AFE_DL25_CUR:
+ case AFE_DL25_RCH_MON:
+ case AFE_DL25_LCH_MON:
+ case AFE_VUL0_CUR_MSB:
+ case AFE_VUL0_CUR:
+ case AFE_VUL1_CUR_MSB:
+ case AFE_VUL1_CUR:
+ case AFE_VUL2_CUR_MSB:
+ case AFE_VUL2_CUR:
+ case AFE_VUL3_CUR_MSB:
+ case AFE_VUL3_CUR:
+ case AFE_VUL4_CUR_MSB:
+ case AFE_VUL4_CUR:
+ case AFE_VUL5_CUR_MSB:
+ case AFE_VUL5_CUR:
+ case AFE_VUL6_CUR_MSB:
+ case AFE_VUL6_CUR:
+ case AFE_VUL7_CUR_MSB:
+ case AFE_VUL7_CUR:
+ case AFE_VUL8_CUR_MSB:
+ case AFE_VUL8_CUR:
+ case AFE_VUL9_CUR_MSB:
+ case AFE_VUL9_CUR:
+ case AFE_VUL10_CUR_MSB:
+ case AFE_VUL10_CUR:
+ case AFE_VUL24_CUR_MSB:
+ case AFE_VUL24_CUR:
+ case AFE_VUL25_CUR_MSB:
+ case AFE_VUL25_CUR:
+ case AFE_VUL_CM0_CUR_MSB:
+ case AFE_VUL_CM0_CUR:
+ case AFE_VUL_CM1_CUR_MSB:
+ case AFE_VUL_CM1_CUR:
+ case AFE_ETDM_IN0_CUR_MSB:
+ case AFE_ETDM_IN0_CUR:
+ case AFE_ETDM_IN1_CUR_MSB:
+ case AFE_ETDM_IN1_CUR:
+ case AFE_HDMI_OUT_CUR_MSB:
+ case AFE_HDMI_OUT_CUR:
+ case AFE_HDMI_OUT_END:
+ case AFE_HDMI_OUT_MON0:
+ case AFE_PROT_SIDEBAND0_MON:
+ case AFE_PROT_SIDEBAND1_MON:
+ case AFE_PROT_SIDEBAND2_MON:
+ case AFE_PROT_SIDEBAND3_MON:
+ case AFE_DOMAIN_SIDEBAND0_MON:
+ case AFE_DOMAIN_SIDEBAND1_MON:
+ case AFE_DOMAIN_SIDEBAND2_MON:
+ case AFE_DOMAIN_SIDEBAND3_MON:
+ case AFE_DOMAIN_SIDEBAND4_MON:
+ case AFE_DOMAIN_SIDEBAND5_MON:
+ case AFE_DOMAIN_SIDEBAND6_MON:
+ case AFE_DOMAIN_SIDEBAND7_MON:
+ case AFE_DOMAIN_SIDEBAND8_MON:
+ case AFE_DOMAIN_SIDEBAND9_MON:
+ case AFE_PCM0_INTF_CON1_MASK_MON:
+ case AFE_CONNSYS_I2S_CON_MASK_MON:
+ case AFE_MTKAIF0_CFG0_MASK_MON:
+ case AFE_MTKAIF1_CFG0_MASK_MON:
+ case AFE_ADDA_UL0_SRC_CON0_MASK_MON:
+ case AFE_ASRC_NEW_CON0:
+ case AFE_ASRC_NEW_CON6:
+ case AFE_ASRC_NEW_CON8:
+ case AFE_ASRC_NEW_CON9:
+ case AFE_ASRC_NEW_CON12:
+ case AFE_ASRC_NEW_IP_VERSION:
+ case AFE_GASRC0_NEW_CON0:
+ case AFE_GASRC0_NEW_CON6:
+ case AFE_GASRC0_NEW_CON8:
+ case AFE_GASRC0_NEW_CON9:
+ case AFE_GASRC0_NEW_CON10:
+ case AFE_GASRC0_NEW_CON11:
+ case AFE_GASRC0_NEW_CON12:
+ case AFE_GASRC0_NEW_IP_VERSION:
+ case AFE_GASRC1_NEW_CON0:
+ case AFE_GASRC1_NEW_CON6:
+ case AFE_GASRC1_NEW_CON8:
+ case AFE_GASRC1_NEW_CON9:
+ case AFE_GASRC1_NEW_CON12:
+ case AFE_GASRC1_NEW_IP_VERSION:
+ case AFE_GASRC2_NEW_CON0:
+ case AFE_GASRC2_NEW_CON6:
+ case AFE_GASRC2_NEW_CON8:
+ case AFE_GASRC2_NEW_CON9:
+ case AFE_GASRC2_NEW_CON12:
+ case AFE_GASRC2_NEW_IP_VERSION:
+ case AFE_GAIN0_CUR_L:
+ case AFE_GAIN0_CUR_R:
+ case AFE_GAIN1_CUR_L:
+ case AFE_GAIN1_CUR_R:
+ case AFE_GAIN2_CUR_L:
+ case AFE_GAIN2_CUR_R:
+ case AFE_GAIN3_CUR_L:
+ case AFE_GAIN3_CUR_R:
+ case AFE_IRQ_MCU_EN:
+ case AFE_CUSTOM_IRQ_MCU_EN:
+ case AFE_IRQ_MCU_DSP_EN:
+ case AFE_IRQ_MCU_DSP2_EN:
+ case AFE_DL5_CON0:
+ case AFE_DL6_CON0:
+ case AFE_DL23_CON0:
+ case AFE_DL_24CH_CON0:
+ case AFE_VUL1_CON0:
+ case AFE_VUL3_CON0:
+ case AFE_VUL4_CON0:
+ case AFE_VUL5_CON0:
+ case AFE_VUL9_CON0:
+ case AFE_VUL25_CON0:
+ case AFE_IRQ0_MCU_CFG0:
+ case AFE_IRQ1_MCU_CFG0:
+ case AFE_IRQ2_MCU_CFG0:
+ case AFE_IRQ3_MCU_CFG0:
+ case AFE_IRQ4_MCU_CFG0:
+ case AFE_IRQ5_MCU_CFG0:
+ case AFE_IRQ6_MCU_CFG0:
+ case AFE_IRQ7_MCU_CFG0:
+ case AFE_IRQ8_MCU_CFG0:
+ case AFE_IRQ9_MCU_CFG0:
+ case AFE_IRQ10_MCU_CFG0:
+ case AFE_IRQ11_MCU_CFG0:
+ case AFE_IRQ12_MCU_CFG0:
+ case AFE_IRQ13_MCU_CFG0:
+ case AFE_IRQ14_MCU_CFG0:
+ case AFE_IRQ15_MCU_CFG0:
+ case AFE_IRQ16_MCU_CFG0:
+ case AFE_IRQ17_MCU_CFG0:
+ case AFE_IRQ18_MCU_CFG0:
+ case AFE_IRQ19_MCU_CFG0:
+ case AFE_IRQ20_MCU_CFG0:
+ case AFE_IRQ21_MCU_CFG0:
+ case AFE_IRQ22_MCU_CFG0:
+ case AFE_IRQ23_MCU_CFG0:
+ case AFE_IRQ24_MCU_CFG0:
+ case AFE_IRQ25_MCU_CFG0:
+ case AFE_IRQ26_MCU_CFG0:
+ case AFE_CUSTOM_IRQ0_MCU_CFG0:
+ case AFE_IRQ0_MCU_CFG1:
+ case AFE_IRQ1_MCU_CFG1:
+ case AFE_IRQ2_MCU_CFG1:
+ case AFE_IRQ3_MCU_CFG1:
+ case AFE_IRQ4_MCU_CFG1:
+ case AFE_IRQ5_MCU_CFG1:
+ case AFE_IRQ6_MCU_CFG1:
+ case AFE_IRQ7_MCU_CFG1:
+ case AFE_IRQ8_MCU_CFG1:
+ case AFE_IRQ9_MCU_CFG1:
+ case AFE_IRQ10_MCU_CFG1:
+ case AFE_IRQ11_MCU_CFG1:
+ case AFE_IRQ12_MCU_CFG1:
+ case AFE_IRQ13_MCU_CFG1:
+ case AFE_IRQ14_MCU_CFG1:
+ case AFE_IRQ15_MCU_CFG1:
+ case AFE_IRQ16_MCU_CFG1:
+ case AFE_IRQ17_MCU_CFG1:
+ case AFE_IRQ18_MCU_CFG1:
+ case AFE_IRQ19_MCU_CFG1:
+ case AFE_IRQ20_MCU_CFG1:
+ case AFE_IRQ21_MCU_CFG1:
+ case AFE_IRQ22_MCU_CFG1:
+ case AFE_IRQ23_MCU_CFG1:
+ case AFE_IRQ24_MCU_CFG1:
+ case AFE_IRQ25_MCU_CFG1:
+ case AFE_IRQ26_MCU_CFG1:
+ case AFE_CUSTOM_IRQ0_MCU_CFG1:
+ /* for vow using */
+ case AFE_IRQ_MCU_SCP_EN:
+ case AFE_VUL_CM0_BASE_MSB:
+ case AFE_VUL_CM0_BASE:
+ case AFE_VUL_CM0_END_MSB:
+ case AFE_VUL_CM0_END:
+ case AFE_VUL_CM0_CON0:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static const struct regmap_config mt8189_afe_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+
+ .volatile_reg = mt8189_is_volatile_reg,
+
+ .max_register = AFE_MAX_REGISTER,
+ .num_reg_defaults_raw = AFE_MAX_REGISTER,
+
+ .cache_type = REGCACHE_FLAT,
+};
+
+static irqreturn_t mt8189_afe_irq_handler(int irq_id, void *dev)
+{
+ struct mtk_base_afe *afe = dev;
+ struct mtk_base_afe_irq *irq;
+ u32 status;
+ u32 status_mcu;
+ u32 mcu_en;
+ u32 cus_status;
+ u32 cus_status_mcu;
+ u32 cus_mcu_en;
+ u32 tmp_reg;
+ int ret, cus_ret;
+ int i;
+ struct timespec64 ts64;
+ u64 t1, t2;
+ /* one interrupt period = 5ms */
+ const u64 timeout_limit = 5000000;
+
+ /* get irq that is sent to MCU */
+ regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
+ regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_EN, &cus_mcu_en);
+
+ ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
+ cus_ret = regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_STATUS, &cus_status);
+ /* only care IRQ which is sent to MCU */
+ status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
+ cus_status_mcu = cus_status & cus_mcu_en & AFE_IRQ_STATUS_BITS;
+ if ((ret || status_mcu == 0) && (cus_ret || cus_status_mcu == 0)) {
+ dev_err(afe->dev, "%s(), irq status err, ret %d, 0x%x:0x%x:0x%x:0x%x\n",
+ __func__, ret, status, mcu_en, cus_status_mcu, cus_mcu_en);
+ return IRQ_NONE;
+ }
+
+ ktime_get_ts64(&ts64);
+ t1 = ktime_get_ns();
+
+ for (i = 0; i < MT8189_MEMIF_NUM; i++) {
+ struct mtk_base_afe_memif *memif = &afe->memif[i];
+
+ if (!memif->substream)
+ continue;
+
+ if (memif->irq_usage < 0)
+ continue;
+ irq = &afe->irqs[memif->irq_usage];
+
+ if (i == MT8189_MEMIF_HDMI) {
+ if (cus_status_mcu & BIT(irq->irq_data->id))
+ snd_pcm_period_elapsed(memif->substream);
+ } else if (status_mcu & BIT(irq->irq_data->id)) {
+ snd_pcm_period_elapsed(memif->substream);
+ }
+ }
+
+ ktime_get_ts64(&ts64);
+ t2 = ktime_get_ns();
+ t2 = t2 - t1; /* in ns (10^9) */
+
+ if (t2 > timeout_limit)
+ dev_warn(afe->dev, "IRQ handler exceeded time limit by %llu ns\n",
+ t2 - timeout_limit);
+
+ /* clear irq */
+ for (i = 0; i < MT8189_IRQ_NUM; ++i) {
+ if (((cus_status_mcu & BIT(irq_data[i].id)) && i == MT8189_IRQ_31) ||
+ ((status_mcu & BIT(irq_data[i].id)) && i != MT8189_IRQ_31)) {
+ regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg);
+ regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg,
+ AFE_IRQ_CLR_CFG_MASK_SFT |
+ AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
+ tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
+ AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int mt8189_afe_runtime_suspend(struct device *dev)
+{
+ struct mtk_base_afe *afe = dev_get_drvdata(dev);
+ unsigned int value;
+ unsigned int tmp_reg;
+ int ret, i;
+
+ if (!afe->regmap) {
+ dev_warn(afe->dev, "%s() skip regmap\n", __func__);
+ goto skip_regmap;
+ }
+
+ /* disable AFE */
+ mt8189_afe_disable_main_clock(afe);
+
+ ret = regmap_read_poll_timeout(afe->regmap,
+ AUDIO_ENGEN_CON0_MON,
+ value,
+ (value & AUDIO_ENGEN_MON_SFT) == 0,
+ 20,
+ 1 * 1000 * 1000);
+ dev_dbg(afe->dev, "%s() read_poll ret %d\n", __func__, ret);
+ if (ret)
+ dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
+
+ /* make sure all irq status are cleared */
+ for (i = 0; i < MT8189_IRQ_NUM; i++) {
+ regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg);
+ regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg,
+ AFE_IRQ_CLR_CFG_MASK_SFT |
+ AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
+ tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
+ AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
+ }
+
+ /* reset audio 26M request */
+ regmap_update_bits(afe->regmap,
+ AFE_SPM_CONTROL_REQ, 0x1, 0x0);
+
+ /* cache only */
+ regcache_cache_only(afe->regmap, true);
+ regcache_mark_dirty(afe->regmap);
+
+skip_regmap:
+ mt8189_afe_disable_reg_rw_clk(afe);
+ return 0;
+}
+
+static int mt8189_afe_runtime_resume(struct device *dev)
+{
+ struct mtk_base_afe *afe = dev_get_drvdata(dev);
+ int ret;
+
+ ret = mt8189_afe_enable_reg_rw_clk(afe);
+ if (ret)
+ return ret;
+
+ if (!afe->regmap) {
+ dev_warn(afe->dev, "skip regmap\n");
+ return 0;
+ }
+
+ regcache_cache_only(afe->regmap, false);
+ regcache_sync(afe->regmap);
+
+ /* set audio 26M request */
+ regmap_update_bits(afe->regmap, AFE_SPM_CONTROL_REQ, 0x1, 0x1);
+ regmap_update_bits(afe->regmap, AFE_CBIP_CFG0, 0x1, 0x1);
+
+ /* force cpu use 8_24 format when writing 32bit data */
+ regmap_update_bits(afe->regmap, AFE_MEMIF_CON0,
+ CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
+
+ /* enable AFE */
+ mt8189_afe_enable_main_clock(afe);
+
+ return 0;
+}
+
+static int mt8189_afe_component_probe(struct snd_soc_component *component)
+{
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+
+ if (component) {
+ /* enable clock for regcache get default value from hw */
+ pm_runtime_get_sync(afe->dev);
+ mtk_afe_add_sub_dai_control(component);
+ pm_runtime_put_sync(afe->dev);
+ }
+
+ return 0;
+}
+
+static int mt8189_afe_pcm_open(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ /* set the wait_for_avail to 2 sec*/
+ substream->wait_time = msecs_to_jiffies(2 * 1000);
+
+ return 0;
+}
+
+static void mt8189_afe_pcm_free(struct snd_soc_component *component,
+ struct snd_pcm *pcm)
+{
+ snd_pcm_lib_preallocate_free_for_all(pcm);
+}
+
+static const struct snd_soc_component_driver mt8189_afe_component = {
+ .name = AFE_PCM_NAME,
+ .probe = mt8189_afe_component_probe,
+ .pcm_construct = mtk_afe_pcm_new,
+ .pcm_destruct = mt8189_afe_pcm_free,
+ .open = mt8189_afe_pcm_open,
+ .pointer = mtk_afe_pcm_pointer,
+};
+
+static int mt8189_dai_memif_register(struct mtk_base_afe *afe)
+{
+ struct mtk_base_afe_dai *dai;
+
+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+ if (!dai)
+ return -ENOMEM;
+
+ list_add(&dai->list, &afe->sub_dais);
+
+ dai->dai_drivers = mt8189_memif_dai_driver;
+ dai->num_dai_drivers = ARRAY_SIZE(mt8189_memif_dai_driver);
+ dai->dapm_widgets = mt8189_memif_widgets;
+ dai->num_dapm_widgets = ARRAY_SIZE(mt8189_memif_widgets);
+ dai->dapm_routes = mt8189_memif_routes;
+ dai->num_dapm_routes = ARRAY_SIZE(mt8189_memif_routes);
+
+ return 0;
+}
+
+typedef int (*dai_register_cb)(struct mtk_base_afe *);
+static const dai_register_cb dai_register_cbs[] = {
+ mt8189_dai_adda_register,
+ mt8189_dai_i2s_register,
+ mt8189_dai_pcm_register,
+ mt8189_dai_tdm_register,
+ mt8189_dai_memif_register,
+};
+
+static const struct reg_sequence mt8189_cg_patch[] = {
+ { AUDIO_TOP_CON4, 0x361c },
+};
+
+static int mt8189_afe_pcm_dev_probe(struct platform_device *pdev)
+{
+ int ret, i;
+ unsigned int tmp_reg;
+ int irq_id;
+ struct mtk_base_afe *afe;
+ struct mt8189_afe_private *afe_priv;
+ struct device *dev = &pdev->dev;
+
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
+ if (ret)
+ return ret;
+
+ ret = of_reserved_mem_device_init(dev);
+ if (ret)
+ dev_warn(dev, "failed to assign memory region: %d\n", ret);
+
+ afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
+ if (!afe)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, afe);
+
+ afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv),
+ GFP_KERNEL);
+ if (!afe->platform_priv)
+ return -ENOMEM;
+
+ afe_priv = afe->platform_priv;
+ afe->dev = dev;
+
+ afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(afe->base_addr))
+ return dev_err_probe(dev, PTR_ERR(afe->base_addr),
+ "AFE base_addr not found\n");
+
+ /* init audio related clock */
+ ret = mt8189_init_clock(afe);
+ if (ret)
+ return dev_err_probe(dev, ret, "init clock error.\n");
+
+ /* init memif */
+ /* IPM2.0 no need banding */
+ afe->memif_32bit_supported = 1;
+ afe->memif_size = MT8189_MEMIF_NUM;
+ afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
+ GFP_KERNEL);
+
+ if (!afe->memif)
+ return -ENOMEM;
+
+ for (i = 0; i < afe->memif_size; i++) {
+ afe->memif[i].data = &memif_data[i];
+ afe->memif[i].irq_usage = memif_irq_usage[i];
+ afe->memif[i].const_irq = 1;
+ }
+
+ mutex_init(&afe->irq_alloc_lock);
+
+ /* init irq */
+ afe->irqs_size = MT8189_IRQ_NUM;
+ afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
+ GFP_KERNEL);
+
+ if (!afe->irqs)
+ return -ENOMEM;
+
+ for (i = 0; i < afe->irqs_size; i++)
+ afe->irqs[i].irq_data = &irq_data[i];
+
+ /* request irq */
+ irq_id = platform_get_irq(pdev, 0);
+ if (irq_id < 0)
+ return dev_err_probe(dev, irq_id, "no irq found");
+
+ ret = devm_request_irq(dev, irq_id, mt8189_afe_irq_handler,
+ IRQF_TRIGGER_NONE,
+ "Afe_ISR_Handle", afe);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n");
+
+ /* init sub_dais */
+ INIT_LIST_HEAD(&afe->sub_dais);
+
+ for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
+ ret = dai_register_cbs[i](afe);
+ if (ret)
+ return dev_err_probe(dev, ret, "dai register i %d fail\n", i);
+ }
+
+ /* init dai_driver and component_driver */
+ ret = mtk_afe_combine_sub_dai(afe);
+ if (ret)
+ return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
+
+ /* others */
+ afe->mtk_afe_hardware = &mt8189_afe_hardware;
+ afe->memif_fs = mt8189_memif_fs;
+ afe->irq_fs = mt8189_irq_fs;
+ afe->get_dai_fs = mt8189_get_dai_fs;
+ afe->get_memif_pbuf_size = mt8189_get_memif_pbuf_size;
+
+ afe->runtime_resume = mt8189_afe_runtime_resume;
+ afe->runtime_suspend = mt8189_afe_runtime_suspend;
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ /*
+ * Audio device is part of genpd. Registering it as a syscore device
+ * ensure the proper power-on sequence of the AFE device.
+ */
+ dev_pm_syscore_device(dev, true);
+
+ /* enable clock for regcache get default value from hw */
+ pm_runtime_get_sync(dev);
+
+ afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr,
+ &mt8189_afe_regmap_config);
+ if (IS_ERR(afe->regmap))
+ return PTR_ERR(afe->regmap);
+
+ ret = regmap_register_patch(afe->regmap, mt8189_cg_patch,
+ ARRAY_SIZE(mt8189_cg_patch));
+ if (ret < 0) {
+ dev_err(dev, "Failed to apply cg patch\n");
+ goto err_pm_disable;
+ }
+
+ regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg);
+ regmap_write(afe->regmap, AFE_IRQ_MCU_EN, 0xffffffff);
+ regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg);
+
+ pm_runtime_put_sync(dev);
+
+ regcache_cache_only(afe->regmap, true);
+ regcache_mark_dirty(afe->regmap);
+
+ /* register component */
+ ret = devm_snd_soc_register_component(dev,
+ &mt8189_afe_component,
+ afe->dai_drivers,
+ afe->num_dai_drivers);
+ if (ret) {
+ dev_err(dev, "afe component err: %d\n", ret);
+ goto err_pm_disable;
+ }
+
+ return 0;
+
+err_pm_disable:
+ pm_runtime_put_sync(dev);
+ return ret;
+}
+
+static void mt8189_afe_pcm_dev_remove(struct platform_device *pdev)
+{
+ struct mtk_base_afe *afe = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+
+ pm_runtime_put_sync(dev);
+ if (!pm_runtime_status_suspended(dev))
+ mt8189_afe_runtime_suspend(dev);
+
+ mt8189_afe_disable_main_clock(afe);
+ /* disable afe clock */
+ mt8189_afe_disable_reg_rw_clk(afe);
+ of_reserved_mem_device_release(dev);
+}
+
+static const struct of_device_id mt8189_afe_pcm_dt_match[] = {
+ { .compatible = "mediatek,mt8189-afe-pcm", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mt8189_afe_pcm_dt_match);
+
+static const struct dev_pm_ops mt8189_afe_pm_ops = {
+ SET_RUNTIME_PM_OPS(mt8189_afe_runtime_suspend,
+ mt8189_afe_runtime_resume, NULL)
+};
+
+static struct platform_driver mt8189_afe_pcm_driver = {
+ .driver = {
+ .name = "mt8189-afe-pcm",
+ .of_match_table = mt8189_afe_pcm_dt_match,
+ .pm = &mt8189_afe_pm_ops,
+ },
+ .probe = mt8189_afe_pcm_dev_probe,
+ .remove = mt8189_afe_pcm_dev_remove,
+};
+module_platform_driver(mt8189_afe_pcm_driver);
+
+MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8189");
+MODULE_AUTHOR("Darren Ye <darren.ye@mediatek.com>");
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 09/10] ASoC: dt-bindings: mediatek,mt8189-nau8825: add mt8189-nau8825 document
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
` (7 preceding siblings ...)
2025-10-31 7:32 ` [PATCH v3 08/10] ASoC: mediatek: mt8189: add platform driver Cyril Chao
@ 2025-10-31 7:32 ` Cyril Chao
2025-11-03 9:39 ` Krzysztof Kozlowski
2025-10-31 7:32 ` [PATCH v3 10/10] ASoC: mediatek: mt8189: add machine driver with nau8825 Cyril Chao
2025-11-19 2:53 ` [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Mark Brown
10 siblings, 1 reply; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:32 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add document for mt8189 board with nau8825.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
.../sound/mediatek,mt8189-nau8825.yaml | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8189-nau8825.yaml
diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8189-nau8825.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8189-nau8825.yaml
new file mode 100644
index 000000000000..dd9ee0a3b292
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt8189-nau8825.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mediatek,mt8189-nau8825.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8189 ASoC sound card
+
+maintainers:
+ - Darren Ye <darren.ye@mediatek.com>
+ - Cyril Chao <cyril.chao@mediatek.com>
+
+allOf:
+ - $ref: sound-card-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8189-nau8825
+ - mediatek,mt8189-rt5650
+ - mediatek,mt8189-rt5682s
+ - mediatek,mt8189-rt5682i
+ - mediatek,mt8189-es8326
+
+ mediatek,platform:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of MT8189 ASoC platform.
+
+patternProperties:
+ "^dai-link-[0-9]+$":
+ type: object
+ description:
+ Container for dai-link level properties and CODEC sub-nodes.
+
+ properties:
+ link-name:
+ description:
+ This property corresponds to the name of the BE dai-link to which
+ we are going to update parameters in this node.
+ enum:
+ - TDM_DPTX_BE
+ - I2SOUT0_BE
+ - I2SIN0_BE
+ - I2SOUT1_BE
+
+ codec:
+ description: Holds subnode which indicates codec dai.
+ type: object
+ additionalProperties: false
+
+ properties:
+ sound-dai:
+ minItems: 1
+ maxItems: 2
+ required:
+ - sound-dai
+
+ dai-format:
+ description: audio format.
+ enum:
+ - i2s
+ - right_j
+ - left_j
+ - dsp_a
+ - dsp_b
+
+ mediatek,clk-provider:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: Indicates dai-link clock master.
+ enum:
+ - cpu
+ - codec
+
+ additionalProperties: false
+
+ required:
+ - link-name
+
+required:
+ - compatible
+ - mediatek,platform
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sound {
+ compatible = "mediatek,mt8189-nau8825";
+ model = "mt8189_rt9123_8825";
+ mediatek,platform = <&afe>;
+ dai-link-0 {
+ link-name = "I2SOUT1_BE";
+ dai-format = "i2s";
+ mediatek,clk-provider = "cpu";
+ codec {
+ sound-dai = <&nau8825>;
+ };
+ };
+ };
+
+...
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 09/10] ASoC: dt-bindings: mediatek,mt8189-nau8825: add mt8189-nau8825 document
2025-10-31 7:32 ` [PATCH v3 09/10] ASoC: dt-bindings: mediatek,mt8189-nau8825: add mt8189-nau8825 document Cyril Chao
@ 2025-11-03 9:39 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-03 9:39 UTC (permalink / raw)
To: Cyril Chao
Cc: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai, linux-sound, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Fri, Oct 31, 2025 at 03:32:03PM +0800, Cyril Chao wrote:
> + mediatek,platform:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The phandle of MT8189 ASoC platform.
> +
> +patternProperties:
> + "^dai-link-[0-9]+$":
> + type: object
> + description:
> + Container for dai-link level properties and CODEC sub-nodes.
<placeholder (see further)>
> +
> + properties:
> + link-name:
> + description:
> + This property corresponds to the name of the BE dai-link to which
> + we are going to update parameters in this node.
> + enum:
> + - TDM_DPTX_BE
> + - I2SOUT0_BE
> + - I2SIN0_BE
> + - I2SOUT1_BE
> +
> + codec:
> + description: Holds subnode which indicates codec dai.
> + type: object
> + additionalProperties: false
> +
> + properties:
> + sound-dai:
> + minItems: 1
> + maxItems: 2
> + required:
> + - sound-dai
> +
> + dai-format:
> + description: audio format.
> + enum:
> + - i2s
> + - right_j
> + - left_j
> + - dsp_a
> + - dsp_b
> +
> + mediatek,clk-provider:
> + $ref: /schemas/types.yaml#/definitions/string
> + description: Indicates dai-link clock master.
> + enum:
> + - cpu
> + - codec
> +
> + additionalProperties: false
If there is going to be a new version please move this one above to
earlier place - after "description:", to the placeholder place (but of
course keep indentation level, just ordering).
Also
A nit, subject: drop second/last, redundant "document". The
"dt-bindings" prefix is already stating that this is documentation.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
No need to resend just for that.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 10/10] ASoC: mediatek: mt8189: add machine driver with nau8825
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
` (8 preceding siblings ...)
2025-10-31 7:32 ` [PATCH v3 09/10] ASoC: dt-bindings: mediatek,mt8189-nau8825: add mt8189-nau8825 document Cyril Chao
@ 2025-10-31 7:32 ` Cyril Chao
2025-11-19 2:53 ` [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Mark Brown
10 siblings, 0 replies; 13+ messages in thread
From: Cyril Chao @ 2025-10-31 7:32 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group,
Cyril Chao
Add support for mt8189 board with nau8825.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
---
sound/soc/mediatek/Kconfig | 21 +
sound/soc/mediatek/mt8189/Makefile | 3 +
sound/soc/mediatek/mt8189/mt8189-nau8825.c | 1178 ++++++++++++++++++++
3 files changed, 1202 insertions(+)
create mode 100644 sound/soc/mediatek/mt8189/mt8189-nau8825.c
diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index b28648e0d913..3a1e1fa3fe5c 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -256,6 +256,27 @@ config SND_SOC_MT8189
Select Y if you have such device.
If unsure select "N".
+config SND_SOC_MT8189_NAU8825
+ tristate "ASoc Audio driver for MT8189 with NAU8825 and I2S codec"
+ depends on SND_SOC_MT8189
+ depends on I2C
+ select SND_SOC_DMIC
+ select SND_SOC_HDMI_CODEC
+ select SND_SOC_NAU8825
+ select SND_SOC_RT5645
+ select SND_SOC_RT9123P
+ select SND_SOC_RT1015P
+ select SND_SOC_RT5682S
+ select SND_SOC_RT5682_I2C
+ select SND_SOC_CS35L41_I2C
+ select SND_SOC_AW88081
+ select SND_SOC_ES8326
+ help
+ This adds support for ASoC machine driver for MediaTek MT8189
+ boards with the NAU8828 and other I2S audio codecs.
+ Select Y if you have such device.
+ If unsure select "N".
+
config SND_SOC_MT8192
tristate "ASoC support for Mediatek MT8192 chip"
depends on ARCH_MEDIATEK
diff --git a/sound/soc/mediatek/mt8189/Makefile b/sound/soc/mediatek/mt8189/Makefile
index 795b1869bd27..83a033284182 100644
--- a/sound/soc/mediatek/mt8189/Makefile
+++ b/sound/soc/mediatek/mt8189/Makefile
@@ -13,3 +13,6 @@ snd-soc-mt8189-afe-objs += \
mt8189-dai-tdm.o
obj-$(CONFIG_SND_SOC_MT8189) += snd-soc-mt8189-afe.o
+
+# machine driver
+obj-$(CONFIG_SND_SOC_MT8189_NAU8825) += mt8189-nau8825.o
diff --git a/sound/soc/mediatek/mt8189/mt8189-nau8825.c b/sound/soc/mediatek/mt8189/mt8189-nau8825.c
new file mode 100644
index 000000000000..5ef15ec988be
--- /dev/null
+++ b/sound/soc/mediatek/mt8189/mt8189-nau8825.c
@@ -0,0 +1,1178 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * mt8189-nau8825.c -- mt8189 nau8825 ALSA SoC machine driver
+ *
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Darren Ye <darren.ye@mediatek.com>
+ */
+
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <sound/pcm_params.h>
+
+#include "mt8189-afe-common.h"
+
+#include "../common/mtk-soc-card.h"
+#include "../common/mtk-soundcard-driver.h"
+#include "../common/mtk-afe-platform-driver.h"
+
+#include "../../codecs/cs35l41.h"
+#include "../../codecs/nau8825.h"
+#include "../../codecs/rt5682s.h"
+#include "../../codecs/rt5682.h"
+
+#define NAU8825_HS_PRESENT BIT(0)
+#define RT5682S_HS_PRESENT BIT(1)
+#define RT5650_HS_PRESENT BIT(2)
+#define RT5682I_HS_PRESENT BIT(3)
+#define ES8326_HS_PRESENT BIT(4)
+
+/*
+ * Nau88l25
+ */
+#define NAU8825_CODEC_DAI "nau8825-hifi"
+
+/*
+ * Rt5682s
+ */
+#define RT5682S_CODEC_DAI "rt5682s-aif1"
+
+/*
+ * Rt5650
+ */
+#define RT5650_CODEC_DAI "rt5645-aif1"
+
+/*
+ * Rt5682i
+ */
+#define RT5682I_CODEC_DAI "rt5682-aif1"
+
+/*
+ * Cs35l41
+ */
+#define CS35L41_CODEC_DAI "cs35l41-pcm"
+#define CS35L41_DEV0_NAME "cs35l41.7-0040"
+#define CS35L41_DEV1_NAME "cs35l41.7-0042"
+
+/*
+ * ES8326
+ */
+#define ES8326_CODEC_DAI "ES8326 HiFi"
+
+enum mt8189_jacks {
+ MT8189_JACK_HEADSET,
+ MT8189_JACK_DP,
+ MT8189_JACK_HDMI,
+ MT8189_JACK_MAX,
+};
+
+static struct snd_soc_jack_pin mt8189_dp_jack_pins[] = {
+ {
+ .pin = "DP",
+ .mask = SND_JACK_LINEOUT,
+ },
+};
+
+static struct snd_soc_jack_pin mt8189_hdmi_jack_pins[] = {
+ {
+ .pin = "HDMI",
+ .mask = SND_JACK_LINEOUT,
+ },
+};
+
+static struct snd_soc_jack_pin mt8189_headset_jack_pins[] = {
+ {
+ .pin = "Headphone Jack",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ {
+ .pin = "Headset Mic",
+ .mask = SND_JACK_MICROPHONE,
+ },
+};
+
+static const struct snd_kcontrol_new mt8189_dumb_spk_controls[] = {
+ SOC_DAPM_PIN_SWITCH("Ext Spk"),
+};
+
+static const struct snd_soc_dapm_widget mt8189_dumb_spk_widgets[] = {
+ SND_SOC_DAPM_SPK("Ext Spk", NULL),
+};
+
+static const struct snd_soc_dapm_widget mt8189_headset_widgets[] = {
+ SND_SOC_DAPM_HP("Headphone Jack", NULL),
+ SND_SOC_DAPM_MIC("Headset Mic", NULL),
+};
+
+static const struct snd_kcontrol_new mt8189_headset_controls[] = {
+ SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+ SOC_DAPM_PIN_SWITCH("Headset Mic"),
+};
+
+static const struct snd_soc_dapm_widget mt8189_nau8825_card_widgets[] = {
+ SND_SOC_DAPM_SINK("DP"),
+};
+
+static int mt8189_common_i2s_startup(struct snd_pcm_substream *substream)
+{
+ static const unsigned int rates[] = {
+ 48000,
+ };
+ static const struct snd_pcm_hw_constraint_list constraints_rates = {
+ .count = ARRAY_SIZE(rates),
+ .list = rates,
+ };
+
+ return snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE,
+ &constraints_rates);
+}
+
+static int mt8189_common_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ unsigned int rate = params_rate(params);
+ unsigned int mclk_fs_ratio = 128;
+ unsigned int mclk_fs = rate * mclk_fs_ratio;
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+
+ return snd_soc_dai_set_sysclk(cpu_dai,
+ 0, mclk_fs, SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8189_common_i2s_ops = {
+ .startup = mt8189_common_i2s_startup,
+ .hw_params = mt8189_common_i2s_hw_params,
+};
+
+static int mt8189_dptx_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ unsigned int rate = params_rate(params);
+ unsigned int mclk_fs_ratio = 256;
+ unsigned int mclk_fs = rate * mclk_fs_ratio;
+ struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
+
+ return snd_soc_dai_set_sysclk(dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8189_dptx_ops = {
+ .hw_params = mt8189_dptx_hw_params,
+};
+
+static int mt8189_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ dev_dbg(rtd->dev, "%s(), fix format to 32bit\n", __func__);
+
+ /* fix BE i2s format to 32bit, clean param mask first */
+ snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
+ 0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
+
+ params_set_format(params, SNDRV_PCM_FORMAT_S32_LE);
+
+ return 0;
+}
+
+static const struct snd_soc_ops mt8189_pcm_ops = {
+ .startup = mt8189_common_i2s_startup,
+};
+
+static int mt8189_nau8825_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
+ unsigned int rate = params_rate(params);
+ unsigned int bit_width = params_width(params);
+ int clk_freq, ret;
+
+ clk_freq = rate * 2 * bit_width;
+ dev_dbg(codec_dai->dev, "clk_freq %d, rate: %d, bit_width: %d\n",
+ clk_freq, rate, bit_width);
+
+ /* Configure clock for codec */
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8825_CLK_FLL_BLK, 0,
+ SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ dev_err(codec_dai->dev, "can't set BCLK clock %d\n", ret);
+ return ret;
+ }
+
+ /* Configure pll for codec */
+ ret = snd_soc_dai_set_pll(codec_dai, 0, 0, clk_freq,
+ rate * 256);
+ if (ret < 0) {
+ dev_err(codec_dai->dev, "can't set BCLK: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_ops mt8189_nau8825_ops = {
+ .startup = mt8189_common_i2s_startup,
+ .hw_params = mt8189_nau8825_hw_params,
+};
+
+static int mt8189_rtxxxx_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ struct snd_soc_card *card = rtd->card;
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
+ unsigned int rate = params_rate(params);
+ int bitwidth;
+ int ret;
+
+ bitwidth = snd_pcm_format_width(params_format(params));
+ if (bitwidth < 0) {
+ dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
+ return bitwidth;
+ }
+
+ ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
+ if (ret) {
+ dev_err(card->dev, "failed to set tdm slot\n");
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_pll(codec_dai, 0, 1, rate * 32, rate * 512);
+ if (ret) {
+ dev_err(card->dev, "failed to set pll\n");
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, 1, rate * 512, SND_SOC_CLOCK_IN);
+ if (ret) {
+ dev_err(card->dev, "failed to set sysclk\n");
+ return ret;
+ }
+
+ return snd_soc_dai_set_sysclk(cpu_dai, 0, rate * 512,
+ SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8189_rtxxxx_i2s_ops = {
+ .startup = mt8189_common_i2s_startup,
+ .hw_params = mt8189_rtxxxx_i2s_hw_params,
+};
+
+static int mt8189_cs35l41_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ unsigned int rate = params_rate(params);
+ unsigned int mclk_fs = rate * 128;
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai;
+ int clk_freq = rate * 32;
+ int rx_slot[] = {0, 1};
+ int i, ret;
+
+ for_each_rtd_codec_dais(rtd, i, codec_dai) {
+ ret = snd_soc_component_set_sysclk(codec_dai->component,
+ CS35L41_CLKID_SCLK, 0,
+ clk_freq, SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ dev_err(codec_dai->dev, "set component sysclk fail: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CS35L41_CLKID_SCLK,
+ clk_freq, SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ dev_err(codec_dai->dev, "set sysclk fail: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_channel_map(codec_dai, 0, NULL,
+ 1, &rx_slot[i]);
+ if (ret < 0) {
+ dev_err(codec_dai->dev, "set channel map fail: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ return snd_soc_dai_set_sysclk(cpu_dai,
+ 0, mclk_fs, SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8189_cs35l41_i2s_ops = {
+ .startup = mt8189_common_i2s_startup,
+ .hw_params = mt8189_cs35l41_i2s_hw_params,
+};
+
+static int mt8189_es8326_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
+ unsigned int rate = params_rate(params);
+ int ret;
+
+ /* Configure MCLK for codec */
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, rate * 256, SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ dev_err(codec_dai->dev, "can't set MCLK %d\n", ret);
+ return ret;
+ }
+
+ /* Configure MCLK for cpu */
+ return snd_soc_dai_set_sysclk(cpu_dai, 0, rate * 256, SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8189_es8326_ops = {
+ .startup = mt8189_common_i2s_startup,
+ .hw_params = mt8189_es8326_hw_params,
+};
+
+static int mt8189_dumb_amp_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_card *card = rtd->card;
+ int ret;
+
+ ret = snd_soc_dapm_new_controls(&card->dapm, mt8189_dumb_spk_widgets,
+ ARRAY_SIZE(mt8189_dumb_spk_widgets));
+ if (ret) {
+ dev_err(rtd->dev, "unable to add Dumb Speaker dapm, ret %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_add_card_controls(card, mt8189_dumb_spk_controls,
+ ARRAY_SIZE(mt8189_dumb_spk_controls));
+ if (ret) {
+ dev_err(rtd->dev, "unable to add Dumb card controls, ret %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mt8189_dptx_codec_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card);
+ struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8189_JACK_DP];
+ struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
+ int ret;
+
+ ret = snd_soc_card_jack_new_pins(rtd->card, "DP Jack", SND_JACK_LINEOUT,
+ jack, mt8189_dp_jack_pins,
+ ARRAY_SIZE(mt8189_dp_jack_pins));
+ if (ret) {
+ dev_err(rtd->dev, "%s, new jack failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = snd_soc_component_set_jack(component, jack, NULL);
+ if (ret) {
+ dev_err(rtd->dev, "%s, set jack failed on %s (ret=%d)\n",
+ __func__, component->name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mt8189_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card);
+ struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8189_JACK_HDMI];
+ struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
+ int ret;
+
+ ret = snd_soc_card_jack_new_pins(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
+ jack, mt8189_hdmi_jack_pins,
+ ARRAY_SIZE(mt8189_hdmi_jack_pins));
+ if (ret) {
+ dev_err(rtd->dev, "%s, new jack failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = snd_soc_component_set_jack(component, jack, NULL);
+ if (ret) {
+ dev_err(rtd->dev, "%s, set jack failed on %s (ret=%d)\n",
+ __func__, component->name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mt8189_headset_codec_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_card *card = rtd->card;
+ struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(card);
+ struct snd_soc_jack *jack = &soc_card_data->card_data->jacks[MT8189_JACK_HEADSET];
+ struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
+ struct mtk_platform_card_data *card_data = soc_card_data->card_data;
+ int ret;
+ int type;
+
+ ret = snd_soc_dapm_new_controls(&card->dapm, mt8189_headset_widgets,
+ ARRAY_SIZE(mt8189_headset_widgets));
+ if (ret) {
+ dev_err(rtd->dev, "unable to add nau8825 card widget, ret %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_add_card_controls(card, mt8189_headset_controls,
+ ARRAY_SIZE(mt8189_headset_controls));
+ if (ret) {
+ dev_err(rtd->dev, "unable to add nau8825 card controls, ret %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
+ SND_JACK_HEADSET | SND_JACK_BTN_0 |
+ SND_JACK_BTN_1 | SND_JACK_BTN_2 |
+ SND_JACK_BTN_3,
+ jack,
+ mt8189_headset_jack_pins,
+ ARRAY_SIZE(mt8189_headset_jack_pins));
+ if (ret) {
+ dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
+ return ret;
+ }
+
+ if (card_data->flags & ES8326_HS_PRESENT) {
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
+ } else {
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
+ }
+
+ type = SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | SND_JACK_BTN_3;
+ ret = snd_soc_component_set_jack(component, jack, (void *)&type);
+ if (ret) {
+ dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+};
+
+static void mt8189_headset_codec_exit(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component;
+
+ snd_soc_component_set_jack(component, NULL, NULL);
+}
+
+/* FE */
+SND_SOC_DAILINK_DEFS(playback0,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL0")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback1,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback2,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback3,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback4,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL4")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback5,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL5")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback6,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback7,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback8,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback23,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL23")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback24,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL24")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback25,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL25")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback_24ch,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL_24CH")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture0,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL0")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture1,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture2,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture3,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture4,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture5,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture6,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture7,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL7")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture8,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL8")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture9,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL9")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture10,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL10")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture24,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL24")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture25,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL25")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture_cm0,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL_CM0")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture_cm1,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL_CM1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture_etdm_in0,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL_ETDM_IN0")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(capture_etdm_in1,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL_ETDM_IN1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(playback_hdmi,
+ DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+/* BE */
+SND_SOC_DAILINK_DEFS(ap_dmic,
+ DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(ap_dmic_ch34,
+ DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_CH34")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(i2sin0,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2SIN0")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(i2sin1,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2SIN1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(i2sout0,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT0")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(i2sout1,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2SOUT1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(pcm0,
+ DAILINK_COMP_ARRAY(COMP_CPU("PCM 0")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+SND_SOC_DAILINK_DEFS(tdm_dptx,
+ DAILINK_COMP_ARRAY(COMP_CPU("TDM_DPTX")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+static struct snd_soc_dai_link mt8189_nau8825_dai_links[] = {
+ /* Front End DAI links */
+ {
+ .name = "DL0_FE",
+ .stream_name = "DL0 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ .dpcm_merged_format = 1,
+ SND_SOC_DAILINK_REG(playback0),
+ },
+ {
+ .name = "DL1_FE",
+ .stream_name = "DL1 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ .dpcm_merged_format = 1,
+ SND_SOC_DAILINK_REG(playback1),
+ },
+ {
+ .name = "UL0_FE",
+ .stream_name = "UL0 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ .dpcm_merged_format = 1,
+ SND_SOC_DAILINK_REG(capture0),
+ },
+ {
+ .name = "UL1_FE",
+ .stream_name = "UL1 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ .dpcm_merged_format = 1,
+ SND_SOC_DAILINK_REG(capture1),
+ },
+ {
+ .name = "UL2_FE",
+ .stream_name = "UL2 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ .dpcm_merged_format = 1,
+ SND_SOC_DAILINK_REG(capture2),
+ },
+ {
+ .name = "HDMI_FE",
+ .stream_name = "HDMI Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback_hdmi),
+ },
+ {
+ .name = "DL2_FE",
+ .stream_name = "DL2 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback2),
+ },
+ {
+ .name = "DL3_FE",
+ .stream_name = "DL3 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback3),
+ },
+ {
+ .name = "DL4_FE",
+ .stream_name = "DL4 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback4),
+ },
+ {
+ .name = "DL5_FE",
+ .stream_name = "DL5 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback5),
+ },
+ {
+ .name = "DL6_FE",
+ .stream_name = "DL6 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback6),
+ },
+ {
+ .name = "DL7_FE",
+ .stream_name = "DL7 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback7),
+ },
+ {
+ .name = "DL8 FE",
+ .stream_name = "DL8 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback8),
+ },
+ {
+ .name = "DL23 FE",
+ .stream_name = "DL23 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback23),
+ },
+ {
+ .name = "DL24 FE",
+ .stream_name = "DL24 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback24),
+ },
+ {
+ .name = "DL25 FE",
+ .stream_name = "DL25 Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback25),
+ },
+ {
+ .name = "DL_24CH_FE",
+ .stream_name = "DL_24CH Playback",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .playback_only = 1,
+ SND_SOC_DAILINK_REG(playback_24ch),
+ },
+ {
+ .name = "UL9_FE",
+ .stream_name = "UL9 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture9),
+ },
+ {
+ .name = "UL3_FE",
+ .stream_name = "UL3 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture3),
+ },
+ {
+ .name = "UL7_FE",
+ .stream_name = "UL7 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture7),
+ },
+ {
+ .name = "UL4_FE",
+ .stream_name = "UL4 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture4),
+ },
+ {
+ .name = "UL5_FE",
+ .stream_name = "UL5 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture5),
+ },
+ {
+ .name = "UL_CM0_FE",
+ .stream_name = "UL_CM0 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture_cm0),
+ },
+ {
+ .name = "UL_CM1_FE",
+ .stream_name = "UL_CM1 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture_cm1),
+ },
+ {
+ .name = "UL10_FE",
+ .stream_name = "UL10 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture10),
+ },
+ {
+ .name = "UL6_FE",
+ .stream_name = "UL6 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture6),
+ },
+ {
+ .name = "UL25_FE",
+ .stream_name = "UL25 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture25),
+ },
+ {
+ .name = "UL8_FE",
+ .stream_name = "UL8 Capture_Mono_1",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture8),
+ },
+ {
+ .name = "UL24_FE",
+ .stream_name = "UL24 Capture_Mono_2",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture24),
+ },
+ {
+ .name = "UL_ETDM_In0_FE",
+ .stream_name = "UL_ETDM_In0 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture_etdm_in0),
+ },
+ {
+ .name = "UL_ETDM_In1_FE",
+ .stream_name = "UL_ETDM_In1 Capture",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .capture_only = 1,
+ SND_SOC_DAILINK_REG(capture_etdm_in1),
+ },
+ /* Back End DAI links */
+ {
+ .name = "I2SIN0_BE",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBC_CFC
+ | SND_SOC_DAIFMT_GATED,
+ .ops = &mt8189_common_i2s_ops,
+ .no_pcm = 1,
+ .capture_only = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(i2sin0),
+ },
+ {
+ .name = "I2SIN1_BE",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBC_CFC
+ | SND_SOC_DAIFMT_GATED,
+ .ops = &mt8189_common_i2s_ops,
+ .no_pcm = 1,
+ .capture_only = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(i2sin1),
+ },
+ {
+ .name = "I2SOUT0_BE",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBC_CFC
+ | SND_SOC_DAIFMT_GATED,
+ .ops = &mt8189_common_i2s_ops,
+ .no_pcm = 1,
+ .playback_only = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(i2sout0),
+ },
+ {
+ .name = "I2SOUT1_BE",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBC_CFC
+ | SND_SOC_DAIFMT_GATED,
+ .ops = &mt8189_common_i2s_ops,
+ .no_pcm = 1,
+ .playback_only = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(i2sout1),
+ },
+ {
+ .name = "AP_DMIC_BE",
+ .no_pcm = 1,
+ .capture_only = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(ap_dmic),
+ },
+ {
+ .name = "AP_DMIC_CH34_BE",
+ .no_pcm = 1,
+ .capture_only = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(ap_dmic_ch34),
+ },
+ {
+ .name = "TDM_DPTX_BE",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBC_CFC
+ | SND_SOC_DAIFMT_GATED,
+ .ops = &mt8189_dptx_ops,
+ .be_hw_params_fixup = mt8189_dptx_hw_params_fixup,
+ .no_pcm = 1,
+ .playback_only = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(tdm_dptx),
+ },
+ {
+ .name = "PCM_0_BE",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBC_CFC
+ | SND_SOC_DAIFMT_GATED,
+ .no_pcm = 1,
+ .ops = &mt8189_pcm_ops,
+ .playback_only = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(pcm0),
+ },
+};
+
+static struct snd_soc_codec_conf mt8189_cs35l41_codec_conf[] = {
+ {
+ .dlc = COMP_CODEC_CONF(CS35L41_DEV0_NAME),
+ .name_prefix = "Right",
+ },
+ {
+ .dlc = COMP_CODEC_CONF(CS35L41_DEV1_NAME),
+ .name_prefix = "Left",
+ },
+};
+
+static int mt8189_nau8825_soc_card_probe(struct mtk_soc_card_data *soc_card_data, bool legacy)
+{
+ struct snd_soc_card *card = soc_card_data->card_data->card;
+ struct snd_soc_dai_link *dai_link;
+ bool init_nau8825 = false;
+ bool init_rt5682s = false;
+ bool init_rt5650 = false;
+ bool init_rt5682i = false;
+ bool init_es8326 = false;
+ bool init_dumb = false;
+ int i;
+
+ for_each_card_prelinks(card, i, dai_link) {
+ if (strcmp(dai_link->name, "TDM_DPTX_BE") == 0) {
+ if (dai_link->num_codecs &&
+ strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai"))
+ dai_link->init = mt8189_dptx_codec_init;
+ } else if (strcmp(dai_link->name, "PCM_0_BE") == 0) {
+ if (dai_link->num_codecs &&
+ strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai"))
+ dai_link->init = mt8189_hdmi_codec_init;
+ } else if (strcmp(dai_link->name, "I2SOUT0_BE") == 0 ||
+ strcmp(dai_link->name, "I2SIN0_BE") == 0) {
+ if (!strcmp(dai_link->codecs->dai_name, NAU8825_CODEC_DAI)) {
+ dai_link->ops = &mt8189_nau8825_ops;
+ if (!init_nau8825) {
+ dai_link->init = mt8189_headset_codec_init;
+ dai_link->exit = mt8189_headset_codec_exit;
+ init_nau8825 = true;
+ }
+ } else if (!strcmp(dai_link->codecs->dai_name, RT5682S_CODEC_DAI)) {
+ dai_link->ops = &mt8189_rtxxxx_i2s_ops;
+ if (!init_rt5682s) {
+ dai_link->init = mt8189_headset_codec_init;
+ dai_link->exit = mt8189_headset_codec_exit;
+ init_rt5682s = true;
+ }
+ } else if (!strcmp(dai_link->codecs->dai_name, RT5650_CODEC_DAI)) {
+ dai_link->ops = &mt8189_rtxxxx_i2s_ops;
+ if (!init_rt5650) {
+ dai_link->init = mt8189_headset_codec_init;
+ dai_link->exit = mt8189_headset_codec_exit;
+ init_rt5650 = true;
+ }
+ } else if (!strcmp(dai_link->codecs->dai_name, RT5682I_CODEC_DAI)) {
+ dai_link->ops = &mt8189_rtxxxx_i2s_ops;
+ if (!init_rt5682i) {
+ dai_link->init = mt8189_headset_codec_init;
+ dai_link->exit = mt8189_headset_codec_exit;
+ init_rt5682i = true;
+ }
+ } else if (!strcmp(dai_link->codecs->dai_name, ES8326_CODEC_DAI)) {
+ dai_link->ops = &mt8189_es8326_ops;
+ if (!init_es8326) {
+ dai_link->init = mt8189_headset_codec_init;
+ dai_link->exit = mt8189_headset_codec_exit;
+ init_es8326 = true;
+ }
+ } else {
+ if (strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai")) {
+ if (!init_dumb) {
+ dai_link->init = mt8189_dumb_amp_init;
+ init_dumb = true;
+ }
+ }
+ }
+ } else if (strcmp(dai_link->name, "I2SOUT1_BE") == 0) {
+ if (!strcmp(dai_link->codecs->dai_name, CS35L41_CODEC_DAI)) {
+ dai_link->ops = &mt8189_cs35l41_i2s_ops;
+ card->num_configs = ARRAY_SIZE(mt8189_cs35l41_codec_conf);
+ card->codec_conf = mt8189_cs35l41_codec_conf;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static struct snd_soc_card mt8189_nau8825_soc_card = {
+ .owner = THIS_MODULE,
+ .dai_link = mt8189_nau8825_dai_links,
+ .num_links = ARRAY_SIZE(mt8189_nau8825_dai_links),
+ .dapm_widgets = mt8189_nau8825_card_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(mt8189_nau8825_card_widgets),
+};
+
+static const struct mtk_soundcard_pdata mt8189_nau8825_card = {
+ .card_name = "mt8189_nau8825",
+ .card_data = &(struct mtk_platform_card_data) {
+ .card = &mt8189_nau8825_soc_card,
+ .num_jacks = MT8189_JACK_MAX,
+ .flags = NAU8825_HS_PRESENT
+ },
+ .sof_priv = NULL,
+ .soc_probe = mt8189_nau8825_soc_card_probe,
+};
+
+static const struct mtk_soundcard_pdata mt8189_rt5650_card = {
+ .card_name = "mt8189_rt5650",
+ .card_data = &(struct mtk_platform_card_data) {
+ .card = &mt8189_nau8825_soc_card,
+ .num_jacks = MT8189_JACK_MAX,
+ .flags = RT5650_HS_PRESENT
+ },
+ .sof_priv = NULL,
+ .soc_probe = mt8189_nau8825_soc_card_probe,
+};
+
+static const struct mtk_soundcard_pdata mt8189_rt5682s_card = {
+ .card_name = "mt8189_rt5682s",
+ .card_data = &(struct mtk_platform_card_data) {
+ .card = &mt8189_nau8825_soc_card,
+ .num_jacks = MT8189_JACK_MAX,
+ .flags = RT5682S_HS_PRESENT
+ },
+ .sof_priv = NULL,
+ .soc_probe = mt8189_nau8825_soc_card_probe,
+};
+
+static const struct mtk_soundcard_pdata mt8189_rt5682i_card = {
+ .card_name = "mt8189_rt5682i",
+ .card_data = &(struct mtk_platform_card_data) {
+ .card = &mt8189_nau8825_soc_card,
+ .num_jacks = MT8189_JACK_MAX,
+ .flags = RT5682I_HS_PRESENT
+ },
+ .sof_priv = NULL,
+ .soc_probe = mt8189_nau8825_soc_card_probe,
+};
+
+static const struct mtk_soundcard_pdata mt8188_es8326_card = {
+ .card_name = "mt8188_es8326",
+ .card_data = &(struct mtk_platform_card_data) {
+ .card = &mt8189_nau8825_soc_card,
+ .num_jacks = MT8189_JACK_MAX,
+ .flags = ES8326_HS_PRESENT
+ },
+ .sof_priv = NULL,
+ .soc_probe = mt8189_nau8825_soc_card_probe,
+};
+
+static const struct of_device_id mt8189_nau8825_dt_match[] = {
+ {.compatible = "mediatek,mt8189-nau8825", .data = &mt8189_nau8825_card,},
+ {.compatible = "mediatek,mt8189-rt5650", .data = &mt8189_rt5650_card,},
+ {.compatible = "mediatek,mt8189-rt5682s", .data = &mt8189_rt5682s_card,},
+ {.compatible = "mediatek,mt8189-rt5682i", .data = &mt8189_rt5682i_card,},
+ {.compatible = "mediatek,mt8189-es8326", .data = &mt8188_es8326_card,},
+ {}
+};
+MODULE_DEVICE_TABLE(of, mt8189_nau8825_dt_match);
+
+static struct platform_driver mt8189_nau8825_driver = {
+ .driver = {
+ .name = "mt8189-nau8825",
+ .of_match_table = mt8189_nau8825_dt_match,
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = mtk_soundcard_common_probe,
+};
+module_platform_driver(mt8189_nau8825_driver);
+
+/* Module information */
+MODULE_DESCRIPTION("MT8189 NAU8825 ALSA SoC machine driver");
+MODULE_AUTHOR("Darren Ye <darren.ye@mediatek.com>");
+MODULE_AUTHOR("Cyril Chao <cyril.chao@mediatek.com>");
+MODULE_LICENSE("GPL");
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC
2025-10-31 7:31 [PATCH v3 00/10] ASoC: mediatek: Add support for MT8189 SoC Cyril Chao
` (9 preceding siblings ...)
2025-10-31 7:32 ` [PATCH v3 10/10] ASoC: mediatek: mt8189: add machine driver with nau8825 Cyril Chao
@ 2025-11-19 2:53 ` Mark Brown
10 siblings, 0 replies; 13+ messages in thread
From: Mark Brown @ 2025-11-19 2:53 UTC (permalink / raw)
To: Liam Girdwood, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, Jaroslav Kysela,
Takashi Iwai, Cyril Chao
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Cyril Chao, Project_Global_Chrome_Upstream_Group
On Fri, 31 Oct 2025 15:31:54 +0800, Cyril Chao wrote:
> Based on tag: next-20251031, linux-next/master
>
> This series of patches adds support for Mediatek AFE of MT8189 SoC.
> Patches are based on broonie tree "for-next" branch.
>
> Changes in v3:
> - Added support for CS35L codec in the machine driver.
> - Added I2SOUT0/I2SOUT1 MCLK configuration and enabled the clocks.
> - Added dpcm_merged_format flag to the dai-link to ensure codec
> format constraints are applied.
> - Added support for ES8326 codec in the machine driver.
> - Updated the dt-bindings description based on reviewer comments.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[01/10] ASoC: mediatek: mt8189: add common header
commit: 81f8f29a48defd572ec34d2b9c84374fd05158cc
[02/10] ASoC: mediatek: mt8189: support audio clock control
commit: dc637ffeed6c32c951520774897601ebd9ffc3d5
[03/10] ASoC: mediatek: mt8189: support ADDA in platform driver
commit: e3acef6ef89ffbd6c80950d5fa0d024a8d11c1c4
[04/10] ASoC: mediatek: mt8189: support I2S in platform driver
commit: 34e437097247f92fba6fac3d6e40e33af5f32e3d
[05/10] ASoC: mediatek: mt8189: support TDM in platform driver
commit: 9f202872ba04d71c96908c56abcc6e3f4a629a40
[06/10] ASoC: mediatek: mt8189: support PCM in platform driver
commit: 402ff043395fd9444810c723056fe741c77dbc21
[07/10] ASoC: dt-bindings: mediatek,mt8189-afe-pcm: add audio afe document
commit: 22e9bd51e518e8fcad269c0c1f4bd84467db093e
[08/10] ASoC: mediatek: mt8189: add platform driver
commit: 7eb1535855983f67b95c2ba777d686cc17188285
[09/10] ASoC: dt-bindings: mediatek,mt8189-nau8825: add mt8189-nau8825 document
commit: 4980df101676f598ad515725a94424d244a5c5a3
[10/10] ASoC: mediatek: mt8189: add machine driver with nau8825
commit: d218ea171430e49412804efb794942dd121a8032
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply [flat|nested] 13+ messages in thread