[PATCH 06/13] ARM: dts: rv1108: Add GMAC support

[PATCH 06/13] ARM: dts: rv1108: Add GMAC support

[Otavio Salvador]

Add GMAC support for RV1108.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 36 +++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 4f4275599f7a..c7a26f82655b 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -516,6 +516,27 @@
 		status = "disabled";
 	};
 
+	gmac: eth@30200000 {
+		compatible = "rockchip,rv1108-gmac";
+		reg = <0x30200000 0x10000>;
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "macirq", "eth_wake_irq";
+		clocks = <&cru SCLK_MAC>,
+			<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
+			<&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
+			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+		clock-names = "stmmaceth",
+			"mac_clk_rx", "mac_clk_tx",
+			"clk_mac_ref", "clk_mac_refout",
+			"aclk_mac", "pclk_mac";
+		phy-mode = "rmii";
+		pinctrl-names = "default";
+		pinctrl-0 = <&rmii_pins>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@32010000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
@@ -641,6 +662,21 @@
 			input-enable;
 		};
 
+		gmac {
+			rmii_pins: rmii-pins {
+				rockchip,pins =	<1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
+						<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
+						<1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
+						<1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
+						<1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
+						<1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
+						<1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
+						<1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
+						<1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
+						<1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
+			};
+		};
+
 		i2c0 {
 			i2c0_xfer: i2c0-xfer {
 				rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
-- 
2.19.1

[PATCH 07/13] ARM: dts: rv1108: Fix the timer mask

[Otavio Salvador]

As done in the Rockchip vendor tree and also on other
"arm,armv7-timer" instances, the correct GIC_CPU_MASK_SIMPLE mask
is 4 instead of 1.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index c7a26f82655b..7b331766120d 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -71,8 +71,8 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		clock-frequency = <24000000>;
 	};
 
-- 
2.19.1

[PATCH 08/13] ARM: dts: rv1108: Fix the PMU interrupt number

[Otavio Salvador]

According to the Rockchip vendor tree the PMU interrupt number is
76, so fix it accordingly.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 7b331766120d..442b749eb2e9 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -66,7 +66,7 @@
 
 	arm-pmu {
 		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	timer {
-- 
2.19.1

[PATCH 09/13] ARM: dts: rv1108: Assign the proper GPIO clocks

[Otavio Salvador]

It is not correct to assign the 24MHz clock oscillator to the GPIO
ports.

Fix it by assigning the proper GPIO clocks instead.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 442b749eb2e9..ce5509c4657b 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -562,7 +562,7 @@
 			compatible = "rockchip,gpio-bank";
 			reg = <0x20030000 0x100>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&xin24m>;
+			clocks = <&cru PCLK_GPIO0_PMU>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -575,7 +575,7 @@
 			compatible = "rockchip,gpio-bank";
 			reg = <0x10310000 0x100>;
 			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&xin24m>;
+			clocks = <&cru PCLK_GPIO1>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -588,7 +588,7 @@
 			compatible = "rockchip,gpio-bank";
 			reg = <0x10320000 0x100>;
 			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&xin24m>;
+			clocks = <&cru PCLK_GPIO2>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -601,7 +601,7 @@
 			compatible = "rockchip,gpio-bank";
 			reg = <0x10330000 0x100>;
 			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&xin24m>;
+			clocks = <&cru PCLK_GPIO3>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
-- 
2.19.1

[PATCH 10/13] ARM: dts: rv1108: Add UART DMA support

[Otavio Salvador]

Pass the 'dmas' property to the UART ports so that DMA can
be supported.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index ce5509c4657b..7ef6d965871c 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -114,6 +114,8 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
+		dmas = <&pdma 6>, <&pdma 7>;
+		#dma-cells = <2>;
 		clock-frequency = <24000000>;
 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 		clock-names = "baudclk", "apb_pclk";
@@ -128,6 +130,8 @@
 		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
+		dmas = <&pdma 4>, <&pdma 5>;
+		#dma-cells = <2>;
 		clock-frequency = <24000000>;
 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 		clock-names = "baudclk", "apb_pclk";
@@ -142,6 +146,8 @@
 		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
+		dmas = <&pdma 2>, <&pdma 3>;
+		#dma-cells = <2>;
 		clock-frequency = <24000000>;
 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 		clock-names = "baudclk", "apb_pclk";
-- 
2.19.1

[PATCH 11/13] ARM: dts: rv1108: Add internal timer support

[Otavio Salvador]

Add support for the internal timer peripheral on RV1108.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 7ef6d965871c..42566adadc83 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -291,6 +291,14 @@
 		};
 	};
 
+	timer: timer@10350000 {
+		compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
+		reg = <0x10350000 0x20>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&xin24m>, <&cru PCLK_TIMER>;
+		clock-names = "timer", "pclk";
+	};
+
 	watchdog: wdt@10360000 {
 		compatible = "snps,dw-wdt";
 		reg = <0x10360000 0x100>;
-- 
2.19.1

[PATCH 12/13] ARM: dts: rv1108: Pass the 'arm,cpu-registers-not-fw-configured' property

[Otavio Salvador]

Since firmware does not initialize  any of the generic timer CPU
registers pass the 'arm,cpu-registers-not-fw-configured' property as
suggested in Documentation/devicetree/bindings/timer/arm,arch_timer.txt.

This also aligns with other Rockchip SoC dtsi files.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 42566adadc83..d96c58728b28 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -71,6 +71,7 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
+		arm,cpu-registers-not-fw-configured;
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		clock-frequency = <24000000>;
-- 
2.19.1

[PATCH 13/13] ARM: dts: rv1108: Pass the 'clock-latency' property

[Otavio Salvador]

Like it is done on cpu nodes of other Rockchip SoCs, pass the
'clock-latency' property to the CPU node, so that cpufreq driver
can take the latency into account when switching frequencies.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---

 arch/arm/boot/dts/rv1108.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index d96c58728b28..4e1ca13a1636 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -36,6 +36,7 @@
 			#cooling-cells = <2>; /* min followed by max */
 			dynamic-power-coefficient = <75>;
 			operating-points-v2 = <&cpu_opp_table>;
+			clock-latency = <40000>;
 		};
 	};
 
-- 
2.19.1

Re: [PATCH 07/13] ARM: dts: rv1108: Fix the timer mask

[Heiko Stuebner]

Am Sonntag, 25. November 2018, 22:19:01 CET schrieb Otavio Salvador:
> As done in the Rockchip vendor tree and also on other
> "arm,armv7-timer" instances, the correct GIC_CPU_MASK_SIMPLE mask
> is 4 instead of 1.

Nope. That value represents the number of cores in the system.
As the rv1108 only has one core, that should likely stay as it is.

Also, it seems I only got patches 6-13 what happened to 1-5?

Heiko

> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
> ---
> 
>  arch/arm/boot/dts/rv1108.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
> index c7a26f82655b..7b331766120d 100644
> --- a/arch/arm/boot/dts/rv1108.dtsi
> +++ b/arch/arm/boot/dts/rv1108.dtsi
> @@ -71,8 +71,8 @@
>  
>  	timer {
>  		compatible = "arm,armv7-timer";
> -		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
> -			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>  		clock-frequency = <24000000>;
>  	};
>  
> 

Re: [PATCH 08/13] ARM: dts: rv1108: Fix the PMU interrupt number

[Heiko Stuebner]

Hi Otavio,

Am Sonntag, 25. November 2018, 22:19:02 CET schrieb Otavio Salvador:
> According to the Rockchip vendor tree the PMU interrupt number is
> 76, so fix it accordingly.
> 
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>

looks ok, especially as the TRM I have doesn't list neither irqs :-)
But please explain the second Signed-off by Fabio?

If Fabio is the original author, the patch From should reflect that
and the Signed-off-by lines should be swapped. As it is now
I would expect Fabio being the one sending the patches.
Or is it supposed to be a "Co-developed-by:"?
See Documentation/process/5.Posting.rst.


Thanks
Heiko

Re: [PATCH 11/13] ARM: dts: rv1108: Add internal timer support

[Heiko Stuebner]

Hi,

Am Sonntag, 25. November 2018, 22:19:05 CET schrieb Otavio Salvador:
> Add support for the internal timer peripheral on RV1108.
> 
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> ---
> 
>  arch/arm/boot/dts/rv1108.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
> index 7ef6d965871c..42566adadc83 100644
> --- a/arch/arm/boot/dts/rv1108.dtsi
> +++ b/arch/arm/boot/dts/rv1108.dtsi
> @@ -291,6 +291,14 @@
>  		};
>  	};
>  
> +	timer: timer@10350000 {
> +		compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";

please also document that new compatible string in
Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt


Heiko

Re: [PATCH 06/13] ARM: dts: rv1108: Add GMAC support

[Heiko Stuebner]

Am Sonntag, 25. November 2018, 22:19:00 CET schrieb Otavio Salvador:
> Add GMAC support for RV1108.
> 
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

applied for 4.21 after modifying the subject a bit and adding
a comment explaining that the rv1108 only has that rmii interface.

While the dwmac is definitly a big improvement over the arc-emac
it is still surprising that the gbit mac only gets a 100mbit phy interface.


Heiko

Re: [PATCH 13/13] ARM: dts: rv1108: Pass the 'clock-latency' property

[Heiko Stuebner]

Am Sonntag, 25. November 2018, 22:19:07 CET schrieb Otavio Salvador:
> Like it is done on cpu nodes of other Rockchip SoCs, pass the
> 'clock-latency' property to the CPU node, so that cpufreq driver
> can take the latency into account when switching frequencies.
> 
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

applied for 4.21 after adapting the subject and moving the property
to its correct alphabetical position in the node.


Thanks
Heiko

Re: [PATCH 12/13] ARM: dts: rv1108: Pass the 'arm,cpu-registers-not-fw-configured' property

[Heiko Stuebner]

Am Sonntag, 25. November 2018, 22:19:06 CET schrieb Otavio Salvador:
> Since firmware does not initialize  any of the generic timer CPU
> registers pass the 'arm,cpu-registers-not-fw-configured' property as
> suggested in Documentation/devicetree/bindings/timer/arm,arch_timer.txt.
> 
> This also aligns with other Rockchip SoC dtsi files.
> 
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

applied for 4.21 after adapting the subject a bit.


Thanks
Heiko

Re: [PATCH 08/13] ARM: dts: rv1108: Fix the PMU interrupt number

[Otavio Salvador]

Hello Heiko,

On Mon, Nov 26, 2018 at 3:59 AM Heiko Stuebner <heiko@sntech.de> wrote:
> Am Sonntag, 25. November 2018, 22:19:02 CET schrieb Otavio Salvador:
> > According to the Rockchip vendor tree the PMU interrupt number is
> > 76, so fix it accordingly.
> >
> > Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> > Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
>
> looks ok, especially as the TRM I have doesn't list neither irqs :-)
> But please explain the second Signed-off by Fabio?
>
> If Fabio is the original author, the patch From should reflect that
> and the Signed-off-by lines should be swapped. As it is now
> I would expect Fabio being the one sending the patches.
> Or is it supposed to be a "Co-developed-by:"?
> See Documentation/process/5.Posting.rst.

He works with me and he applied and tested it in our internal tree for
our customer. He reviewed and tested this with me, so I'd like to
provide him credit as well.

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854          Mobile: +1 (347) 903-9750

Re: [PATCH 07/13] ARM: dts: rv1108: Fix the timer mask

[Otavio Salvador]

On Mon, Nov 26, 2018 at 3:27 AM Heiko Stuebner <heiko@sntech.de> wrote:
> Am Sonntag, 25. November 2018, 22:19:01 CET schrieb Otavio Salvador:
> > As done in the Rockchip vendor tree and also on other
> > "arm,armv7-timer" instances, the correct GIC_CPU_MASK_SIMPLE mask
> > is 4 instead of 1.
>
> Nope. That value represents the number of cores in the system.
> As the rv1108 only has one core, that should likely stay as it is.

I see, I will drop it for v2.

> Also, it seems I only got patches 6-13 what happened to 1-5?

It went to other mailing lists, I think. I will add you on Cc to all for v2.

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854          Mobile: +1 (347) 903-9750

Re: [PATCH 08/13] ARM: dts: rv1108: Fix the PMU interrupt number

[Heiko Stuebner]

Am Montag, 26. November 2018, 14:36:01 CET schrieb Otavio Salvador:
> Hello Heiko,
> 
> On Mon, Nov 26, 2018 at 3:59 AM Heiko Stuebner <heiko@sntech.de> wrote:
> > Am Sonntag, 25. November 2018, 22:19:02 CET schrieb Otavio Salvador:
> > > According to the Rockchip vendor tree the PMU interrupt number is
> > > 76, so fix it accordingly.
> > >
> > > Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> > > Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
> >
> > looks ok, especially as the TRM I have doesn't list neither irqs :-)
> > But please explain the second Signed-off by Fabio?
> >
> > If Fabio is the original author, the patch From should reflect that
> > and the Signed-off-by lines should be swapped. As it is now
> > I would expect Fabio being the one sending the patches.
> > Or is it supposed to be a "Co-developed-by:"?
> > See Documentation/process/5.Posting.rst.
> 
> He works with me and he applied and tested it in our internal tree for
> our customer. He reviewed and tested this with me, so I'd like to
> provide him credit as well.

Reviewed-by:
Tested-by:

perhaps then? :-)


Heiko