From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m82213657.xmail.ntesmail.com (mail-m82213657.xmail.ntesmail.com [8.221.36.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2A0A20125F; Fri, 16 Jan 2026 01:01:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=8.221.36.57 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768525286; cv=none; b=ZPlsYgAhD/9BMSgCxb5kc0yIV49JKF0z5qT7brlxzpu1buP62I6+6kt8Z3I5bF7O4kjDmVlLon4Nki3GnxkGQir2kv1l6dwiTBSk4wfTNSSu0IsCrlyZ2RaakBGTGbHQtHgKOmL9p2MIkdnlfai/lM/Pi5lGZHjqm9cN+N+/1so= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768525286; c=relaxed/simple; bh=ItFwumyOI+0Q0HJ2MQBO3rwdZbnpz2orjqEqRBpPams=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=kNlL2QadFRyTHizBe9uUEVamKpK4PNv0dTh2byr/COeAbDwnMWtTFX6Iz1EItOXc6iJ9x4PY342zteLUoGHTDv2eZEgVPbCKX03nAxxGFuBG9YwSTCEhb7v7lbxVsy8WnqfSYfaTOpy84gTSgcd7B23BUvosQD0ubYkL3+DcABY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=cn2q+pBX; arc=none smtp.client-ip=8.221.36.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="cn2q+pBX" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 30d5a76b5; Fri, 16 Jan 2026 08:55:58 +0800 (GMT+08:00) From: Shawn Lin To: Heiko Stuebner , Ulf Hansson Cc: linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, FUKAUMI Naoki , Marco Schirrmeister , John Clark , Tianling Shen , Detlev Casanova , Shawn Lin Subject: [PATCH v4 3/5] mmc: dw_mmc-rockchip: Fix runtime PM support for internal phase support Date: Fri, 16 Jan 2026 08:55:30 +0800 Message-Id: <1768524932-163929-4-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1768524932-163929-1-git-send-email-shawn.lin@rock-chips.com> References: <1768524932-163929-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Tid: 0a9bc44d49ba09cckunm67a197c8691bf9 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhoYS1YZSUxCSkJCTx9CSkhWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=cn2q+pBXzH8PPm0DJPSFzeewkBw5/2FjgWROFXyful9U9I970ROifthHNseNkFnzLwMuIqu/Oot6nVrOerDkZogR9bzFdNcOhL6zn1EkXzMzqeanbhGIC1u1PeRkIIb1O9KQnyAB2Dut5xDyPxAVeuBSnTdxcGP9/qeP4FrwSLY=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=nAxcwtoR+PZuKKJSWxlt9Mjgw/ELV6cayHnxUmZ3BKE=; h=date:mime-version:subject:message-id:from; Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: RK3576 is the first platform to introduce internal phase support, and subsequent platforms are expected to adopt a similar design. In this architecture, runtime suspend powers off the attached power domain, which resets registers, including vendor-specific ones such as SDMMC_TIMING_CON0, SDMMC_TIMING_CON1, and SDMMC_MISC_CON. These registers must be saved and restored, a requirement that falls outside the scope of the dw_mmc core. Fixes: 59903441f5e4 ("mmc: dw_mmc-rockchip: Add internal phase support") Signed-off-by: Shawn Lin Tested-by: Marco Schirrmeister --- Changes in v3: None Changes in v2: None drivers/mmc/host/dw_mmc-rockchip.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 879188f..2fe0896 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -36,6 +36,8 @@ struct dw_mci_rockchip_priv_data { int default_sample_phase; int num_phases; bool internal_phase; + int sample_phase; + int drv_phase; }; /* @@ -573,9 +575,43 @@ static void dw_mci_rockchip_remove(struct platform_device *pdev) dw_mci_pltfm_remove(pdev); } +static int dw_mci_rockchip_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct dw_mci *host = platform_get_drvdata(pdev); + struct dw_mci_rockchip_priv_data *priv = host->priv; + + if (priv->internal_phase) { + priv->sample_phase = rockchip_mmc_get_phase(host, true); + priv->drv_phase = rockchip_mmc_get_phase(host, false); + } + + return dw_mci_runtime_suspend(dev); +} + +static int dw_mci_rockchip_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct dw_mci *host = platform_get_drvdata(pdev); + struct dw_mci_rockchip_priv_data *priv = host->priv; + int ret; + + ret = dw_mci_runtime_resume(dev); + if (ret) + return ret; + + if (priv->internal_phase) { + rockchip_mmc_set_phase(host, true, priv->sample_phase); + rockchip_mmc_set_phase(host, false, priv->drv_phase); + mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE); + } + + return ret; +} + static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = { SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) - RUNTIME_PM_OPS(dw_mci_runtime_suspend, dw_mci_runtime_resume, NULL) + RUNTIME_PM_OPS(dw_mci_rockchip_runtime_suspend, dw_mci_rockchip_runtime_resume, NULL) }; static struct platform_driver dw_mci_rockchip_pltfm_driver = { -- 2.7.4